1 /* Auto-generated config file peripheral_clk_config.h */ 2 #ifndef PERIPHERAL_CLK_CONFIG_H 3 #define PERIPHERAL_CLK_CONFIG_H 4 5 // <<< Use Configuration Wizard in Context Menu >>> 6 7 // <y> ADC Clock Source 8 // <id> adc_gclk_selection 9 10 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 11 12 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 13 14 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 15 16 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 17 18 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 19 20 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 21 22 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 23 24 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 25 26 // <i> Select the clock source for ADC. 27 #ifndef CONF_GCLK_ADC0_SRC 28 #define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 29 #endif 30 31 /** 32 * \def CONF_GCLK_ADC0_FREQUENCY 33 * \brief ADC0's Clock frequency 34 */ 35 #ifndef CONF_GCLK_ADC0_FREQUENCY 36 #define CONF_GCLK_ADC0_FREQUENCY 40001536 37 #endif 38 39 /** 40 * \def CONF_CPU_FREQUENCY 41 * \brief CPU's Clock frequency 42 */ 43 #ifndef CONF_CPU_FREQUENCY 44 #define CONF_CPU_FREQUENCY 40001536 45 #endif 46 47 // <y> Core Clock Source 48 // <id> core_gclk_selection 49 50 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 51 52 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 53 54 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 55 56 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 57 58 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 59 60 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 61 62 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 63 64 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 65 66 // <i> Select the clock source for CORE. 67 #ifndef CONF_GCLK_SERCOM0_CORE_SRC 68 #define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 69 #endif 70 71 // <y> Slow Clock Source 72 // <id> slow_gclk_selection 73 74 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 75 76 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 77 78 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 79 80 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 81 82 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 83 84 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 85 86 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 87 88 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 89 90 // <i> Select the slow clock source. 91 #ifndef CONF_GCLK_SERCOM0_SLOW_SRC 92 #define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val 93 #endif 94 95 /** 96 * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY 97 * \brief SERCOM0's Core Clock frequency 98 */ 99 #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY 100 #define CONF_GCLK_SERCOM0_CORE_FREQUENCY 40001536 101 #endif 102 103 /** 104 * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY 105 * \brief SERCOM0's Slow Clock frequency 106 */ 107 #ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY 108 #define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 4000000 109 #endif 110 111 // <y> Core Clock Source 112 // <id> core_gclk_selection 113 114 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 115 116 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 117 118 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 119 120 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 121 122 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 123 124 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 125 126 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 127 128 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 129 130 // <i> Select the clock source for CORE. 131 #ifndef CONF_GCLK_SERCOM4_CORE_SRC 132 #define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 133 #endif 134 135 // <y> Slow Clock Source 136 // <id> slow_gclk_selection 137 138 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 139 140 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 141 142 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 143 144 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 145 146 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 147 148 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 149 150 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 151 152 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 153 154 // <i> Select the slow clock source. 155 #ifndef CONF_GCLK_SERCOM4_SLOW_SRC 156 #define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val 157 #endif 158 159 /** 160 * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY 161 * \brief SERCOM4's Core Clock frequency 162 */ 163 #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY 164 #define CONF_GCLK_SERCOM4_CORE_FREQUENCY 40001536 165 #endif 166 167 /** 168 * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY 169 * \brief SERCOM4's Slow Clock frequency 170 */ 171 #ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY 172 #define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 4000000 173 #endif 174 175 // <y> CAN0 Clock Source 176 // <id> can_gclk_selection 177 178 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 179 180 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 181 182 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 183 184 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 185 186 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 187 188 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 189 190 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 191 192 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 193 194 // <i> Select the clock source for CAN0. 195 #ifndef CONF_GCLK_CAN0_SRC 196 #define CONF_GCLK_CAN0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 197 #endif 198 199 /** 200 * \def CONF_GCLK_CAN0_FREQUENCY 201 * \brief CAN0's Clock frequency 202 */ 203 #ifndef CONF_GCLK_CAN0_FREQUENCY 204 #define CONF_GCLK_CAN0_FREQUENCY 40001536 205 #endif 206 207 // <<< end of configuration section >>> 208 209 #endif // PERIPHERAL_CLK_CONFIG_H 210