1 /* Auto-generated config file peripheral_clk_config.h */
2 #ifndef PERIPHERAL_CLK_CONFIG_H
3 #define PERIPHERAL_CLK_CONFIG_H
4 
5 // <<< Use Configuration Wizard in Context Menu >>>
6 
7 // <y> ADC Clock Source
8 // <id> adc_gclk_selection
9 
10 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
11 
12 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
13 
14 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
15 
16 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
17 
18 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
19 
20 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
21 
22 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
23 
24 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
25 
26 // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
27 
28 // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
29 
30 // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
31 
32 // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
33 
34 // <i> Select the clock source for ADC.
35 #ifndef CONF_GCLK_ADC0_SRC
36 #define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
37 #endif
38 
39 /**
40  * \def CONF_GCLK_ADC0_FREQUENCY
41  * \brief ADC0's Clock frequency
42  */
43 #ifndef CONF_GCLK_ADC0_FREQUENCY
44 #define CONF_GCLK_ADC0_FREQUENCY 120000000
45 #endif
46 
47 /**
48  * \def CONF_CPU_FREQUENCY
49  * \brief CPU's Clock frequency
50  */
51 #ifndef CONF_CPU_FREQUENCY
52 #define CONF_CPU_FREQUENCY 120000000
53 #endif
54 
55 // <y> Core Clock Source
56 // <id> core_gclk_selection
57 
58 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
59 
60 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
61 
62 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
63 
64 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
65 
66 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
67 
68 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
69 
70 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
71 
72 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
73 
74 // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
75 
76 // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
77 
78 // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
79 
80 // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
81 
82 // <i> Select the clock source for CORE.
83 #ifndef CONF_GCLK_SERCOM2_CORE_SRC
84 #define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
85 #endif
86 
87 // <y> Slow Clock Source
88 // <id> slow_gclk_selection
89 
90 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
91 
92 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
93 
94 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
95 
96 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
97 
98 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
99 
100 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
101 
102 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
103 
104 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
105 
106 // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
107 
108 // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
109 
110 // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
111 
112 // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
113 
114 // <i> Select the slow clock source.
115 #ifndef CONF_GCLK_SERCOM2_SLOW_SRC
116 #define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
117 #endif
118 
119 /**
120  * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
121  * \brief SERCOM2's Core Clock frequency
122  */
123 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
124 #define CONF_GCLK_SERCOM2_CORE_FREQUENCY 120000000
125 #endif
126 
127 /**
128  * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
129  * \brief SERCOM2's Slow Clock frequency
130  */
131 #ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
132 #define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 3000000
133 #endif
134 
135 // <y> Core Clock Source
136 // <id> core_gclk_selection
137 
138 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
139 
140 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
141 
142 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
143 
144 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
145 
146 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
147 
148 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
149 
150 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
151 
152 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
153 
154 // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
155 
156 // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
157 
158 // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
159 
160 // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
161 
162 // <i> Select the clock source for CORE.
163 #ifndef CONF_GCLK_SERCOM7_CORE_SRC
164 #define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
165 #endif
166 
167 // <y> Slow Clock Source
168 // <id> slow_gclk_selection
169 
170 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
171 
172 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
173 
174 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
175 
176 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
177 
178 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
179 
180 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
181 
182 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
183 
184 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
185 
186 // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
187 
188 // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
189 
190 // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
191 
192 // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
193 
194 // <i> Select the slow clock source.
195 #ifndef CONF_GCLK_SERCOM7_SLOW_SRC
196 #define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
197 #endif
198 
199 /**
200  * \def CONF_GCLK_SERCOM7_CORE_FREQUENCY
201  * \brief SERCOM7's Core Clock frequency
202  */
203 #ifndef CONF_GCLK_SERCOM7_CORE_FREQUENCY
204 #define CONF_GCLK_SERCOM7_CORE_FREQUENCY 40000000
205 #endif
206 
207 /**
208  * \def CONF_GCLK_SERCOM7_SLOW_FREQUENCY
209  * \brief SERCOM7's Slow Clock frequency
210  */
211 #ifndef CONF_GCLK_SERCOM7_SLOW_FREQUENCY
212 #define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 3000000
213 #endif
214 
215 // <y> CAN1 Clock Source
216 // <id> can_gclk_selection
217 
218 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
219 
220 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
221 
222 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
223 
224 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
225 
226 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
227 
228 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
229 
230 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
231 
232 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
233 
234 // <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
235 
236 // <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
237 
238 // <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
239 
240 // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
241 
242 // <i> Select the clock source for CAN1.
243 #ifndef CONF_GCLK_CAN1_SRC
244 #define CONF_GCLK_CAN1_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
245 #endif
246 
247 /**
248  * \def CONF_GCLK_CAN1_FREQUENCY
249  * \brief CAN1's Clock frequency
250  */
251 #ifndef CONF_GCLK_CAN1_FREQUENCY
252 #define CONF_GCLK_CAN1_FREQUENCY 40000000
253 #endif
254 
255 // <<< end of configuration section >>>
256 
257 #endif // PERIPHERAL_CLK_CONFIG_H
258