1 /* Auto-generated config file hpl_sercom_config.h */ 2 #ifndef HPL_SERCOM_CONFIG_H 3 #define HPL_SERCOM_CONFIG_H 4 5 // <<< Use Configuration Wizard in Context Menu >>> 6 7 #include <peripheral_clk_config.h> 8 9 #ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER 10 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) 11 #endif 12 13 #ifndef CONF_SERCOM_0_I2CM_ENABLE 14 #define CONF_SERCOM_0_I2CM_ENABLE 1 15 #endif 16 17 // <h> Basic 18 19 // <o> I2C Bus clock speed (Hz) <1-400000> 20 // <i> I2C Bus clock (SCL) speed measured in Hz 21 // <id> i2c_master_baud_rate 22 #ifndef CONF_SERCOM_0_I2CM_BAUD 23 #define CONF_SERCOM_0_I2CM_BAUD 100000 24 #endif 25 26 // </h> 27 28 // <e> Advanced 29 // <id> i2c_master_advanced 30 #ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 31 #define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 1 32 #endif 33 34 // <o> TRise (ns) <0-300> 35 // <i> Determined by the bus impedance, check electric characteristics in the datasheet 36 // <i> Standard Fast Mode: typical 215ns, max 300ns 37 // <i> Fast Mode +: typical 60ns, max 100ns 38 // <i> High Speed Mode: typical 20ns, max 40ns 39 // <id> i2c_master_arch_trise 40 41 #ifndef CONF_SERCOM_0_I2CM_TRISE 42 #define CONF_SERCOM_0_I2CM_TRISE 215 43 #endif 44 45 // <q> Master SCL Low Extended Time-Out (MEXTTOEN) 46 // <i> This enables the master SCL low extend time-out 47 // <id> i2c_master_arch_mexttoen 48 #ifndef CONF_SERCOM_0_I2CM_MEXTTOEN 49 #define CONF_SERCOM_0_I2CM_MEXTTOEN 1 50 #endif 51 52 // <q> Slave SCL Low Extend Time-Out (SEXTTOEN) 53 // <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine 54 // <id> i2c_master_arch_sexttoen 55 #ifndef CONF_SERCOM_0_I2CM_SEXTTOEN 56 #define CONF_SERCOM_0_I2CM_SEXTTOEN 0 57 #endif 58 59 // <q> SCL Low Time-Out (LOWTOUT) 60 // <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold 61 // <id> i2c_master_arch_lowtout 62 #ifndef CONF_SERCOM_0_I2CM_LOWTOUT 63 #define CONF_SERCOM_0_I2CM_LOWTOUT 1 64 #endif 65 66 // <o> Inactive Time-Out (INACTOUT) 67 // <0x0=>Disabled 68 // <0x1=>5-6 SCL cycle time-out(50-60us) 69 // <0x2=>10-11 SCL cycle time-out(100-110us) 70 // <0x3=>20-21 SCL cycle time-out(200-210us) 71 // <i> Defines if inactivity time-out should be enabled, and how long the time-out should be 72 // <id> i2c_master_arch_inactout 73 #ifndef CONF_SERCOM_0_I2CM_INACTOUT 74 #define CONF_SERCOM_0_I2CM_INACTOUT 0x3 75 #endif 76 77 // <o> SDA Hold Time (SDAHOLD) 78 // <0=>Disabled 79 // <1=>50-100ns hold time 80 // <2=>300-600ns hold time 81 // <3=>400-800ns hold time 82 // <i> Defines the SDA hold time with respect to the negative edge of SCL 83 // <id> i2c_master_arch_sdahold 84 #ifndef CONF_SERCOM_0_I2CM_SDAHOLD 85 #define CONF_SERCOM_0_I2CM_SDAHOLD 0x2 86 #endif 87 88 // <q> Run in stand-by 89 // <i> Determine if the module shall run in standby sleep mode 90 // <id> i2c_master_arch_runstdby 91 #ifndef CONF_SERCOM_0_I2CM_RUNSTDBY 92 #define CONF_SERCOM_0_I2CM_RUNSTDBY 0 93 #endif 94 95 // <o> Debug Stop Mode 96 // <i> Behavior of the baud-rate generator when CPU is halted by external debugger. 97 // <0=>Keep running 98 // <1=>Halt 99 // <id> i2c_master_arch_dbgstop 100 #ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 101 #define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0 102 #endif 103 104 // </e> 105 106 #ifndef CONF_SERCOM_0_I2CM_SPEED 107 #define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode 108 #endif 109 #if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300 110 #warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns 111 #undef CONF_SERCOM_0_I2CM_TRISE 112 #define CONF_SERCOM_0_I2CM_TRISE 215U 113 #endif 114 115 // gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) 116 // BAUD + BAUDLOW = -------------------------------------------------------------------- 117 // i2c_scl_freq 118 // BAUD: register value low [7:0] 119 // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW 120 #define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW \ 121 (((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10U) \ 122 - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000U) \ 123 / 1000U)) \ 124 * 10U \ 125 + 5U) \ 126 / (CONF_SERCOM_0_I2CM_BAUD * 10U)) 127 #ifndef CONF_SERCOM_0_I2CM_BAUD_RATE 128 #if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2) 129 #warning Requested I2C baudrate too low, please check 130 #define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF 131 #elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1 132 #warning Requested I2C baudrate too high, please check 133 #define CONF_SERCOM_0_I2CM_BAUD_RATE 1 134 #else 135 #define CONF_SERCOM_0_I2CM_BAUD_RATE \ 136 ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1) \ 137 ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ 138 : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2)) 139 #endif 140 #endif 141 142 #include <peripheral_clk_config.h> 143 144 #ifndef CONF_SERCOM_4_USART_ENABLE 145 #define CONF_SERCOM_4_USART_ENABLE 1 146 #endif 147 148 // <h> Basic Configuration 149 150 // <q> Receive buffer enable 151 // <i> Enable input buffer in SERCOM module 152 // <id> usart_rx_enable 153 #ifndef CONF_SERCOM_4_USART_RXEN 154 #define CONF_SERCOM_4_USART_RXEN 1 155 #endif 156 157 // <q> Transmitt buffer enable 158 // <i> Enable output buffer in SERCOM module 159 // <id> usart_tx_enable 160 #ifndef CONF_SERCOM_4_USART_TXEN 161 #define CONF_SERCOM_4_USART_TXEN 1 162 #endif 163 164 // <o> Frame parity 165 // <0x0=>No parity 166 // <0x1=>Even parity 167 // <0x2=>Odd parity 168 // <i> Parity bit mode for USART frame 169 // <id> usart_parity 170 #ifndef CONF_SERCOM_4_USART_PARITY 171 #define CONF_SERCOM_4_USART_PARITY 0x0 172 #endif 173 174 // <o> Character Size 175 // <0x0=>8 bits 176 // <0x1=>9 bits 177 // <0x5=>5 bits 178 // <0x6=>6 bits 179 // <0x7=>7 bits 180 // <i> Data character size in USART frame 181 // <id> usart_character_size 182 #ifndef CONF_SERCOM_4_USART_CHSIZE 183 #define CONF_SERCOM_4_USART_CHSIZE 0x0 184 #endif 185 186 // <o> Stop Bit 187 // <0=>One stop bit 188 // <1=>Two stop bits 189 // <i> Number of stop bits in USART frame 190 // <id> usart_stop_bit 191 #ifndef CONF_SERCOM_4_USART_SBMODE 192 #define CONF_SERCOM_4_USART_SBMODE 0 193 #endif 194 195 // <o> Baud rate <1-3000000> 196 // <i> USART baud rate setting 197 // <id> usart_baud_rate 198 #ifndef CONF_SERCOM_4_USART_BAUD 199 #define CONF_SERCOM_4_USART_BAUD 115200 200 #endif 201 202 // </h> 203 204 // <e> Advanced configuration 205 // <id> usart_advanced 206 #ifndef CONF_SERCOM_4_USART_ADVANCED_CONFIG 207 #define CONF_SERCOM_4_USART_ADVANCED_CONFIG 1 208 #endif 209 210 // <q> Run in stand-by 211 // <i> Keep the module running in standby sleep mode 212 // <id> usart_arch_runstdby 213 #ifndef CONF_SERCOM_4_USART_RUNSTDBY 214 #define CONF_SERCOM_4_USART_RUNSTDBY 0 215 #endif 216 217 // <q> Immediate Buffer Overflow Notification 218 // <i> Controls when the BUFOVF status bit is asserted 219 // <id> usart_arch_ibon 220 #ifndef CONF_SERCOM_4_USART_IBON 221 #define CONF_SERCOM_4_USART_IBON 0 222 #endif 223 224 // <q> Start of Frame Detection Enable 225 // <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) 226 // <id> usart_arch_sfde 227 #ifndef CONF_SERCOM_4_USART_SFDE 228 #define CONF_SERCOM_4_USART_SFDE 0 229 #endif 230 231 // <q> Collision Detection Enable 232 // <i> Collision detection enable 233 // <id> usart_arch_cloden 234 #ifndef CONF_SERCOM_4_USART_CLODEN 235 #define CONF_SERCOM_4_USART_CLODEN 0 236 #endif 237 238 // <o> Operating Mode 239 // <0x0=>USART with external clock 240 // <0x1=>USART with internal clock 241 // <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. 242 // <id> usart_arch_clock_mode 243 #ifndef CONF_SERCOM_4_USART_MODE 244 #define CONF_SERCOM_4_USART_MODE 0x1 245 #endif 246 247 // <o> Sample Rate 248 // <0x0=>16x arithmetic 249 // <0x1=>16x fractional 250 // <0x2=>8x arithmetic 251 // <0x3=>8x fractional 252 // <0x4=>3x arithmetic 253 // <i> How many over-sampling bits used when sampling data state 254 // <id> usart_arch_sampr 255 #ifndef CONF_SERCOM_4_USART_SAMPR 256 #define CONF_SERCOM_4_USART_SAMPR 0x0 257 #endif 258 259 // <o> Sample Adjustment 260 // <0x0=>7-8-9 (3-4-5 8-bit over-sampling) 261 // <0x1=>9-10-11 (4-5-6 8-bit over-sampling) 262 // <0x2=>11-12-13 (5-6-7 8-bit over-sampling) 263 // <0x3=>13-14-15 (6-7-8 8-bit over-sampling) 264 // <i> Adjust which samples to use for data sampling in asynchronous mode 265 // <id> usart_arch_sampa 266 #ifndef CONF_SERCOM_4_USART_SAMPA 267 #define CONF_SERCOM_4_USART_SAMPA 0x0 268 #endif 269 270 // <o> Fractional Part <0-7> 271 // <i> Fractional part of the baud rate if baud rate generator is in fractional mode 272 // <id> usart_arch_fractional 273 #ifndef CONF_SERCOM_4_USART_FRACTIONAL 274 #define CONF_SERCOM_4_USART_FRACTIONAL 0x0 275 #endif 276 277 // <o> Data Order 278 // <0=>MSB is transmitted first 279 // <1=>LSB is transmitted first 280 // <i> Data order of the data bits in the frame 281 // <id> usart_arch_dord 282 #ifndef CONF_SERCOM_4_USART_DORD 283 #define CONF_SERCOM_4_USART_DORD 1 284 #endif 285 286 // Does not do anything in UART mode 287 #define CONF_SERCOM_4_USART_CPOL 0 288 289 // <o> Encoding Format 290 // <0=>No encoding 291 // <1=>IrDA encoded 292 // <id> usart_arch_enc 293 #ifndef CONF_SERCOM_4_USART_ENC 294 #define CONF_SERCOM_4_USART_ENC 0 295 #endif 296 297 // <o> LIN Slave Enable 298 // <i> Break Character Detection and Auto-Baud/LIN Slave Enable. 299 // <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). 300 // <0=>Disable 301 // <1=>Enable 302 // <id> usart_arch_lin_slave_enable 303 #ifndef CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE 304 #define CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE 0 305 #endif 306 307 // <o> Debug Stop Mode 308 // <i> Behavior of the baud-rate generator when CPU is halted by external debugger. 309 // <0=>Keep running 310 // <1=>Halt 311 // <id> usart_arch_dbgstop 312 #ifndef CONF_SERCOM_4_USART_DEBUG_STOP_MODE 313 #define CONF_SERCOM_4_USART_DEBUG_STOP_MODE 0 314 #endif 315 316 // </e> 317 318 #ifndef CONF_SERCOM_4_USART_CMODE 319 #define CONF_SERCOM_4_USART_CMODE 0 320 #endif 321 322 #ifndef CONF_SERCOM_4_USART_RXPO 323 #define CONF_SERCOM_4_USART_RXPO 3 /* RX is on PIN_PB11 */ 324 #endif 325 326 #ifndef CONF_SERCOM_4_USART_TXPO 327 #define CONF_SERCOM_4_USART_TXPO 1 /* TX is on PIN_PB10 */ 328 #endif 329 330 /* Set correct parity settings in register interface based on PARITY setting */ 331 #if CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE == 1 332 #if CONF_SERCOM_4_USART_PARITY == 0 333 #define CONF_SERCOM_4_USART_PMODE 0 334 #define CONF_SERCOM_4_USART_FORM 4 335 #else 336 #define CONF_SERCOM_4_USART_PMODE CONF_SERCOM_4_USART_PARITY - 1 337 #define CONF_SERCOM_4_USART_FORM 5 338 #endif 339 #else /* #if CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE == 0 */ 340 #if CONF_SERCOM_4_USART_PARITY == 0 341 #define CONF_SERCOM_4_USART_PMODE 0 342 #define CONF_SERCOM_4_USART_FORM 0 343 #else 344 #define CONF_SERCOM_4_USART_PMODE CONF_SERCOM_4_USART_PARITY - 1 345 #define CONF_SERCOM_4_USART_FORM 1 346 #endif 347 #endif 348 349 // Calculate BAUD register value in UART mode 350 #if CONF_SERCOM_4_USART_SAMPR == 0 351 #ifndef CONF_SERCOM_4_USART_BAUD_RATE 352 #define CONF_SERCOM_4_USART_BAUD_RATE \ 353 65536 - ((65536 * 16.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY) 354 #endif 355 #ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 356 #define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 357 #endif 358 #elif CONF_SERCOM_4_USART_SAMPR == 1 359 #ifndef CONF_SERCOM_4_USART_BAUD_RATE 360 #define CONF_SERCOM_4_USART_BAUD_RATE \ 361 ((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 16)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8) 362 #endif 363 #ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 364 #define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 365 #endif 366 #elif CONF_SERCOM_4_USART_SAMPR == 2 367 #ifndef CONF_SERCOM_4_USART_BAUD_RATE 368 #define CONF_SERCOM_4_USART_BAUD_RATE \ 369 65536 - ((65536 * 8.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY) 370 #endif 371 #ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 372 #define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 373 #endif 374 #elif CONF_SERCOM_4_USART_SAMPR == 3 375 #ifndef CONF_SERCOM_4_USART_BAUD_RATE 376 #define CONF_SERCOM_4_USART_BAUD_RATE \ 377 ((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 8)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8) 378 #endif 379 #ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 380 #define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 381 #endif 382 #elif CONF_SERCOM_4_USART_SAMPR == 4 383 #ifndef CONF_SERCOM_4_USART_BAUD_RATE 384 #define CONF_SERCOM_4_USART_BAUD_RATE \ 385 65536 - ((65536 * 3.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY) 386 #endif 387 #ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 388 #define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 389 #endif 390 #endif 391 392 // <<< end of configuration section >>> 393 394 #endif // HPL_SERCOM_CONFIG_H 395