1 /******************************************************************************
2 * Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 ******************************************************************************/
5
6 /*****************************************************************************/
7 /**
8 *
9 * @file xsdps_hw.h
10 * @addtogroup sdps_v3_9
11 * @{
12 *
13 * This header file contains the identifiers and basic HW access driver
14 * functions (or macros) that can be used to access the device. Other driver
15 * functions are defined in xsdps.h.
16 *
17 * <pre>
18 * MODIFICATION HISTORY:
19 *
20 * Ver Who Date Changes
21 * ----- --- -------- -----------------------------------------------
22 * 1.00a hk/sg 10/17/13 Initial release
23 * 2.5 sg 07/09/15 Added SD 3.0 features
24 * kvn 07/15/15 Modified the code according to MISRAC-2012.
25 * 2.7 sk 12/10/15 Added support for MMC cards.
26 * sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
27 * 2.8 sk 04/20/16 Added new workaround for auto tuning.
28 * 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
29 * sk 07/16/16 Added support for UHS modes.
30 * sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
31 * operating modes.
32 * 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
33 * 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
34 * 3.3 mn 08/22/17 Updated for Word Access System support
35 * mn 09/06/17 Added support for ARMCC toolchain
36 * 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
37 * 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
38 * 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
39 * mn 05/21/19 Set correct tap delays for Versal
40 * mn 05/21/19 Disable DLL Reset code for Versal
41 * mn 07/03/19 Update Input Tap Delays for Versal
42 * 3.9 mn 03/03/20 Restructured the code for more readability and modularity
43 *
44 * </pre>
45 *
46 ******************************************************************************/
47
48 #ifndef SD_HW_H_
49 #define SD_HW_H_
50
51 #ifdef __cplusplus
52 extern "C" {
53 #endif
54
55 /***************************** Include Files *********************************/
56
57 #include "xil_types.h"
58 #include "xil_assert.h"
59 #include "xil_io.h"
60 #include "xparameters.h"
61
62 /************************** Constant Definitions *****************************/
63
64 /** @name Register Map
65 *
66 * Register offsets from the base address of an SD device.
67 * @{
68 */
69
70 #define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
71 Register */
72 #define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
73 /**< SDMA System Address
74 Low Register */
75 #define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
76 #define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
77 High Register */
78 #define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
79
80 #define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
81 #define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
82 #define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
83 #define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
84 /**< Argument1 Register */
85 #define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
86
87 #define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
88 #define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
89 #define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
90 #define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
91 #define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
92 #define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
93 #define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
94 #define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
95 #define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
96 #define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
97 #define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
98 #define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
99 #define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
100 #define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
101 #define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
102 #define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
103 Status Register */
104 #define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
105 Status Register */
106 #define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
107 Status Enable Register */
108 #define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
109 Status Enable Register */
110 #define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
111 Signal Enable Register */
112 #define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
113 Signal Enable Register */
114
115 #define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
116 Register */
117 #define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
118 #define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
119 #define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
120 #define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
121 Capabilities Register */
122 #define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
123 Capabilities Ext Register */
124 #define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
125 Error Interrupt Status */
126 #define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
127 Status Register */
128 #define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
129 Register */
130 #define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
131 Register */
132 #define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
133 Extended Register */
134 #define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
135 #define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
136 #define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
137 #define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
138 #define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
139 register */
140
141 #define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
142 Register */
143 #define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
144 Register */
145 #define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
146 Register */
147
148 /* @} */
149
150 /** @name Control Register - Host control, Power control,
151 * Block Gap control and Wakeup control
152 *
153 * This register contains bits for various configuration options of
154 * the SD host controller. Read/Write apart from the reserved bits.
155 * @{
156 */
157
158 #define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
159 #define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
160 #define XSDPS_HC_BUS_WIDTH_4 0x00000002U
161 #define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
162 #define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
163 #define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
164 #define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
165 #define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
166 #define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
167 #define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
168 #define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
169 #define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
170
171 #define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
172 #define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
173 #define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
174 #define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
175 #define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
176 #define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
177
178 #define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
179 #define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
180 #define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
181 #define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
182 #define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
183 #define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
184 #define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
185 #define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
186
187 #define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
188 #define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
189 #define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
190
191 /* @} */
192
193 /** @name Control Register - Clock control, Timeout control & Software reset
194 *
195 * This register contains bits for configuration options of clock, timeout and
196 * software reset.
197 * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
198 * @{
199 */
200
201 #define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U
202 #define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U
203 #define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U
204 #define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U
205 #define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x00000003U
206 #define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x000000FFU
207 #define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U
208 #define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U
209 #define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U
210 #define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U
211 #define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U
212 #define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U
213 #define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U
214 #define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U
215 #define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U
216 #define XSDPS_CC_MAX_DIV_CNT 256U
217 #define XSDPS_CC_EXT_MAX_DIV_CNT 2046U
218 #define XSDPS_CC_EXT_DIV_SHIFT 6U
219
220 #define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU
221
222 #define XSDPS_SWRST_ALL_MASK 0x00000001U
223 #define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U
224 #define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U
225
226 #define XSDPS_CC_MAX_NUM_OF_DIV 9U
227 #define XSDPS_CC_DIV_SHIFT 8U
228
229 /* @} */
230
231 /** @name SD Interrupt Registers
232 *
233 * <b> Normal and Error Interrupt Status Register </b>
234 * This register shows the normal and error interrupt status.
235 * Status enable register affects reads of this register.
236 * If Signal enable register is set and the corresponding status bit is set,
237 * interrupt is generated.
238 * Write to clear except
239 * Error_interrupt and Card_Interrupt bits - Read only
240 *
241 * <b> Normal and Error Interrupt Status Enable Register </b>
242 * Setting this register bits enables Interrupt status.
243 * Read/Write except Fixed_to_0 bit (Read only)
244 *
245 * <b> Normal and Error Interrupt Signal Enable Register </b>
246 * This register is used to select which interrupt status is
247 * indicated to the Host System as the interrupt.
248 * Read/Write except Fixed_to_0 bit (Read only)
249 *
250 * All three registers have same bit definitions
251 * @{
252 */
253
254 #define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
255 #define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
256 #define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
257 #define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
258 #define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
259 #define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
260 #define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
261 #define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
262 #define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
263 #define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
264 #define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
265 #define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
266 #define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
267 #define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
268 Interrupt */
269 #define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
270 Interrupt */
271 #define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
272 #define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
273
274 #define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
275 Error */
276 #define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
277 #define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
278 Error */
279 #define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
280 #define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
281 #define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
282 #define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
283 #define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
284 #define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
285 #define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
286 #define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
287 #define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
288 Error */
289 #define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
290 /* @} */
291
292 /** @name Block Size and Block Count Register
293 *
294 * This register contains the block count for current transfer,
295 * block size and SDMA buffer size.
296 * Read/Write except for reserved bits.
297 * @{
298 */
299
300 #define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
301 #define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
302 #define XSDPS_BLK_SIZE_1024 0x400U
303 #define XSDPS_BLK_SIZE_2048 0x800U
304 #define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
305 Current Transfer */
306
307 /* @} */
308
309 /** @name Transfer Mode and Command Register
310 *
311 * The Transfer Mode register is used to control the data transfers and
312 * Command register is used for command generation
313 * Read/Write except for reserved bits.
314 * @{
315 */
316
317 #define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
318 #define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
319 #define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
320 #define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
321 Direction Select */
322 #define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
323 Block Select */
324
325 #define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
326 Select */
327 #define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
328 #define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
329 #define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
330 #define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
331 check busy after
332 response */
333 #define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
334 Enable */
335 #define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
336 Enable */
337 #define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
338 #define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
339 #define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
340 #define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
341 #define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
342 #define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
343 #define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
344 Set to CMD0-63,
345 AMCD0-63 */
346
347 /* @} */
348
349 /** @name Auto CMD Error Status Register
350 *
351 * This register is read only register which contains
352 * information about the error status of Auto CMD 12 and 23.
353 * Read Only
354 * @{
355 */
356 #define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
357 executed */
358 #define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
359 Error */
360 #define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
361 #define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
362 Error */
363 #define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
364 #define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
365 Auto CMD12 Error */
366 /* @} */
367
368 /** @name Host Control2 Register
369 *
370 * This register contains extended configuration bits.
371 * Read Write
372 * @{
373 */
374 #define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
375 #define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
376 #define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
377 #define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
378 #define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
379 #define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
380 #define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
381 #define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
382 Selection */
383 #define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
384 #define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
385 #define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
386 #define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
387 #define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
388 #define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
389 Selection */
390 #define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
391 Enable */
392 #define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
393
394 /* @} */
395
396 /** @name Capabilities Register
397 *
398 * Capabilities register is a read only register which contains
399 * information about the host controller.
400 * Sufficient if read once after power on.
401 * Read Only
402 * @{
403 */
404 #define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
405 select */
406 #define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
407 MHz/KHz */
408 #define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
409 #define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
410 #define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
411 #define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
412 #define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
413
414 #define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
415 #define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
416 #define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
417 #define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
418 #define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
419 support */
420 #define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
421 #define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
422 #define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
423
424 #define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
425 support */
426 /* Spec 2.0 */
427 #define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
428 support */
429 #define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
430 #define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
431
432
433 /* Spec 3.0 */
434 #define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
435 support */
436 #define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
437 #define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
438 #define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
439 #define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
440
441 #define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
442 #define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
443 #define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
444 #define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
445 #define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
446 #define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
447 #define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
448 Re-tuning */
449 #define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
450 tuning */
451 #define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
452 support */
453 #define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
454 #define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
455 #define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
456 #define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
457 for Programmable clock
458 mode */
459 #define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
460 #define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
461
462 /* @} */
463
464 /** @name Present State Register
465 *
466 * Gives the current status of the host controller
467 * Read Only
468 * @{
469 */
470
471 #define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
472 #define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
473 #define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
474 #define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
475 #define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
476 #define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
477 #define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
478 #define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
479 #define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
480 #define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
481 #define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
482 #define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
483 pin level */
484 #define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
485 #define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
486 #define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
487
488 /* @} */
489
490 /** @name Maximum Current Capabilities Register
491 *
492 * This register is read only register which contains
493 * information about current capabilities at each voltage levels.
494 * Read Only
495 * @{
496 */
497 #define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
498 Capability at 1.8V */
499 #define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
500 Capability at 3.0V */
501 #define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
502 Capability at 3.3V */
503 /* @} */
504
505
506 /** @name Force Event for Auto CMD Error Status Register
507 *
508 * This register is write only register which contains
509 * control bits to generate events for Auto CMD error status.
510 * Write Only
511 * @{
512 */
513 #define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
514 executed */
515 #define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
516 Error */
517 #define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
518 #define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
519 Error */
520 #define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
521 #define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
522 Auto CMD12 Error */
523 /* @} */
524
525
526
527 /** @name Force Event for Error Interrupt Status Register
528 *
529 * This register is write only register which contains
530 * control bits to generate events of error interrupt status register.
531 * Write Only
532 * @{
533 */
534 #define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
535 Error */
536 #define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
537 #define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
538 Error */
539 #define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
540 #define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
541 #define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
542 #define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
543 #define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
544 #define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
545 #define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
546 #define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */
547 #define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
548 Error */
549
550 /* @} */
551
552 /** @name ADMA Error Status Register
553 *
554 * This register is read only register which contains
555 * status information about ADMA errors.
556 * Read Only
557 * @{
558 */
559 #define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
560 Error */
561 #define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
562 #define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
563 STOP */
564 #define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
565 FDS */
566 #define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
567 TFR */
568 /* @} */
569
570 /** @name Preset Values Register
571 *
572 * This register is read only register which contains
573 * preset values for each of speed modes.
574 * Read Only
575 * @{
576 */
577 #define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
578 Select Value */
579 #define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
580 Mode Select */
581 #define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
582 Select Value */
583
584 /* @} */
585
586 /** @name Slot Interrupt Status Register
587 *
588 * This register is read only register which contains
589 * interrupt slot signal for each slot.
590 * Read Only
591 * @{
592 */
593 #define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
594 mask */
595
596 /* @} */
597
598 /** @name Host Controller Version Register
599 *
600 * This register is read only register which contains
601 * Host Controller and Vendor Specific version.
602 * Read Only
603 * @{
604 */
605 #define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
606 Specification
607 version mask */
608 #define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
609 Specification
610 version mask */
611 #define XSDPS_HC_SPEC_V3 0x0002U
612 #define XSDPS_HC_SPEC_V2 0x0001U
613 #define XSDPS_HC_SPEC_V1 0x0000U
614
615 /** @name Block size mask for 512 bytes
616 *
617 * Block size mask for 512 bytes - This is the default block size.
618 * @{
619 */
620
621 #define XSDPS_BLK_SIZE_512_MASK 0x200U
622
623 /* @} */
624
625 /** @name Commands
626 *
627 * Constant definitions for commands and response related to SD
628 * @{
629 */
630
631 #define XSDPS_APP_CMD_PREFIX 0x8000U
632 #define CMD0 0x0000U
633 #define CMD1 0x0100U
634 #define CMD2 0x0200U
635 #define CMD3 0x0300U
636 #define CMD4 0x0400U
637 #define CMD5 0x0500U
638 #define CMD6 0x0600U
639 #define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
640 #define CMD7 0x0700U
641 #define CMD8 0x0800U
642 #define CMD9 0x0900U
643 #define CMD10 0x0A00U
644 #define CMD11 0x0B00U
645 #define CMD12 0x0C00U
646 #define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
647 #define CMD16 0x1000U
648 #define CMD17 0x1100U
649 #define CMD18 0x1200U
650 #define CMD19 0x1300U
651 #define CMD21 0x1500U
652 #define CMD23 0x1700U
653 #define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
654 #define CMD24 0x1800U
655 #define CMD25 0x1900U
656 #define CMD41 0x2900U
657 #define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
658 #define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
659 #define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
660 #define CMD52 0x3400U
661 #define CMD55 0x3700U
662 #define CMD58 0x3A00U
663
664 #if 0
665 #define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
666 #define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
667 (u32)XSDPS_CMD_INX_CHK_EN_MASK
668
669 #define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
670 (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
671
672 #define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
673 #define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
674
675 #define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
676 (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
677 #else
678 #define XSDPS_RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
679 #define XSDPS_RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
680 (u32)XSDPS_CMD_INX_CHK_EN_MASK
681
682 #define XSDPS_RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
683 (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
684
685 #define XSDPS_RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
686 #define XSDPS_RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
687
688 #define XSDPS_RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
689 (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
690 #endif
691
692 /* @} */
693
694 /* Card Interface Conditions Definitions */
695 #define XSDPS_CIC_CHK_PATTERN 0xAAU
696 #define XSDPS_CIC_VOLT_MASK (0xFU<<8)
697 #define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
698 #define XSDPS_CIC_VOLT_LOW (1U<<9)
699
700 /* Operation Conditions Register Definitions */
701 #define XSDPS_OCR_PWRUP_STS (1U<<31)
702 #define XSDPS_OCR_CC_STS (1U<<30)
703 #define XSDPS_OCR_S18 (1U<<24)
704 #define XSDPS_OCR_3V5_3V6 (1U<<23)
705 #define XSDPS_OCR_3V4_3V5 (1U<<22)
706 #define XSDPS_OCR_3V3_3V4 (1U<<21)
707 #define XSDPS_OCR_3V2_3V3 (1U<<20)
708 #define XSDPS_OCR_3V1_3V2 (1U<<19)
709 #define XSDPS_OCR_3V0_3V1 (1U<<18)
710 #define XSDPS_OCR_2V9_3V0 (1U<<17)
711 #define XSDPS_OCR_2V8_2V9 (1U<<16)
712 #define XSDPS_OCR_2V7_2V8 (1U<<15)
713 #define XSDPS_OCR_1V7_1V95 (1U<<7)
714 #define XSDPS_OCR_HIGH_VOL 0x00FF8000U
715 #define XSDPS_OCR_LOW_VOL 0x00000080U
716
717 /* SD Card Configuration Register Definitions */
718 #define XSDPS_SCR_REG_LEN 8U
719 #define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
720 #define XSDPS_SCR_SPEC_MASK (0xFU<<24)
721 #define XSDPS_SCR_SPEC_1V0 0U
722 #define XSDPS_SCR_SPEC_1V1 (1U<<24)
723 #define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
724 #define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
725 #define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
726 #define XSDPS_SCR_SEC_SUPP_NONE 0U
727 #define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
728 #define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
729 #define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
730 #define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
731 #define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
732 #define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
733 #define XSDPS_SCR_SPEC3_MASK (1U<<12)
734 #define XSDPS_SCR_SPEC3_2V0 0U
735 #define XSDPS_SCR_SPEC3_3V0 (1U<<12)
736 #define XSDPS_SCR_CMD_SUPP_MASK 0x3U
737 #define XSDPS_SCR_CMD23_SUPP (1U<<1)
738 #define XSDPS_SCR_CMD20_SUPP (1U<<0)
739
740 /* Card Status Register Definitions */
741 #define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
742 #define XSDPS_CD_STS_ADDR_ERR (1U<<30)
743 #define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
744 #define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
745 #define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
746 #define XSDPS_CD_STS_WP_VIO (1U<<26)
747 #define XSDPS_CD_STS_IS_LOCKED (1U<<25)
748 #define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
749 #define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
750 #define XSDPS_CD_STS_ILGL_CMD (1U<<22)
751 #define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
752 #define XSDPS_CD_STS_CC_ERR (1U<<20)
753 #define XSDPS_CD_STS_ERR (1U<<19)
754 #define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
755 #define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
756 #define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
757 #define XSDPS_CD_STS_ER_RST (1U<<13)
758 #define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
759 #define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
760 #define XSDPS_CD_STS_APP_CMD (1U<<5)
761 #define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
762
763 /* Switch Function Definitions CMD6 */
764 #define XSDPS_SWITCH_SD_RESP_LEN 64U
765
766 #define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
767 #define XSDPS_SWITCH_FUNC_CHECK 0U
768
769 #define XSDPS_MODE_FUNC_GRP1 1U
770 #define XSDPS_MODE_FUNC_GRP2 2U
771 #define XSDPS_MODE_FUNC_GRP3 3U
772 #define XSDPS_MODE_FUNC_GRP4 4U
773 #define XSDPS_MODE_FUNC_GRP5 5U
774 #define XSDPS_MODE_FUNC_GRP6 6U
775
776 #define XSDPS_FUNC_GRP_DEF_VAL 0xFU
777 #define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
778
779 #define XSDPS_ACC_MODE_DEF_SDR12 0U
780 #define XSDPS_ACC_MODE_HS_SDR25 1U
781 #define XSDPS_ACC_MODE_SDR50 2U
782 #define XSDPS_ACC_MODE_SDR104 3U
783 #define XSDPS_ACC_MODE_DDR50 4U
784
785 #define XSDPS_CMD_SYS_ARG_SHIFT 4U
786 #define XSDPS_CMD_SYS_DEF 0U
787 #define XSDPS_CMD_SYS_eC 1U
788 #define XSDPS_CMD_SYS_OTP 3U
789 #define XSDPS_CMD_SYS_ASSD 4U
790 #define XSDPS_CMD_SYS_VEND 5U
791
792 #define XSDPS_DRV_TYPE_ARG_SHIFT 8U
793 #define XSDPS_DRV_TYPE_B 0U
794 #define XSDPS_DRV_TYPE_A 1U
795 #define XSDPS_DRV_TYPE_C 2U
796 #define XSDPS_DRV_TYPE_D 3U
797
798 #define XSDPS_CUR_LIM_ARG_SHIFT 12U
799 #define XSDPS_CUR_LIM_200 0U
800 #define XSDPS_CUR_LIM_400 1U
801 #define XSDPS_CUR_LIM_600 2U
802 #define XSDPS_CUR_LIM_800 3U
803
804 #define CSD_SPEC_VER_MASK 0x3C0000U
805 #define READ_BLK_LEN_MASK 0x00000F00U
806 #define C_SIZE_MULT_MASK 0x00000380U
807 #define C_SIZE_LOWER_MASK 0xFFC00000U
808 #define C_SIZE_UPPER_MASK 0x00000003U
809 #define CSD_STRUCT_MASK 0x00C00000U
810 #define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
811
812 /* EXT_CSD field definitions */
813 #define XSDPS_EXT_CSD_SIZE 512U
814
815 #define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
816
817 #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
818 #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
819 #define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
820 #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
821
822 #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
823 #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
824 #define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U)
825 #define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
826 #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
827 #define EXT_CSD_PART_CONFIG_BYTE 179U
828 #define XSDPS_MMC_PART_CFG_0_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
829 | (EXT_CSD_PART_CONFIG_BYTE << 16U) \
830 | ((0U) << 8U))
831
832 #define XSDPS_MMC_PART_CFG_1_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
833 | (EXT_CSD_PART_CONFIG_BYTE << 16U) \
834 | (EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
835
836 #define XSDPS_MMC_PART_CFG_2_ARG ((XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
837 | (EXT_CSD_PART_CONFIG_BYTE << 16U) \
838 | (EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
839
840 #define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
841
842 #define EXT_CSD_CMD_SET_NORMAL (1U<<0)
843 #define EXT_CSD_CMD_SET_SECURE (1U<<1)
844 #define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
845
846 #define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
847 #define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
848 #define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
849 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
850 /* DDR mode @1.8V or 3V I/O */
851 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
852 /* DDR mode @1.2V I/O */
853 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
854 | EXT_CSD_CARD_TYPE_DDR_1_2V)
855 #define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
856 #define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
857 /* SDR mode @1.2V I/O */
858 #define EXT_CSD_BUS_WIDTH_BYTE 183U
859 #define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
860 #define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
861 #define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
862 #define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
863 #define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
864
865 #define EXT_CSD_HS_TIMING_BYTE 185U
866 #define EXT_CSD_HS_TIMING_DEF 0U
867 #define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
868 #define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
869
870 #define EXT_CSD_RST_N_FUN_BYTE 162U
871 #define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
872 #define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
873 #define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
874
875 #define XSDPS_EXT_CSD_CMD_SET 0U
876 #define XSDPS_EXT_CSD_SET_BITS 1U
877 #define XSDPS_EXT_CSD_CLR_BITS 2U
878 #define XSDPS_EXT_CSD_WRITE_BYTE 3U
879
880 #define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
881 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
882 | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
883
884 #define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
885 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
886 | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
887
888 #define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
889 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
890 | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
891
892 #define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
893 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
894 | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
895
896 #define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
897 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
898 | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
899
900 #define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
901 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
902 | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
903
904 #define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
905 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
906 | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
907
908 #define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
909 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
910 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
911
912 #define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
913 | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
914 | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
915
916 #define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
917
918 /* @} */
919
920 /* @400KHz, in usec */
921 #define XSDPS_74CLK_DELAY 2960U
922 #define XSDPS_100CLK_DELAY 4000U
923 #define XSDPS_INIT_DELAY 10000U
924
925 #define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK
926 #define XSDPS_CARD_DEF_ADDR 0x1234U
927
928 #define XSDPS_CARD_SD 1U
929 #define XSDPS_CARD_MMC 2U
930 #define XSDPS_CARD_SDIO 3U
931 #define XSDPS_CARD_SDCOMBO 4U
932 #define XSDPS_CHIP_EMMC 5U
933
934
935 /** @name ADMA2 Descriptor related definitions
936 *
937 * ADMA2 Descriptor related definitions
938 * @{
939 */
940
941 #define XSDPS_DESC_MAX_LENGTH 65536U
942
943 #define XSDPS_DESC_VALID (0x1U << 0)
944 #define XSDPS_DESC_END (0x1U << 1)
945 #define XSDPS_DESC_INT (0x1U << 2)
946 #define XSDPS_DESC_TRAN (0x2U << 4)
947
948 /* @} */
949
950 /* For changing clock frequencies */
951 #define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
952 #define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
953 #define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
954 #define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
955 #define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
956 #define XSDPS_SCR_BLKCNT 1U
957 #define XSDPS_SCR_BLKSIZE 8U
958 #define XSDPS_1_BIT_WIDTH 0x1U
959 #define XSDPS_4_BIT_WIDTH 0x2U
960 #define XSDPS_8_BIT_WIDTH 0x3U
961 #define XSDPS_UHS_SPEED_MODE_SDR12 0x0U
962 #define XSDPS_UHS_SPEED_MODE_SDR25 0x1U
963 #define XSDPS_UHS_SPEED_MODE_SDR50 0x2U
964 #define XSDPS_UHS_SPEED_MODE_SDR104 0x3U
965 #define XSDPS_UHS_SPEED_MODE_DDR50 0x4U
966 #define XSDPS_HIGH_SPEED_MODE 0x5U
967 #define XSDPS_DEFAULT_SPEED_MODE 0x6U
968 #define XSDPS_HS200_MODE 0x7U
969 #define XSDPS_DDR52_MODE 0x4U
970 #define XSDPS_SWITCH_CMD_BLKCNT 1U
971 #define XSDPS_SWITCH_CMD_BLKSIZE 64U
972 #define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U
973 #define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U
974 #define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U
975 #define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U
976 #define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U
977 #define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U
978 #define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U
979 #define XSDPS_EXT_CSD_CMD_BLKCNT 1U
980 #define XSDPS_EXT_CSD_CMD_BLKSIZE 512U
981 #define XSDPS_TUNING_CMD_BLKCNT 1U
982 #define XSDPS_TUNING_CMD_BLKSIZE 64U
983 #define XSDPS_SD_STATUS_BLKCNT 1U
984 #define XSDPS_SD_STATUS_BLKSIZE 64U
985
986 #define XSDPS_HIGH_SPEED_MAX_CLK 50000000U
987 #define XSDPS_UHS_SDR104_MAX_CLK 208000000U
988 #define XSDPS_UHS_SDR50_MAX_CLK 100000000U
989 #define XSDPS_UHS_DDR50_MAX_CLK 50000000U
990 #define XSDPS_UHS_SDR25_MAX_CLK 50000000U
991 #define XSDPS_UHS_SDR12_MAX_CLK 25000000U
992
993 #define SD_DRIVER_TYPE_B 0x01U
994 #define SD_DRIVER_TYPE_A 0x02U
995 #define SD_DRIVER_TYPE_C 0x04U
996 #define SD_DRIVER_TYPE_D 0x08U
997 #define SD_SET_CURRENT_LIMIT_200 0U
998 #define SD_SET_CURRENT_LIMIT_400 1U
999 #define SD_SET_CURRENT_LIMIT_600 2U
1000 #define SD_SET_CURRENT_LIMIT_800 3U
1001
1002 #define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200)
1003 #define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400)
1004 #define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600)
1005 #define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800)
1006
1007 #define XSDPS_SD_SDR12_MAX_CLK 25000000U
1008 #define XSDPS_SD_SDR25_MAX_CLK 50000000U
1009 #define XSDPS_SD_SDR50_MAX_CLK 100000000U
1010 #define XSDPS_SD_DDR50_MAX_CLK 50000000U
1011 #define XSDPS_SD_SDR104_MAX_CLK 208000000U
1012 /*
1013 * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
1014 * than the clock value coming from the core. This value is kept to safely
1015 * switch to SDR104 mode if the SD card supports it.
1016 */
1017 #define XSDPS_SD_INPUT_MAX_CLK 175000000U
1018
1019 #define XSDPS_MMC_HS200_MAX_CLK 200000000U
1020 #define XSDPS_MMC_HSD_MAX_CLK 52000000U
1021 #define XSDPS_MMC_DDR_MAX_CLK 52000000U
1022
1023 #define XSDPS_CARD_STATE_IDLE 0U
1024 #define XSDPS_CARD_STATE_RDY 1U
1025 #define XSDPS_CARD_STATE_IDEN 2U
1026 #define XSDPS_CARD_STATE_STBY 3U
1027 #define XSDPS_CARD_STATE_TRAN 4U
1028 #define XSDPS_CARD_STATE_DATA 5U
1029 #define XSDPS_CARD_STATE_RCV 6U
1030 #define XSDPS_CARD_STATE_PROG 7U
1031 #define XSDPS_CARD_STATE_DIS 8U
1032 #define XSDPS_CARD_STATE_BTST 9U
1033 #define XSDPS_CARD_STATE_SLP 10U
1034
1035 #define XSDPS_SLOT_REM 0U
1036 #define XSDPS_SLOT_EMB 1U
1037
1038 #define XSDPS_WIDTH_8 8U
1039 #define XSDPS_WIDTH_4 4U
1040
1041
1042 #ifdef versal
1043 #define SD_ITAPDLY_SEL_MASK 0x000000FFU
1044 #define SD_OTAPDLY_SEL_MASK 0x0000003FU
1045 #define SD_ITAPDLY 0x0000F0F8U
1046 #define SD_OTAPDLY 0x0000F0FCU
1047 #define SD0_DLL_CTRL 0x00000448U
1048 #define SD1_DLL_CTRL 0x000004C8U
1049 #define SD_DLL_RST 0x00000004U
1050 #define SD_ITAPCHGWIN 0x00000200U
1051 #define SD_ITAPDLYENA 0x00000100U
1052 #define SD_OTAPDLYENA 0x00000040U
1053 #define SD_OTAPDLYSEL_HS200_B0 0x00000002U
1054 #define SD_OTAPDLYSEL_HS200_B2 0x00000002U
1055 #define SD_ITAPDLYSEL_SD50 0x0000000EU
1056 #define SD_OTAPDLYSEL_SD50 0x00000003U
1057 #define SD_ITAPDLYSEL_SD_DDR50 0x00000036U
1058 #define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU
1059 #define SD_OTAPDLYSEL_SD_DDR50 0x00000003U
1060 #define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U
1061 #define SD_ITAPDLYSEL_HSD 0x0000002CU
1062 #define SD_OTAPDLYSEL_SD_HSD 0x00000004U
1063 #define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U
1064 #else
1065 #define SD0_ITAPDLY_SEL_MASK 0x000000FFU
1066 #define SD0_OTAPDLY_SEL_MASK 0x0000003FU
1067 #define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
1068 #define SD1_OTAPDLY_SEL_MASK 0x003F0000U
1069 #define SD_DLL_CTRL 0x00000358U
1070 #define SD_ITAPDLY 0x00000314U
1071 #define SD_OTAPDLY 0x00000318U
1072 #define SD0_DLL_RST 0x00000004U
1073 #define SD1_DLL_RST 0x00040000U
1074 #define SD0_ITAPCHGWIN 0x00000200U
1075 #define SD0_ITAPDLYENA 0x00000100U
1076 #define SD0_OTAPDLYENA 0x00000040U
1077 #define SD1_ITAPCHGWIN 0x02000000U
1078 #define SD1_ITAPDLYENA 0x01000000U
1079 #define SD1_OTAPDLYENA 0x00400000U
1080 #define SD_OTAPDLYSEL_HS200_B0 0x00000003U
1081 #define SD_OTAPDLYSEL_HS200_B2 0x00000002U
1082 #define SD_ITAPDLYSEL_SD50 0x00000014U
1083 #define SD_OTAPDLYSEL_SD50 0x00000003U
1084 #define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU
1085 #define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U
1086 #define SD_OTAPDLYSEL_SD_DDR50 0x00000004U
1087 #define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U
1088 #define SD_ITAPDLYSEL_HSD 0x00000015U
1089 #define SD_OTAPDLYSEL_SD_HSD 0x00000005U
1090 #define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U
1091 #endif
1092
1093 #ifdef __MICROBLAZE__
1094 #define XPS_SYS_CTRL_BASEADDR 0xFF180000U
1095 #endif
1096
1097 /**************************** Type Definitions *******************************/
1098
1099 /***************** Macros (Inline Functions) Definitions *********************/
1100 #define XSdPs_In64 Xil_In64
1101 #define XSdPs_Out64 Xil_Out64
1102
1103 #define XSdPs_In32 Xil_In32
1104 #define XSdPs_Out32 Xil_Out32
1105
1106 #define XSdPs_In16 Xil_In16
1107 #define XSdPs_Out16 Xil_Out16
1108
1109 #define XSdPs_In8 Xil_In8
1110 #define XSdPs_Out8 Xil_Out8
1111
1112 /****************************************************************************/
1113 /**
1114 * Read a register.
1115 *
1116 * @param InstancePtr is the pointer to the sdps instance.
1117 * @param RegOffset contains the offset from the 1st register of the
1118 * device to the target register.
1119 *
1120 * @return The value read from the register.
1121 *
1122 * @note C-Style signature:
1123 * u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
1124 *
1125 ******************************************************************************/
1126 #define XSdPs_ReadReg64(InstancePtr, RegOffset) \
1127 XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
1128
1129 /***************************************************************************/
1130 /**
1131 * Write to a register.
1132 *
1133 * @param InstancePtr is the pointer to the sdps instance.
1134 * @param RegOffset contains the offset from the 1st register of the
1135 * device to target register.
1136 * @param RegisterValue is the value to be written to the register.
1137 *
1138 * @return None.
1139 *
1140 * @note C-Style signature:
1141 * void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
1142 * u64 RegisterValue)
1143 *
1144 ******************************************************************************/
1145 #define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
1146 XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
1147 (RegisterValue))
1148
1149 /****************************************************************************/
1150 /**
1151 * Read a register.
1152 *
1153 * @param BaseAddress contains the base address of the device.
1154 * @param RegOffset contains the offset from the 1st register of the
1155 * device to the target register.
1156 *
1157 * @return The value read from the register.
1158 *
1159 * @note C-Style signature:
1160 * u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
1161 *
1162 ******************************************************************************/
1163 #define XSdPs_ReadReg(BaseAddress, RegOffset) \
1164 XSdPs_In32((BaseAddress) + (RegOffset))
1165
1166 /***************************************************************************/
1167 /**
1168 * Write to a register.
1169 *
1170 * @param BaseAddress contains the base address of the device.
1171 * @param RegOffset contains the offset from the 1st register of the
1172 * device to target register.
1173 * @param RegisterValue is the value to be written to the register.
1174 *
1175 * @return None.
1176 *
1177 * @note C-Style signature:
1178 * void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
1179 * u32 RegisterValue)
1180 *
1181 ******************************************************************************/
1182 #define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
1183 XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
1184
1185 /****************************************************************************/
1186 /**
1187 * Read a register.
1188 *
1189 * @param BaseAddress contains the base address of the device.
1190 * @param RegOffset contains the offset from the 1st register of the
1191 * device to the target register.
1192 *
1193 * @return The value read from the register.
1194 *
1195 * @note C-Style signature:
1196 * u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
1197 *
1198 ******************************************************************************/
XSdPs_ReadReg16(u32 BaseAddress,u8 RegOffset)1199 static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
1200 {
1201 #if defined (__MICROBLAZE__)
1202 u32 Reg;
1203 BaseAddress += RegOffset & 0xFC;
1204 Reg = XSdPs_In32(BaseAddress);
1205 Reg >>= ((RegOffset & 0x3)*8);
1206 return (u16)Reg;
1207 #else
1208 return XSdPs_In16((BaseAddress) + (RegOffset));
1209 #endif
1210 }
1211
1212 /***************************************************************************/
1213 /**
1214 * Write to a register.
1215 *
1216 * @param BaseAddress contains the base address of the device.
1217 * @param RegOffset contains the offset from the 1st register of the
1218 * device to target register.
1219 * @param RegisterValue is the value to be written to the register.
1220 *
1221 * @return None.
1222 *
1223 * @note C-Style signature:
1224 * void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
1225 * u16 RegisterValue)
1226 *
1227 ******************************************************************************/
1228
XSdPs_WriteReg16(u32 BaseAddress,u8 RegOffset,u16 RegisterValue)1229 static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
1230 {
1231 #if defined (__MICROBLAZE__)
1232 u32 Reg;
1233 BaseAddress += RegOffset & 0xFC;
1234 Reg = XSdPs_In32(BaseAddress);
1235 Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
1236 Reg |= RegisterValue <<((RegOffset & 0x3)*8);
1237 XSdPs_Out32(BaseAddress, Reg);
1238 #else
1239 XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
1240 #endif
1241 }
1242
1243 /****************************************************************************/
1244 /**
1245 * Read a register.
1246 *
1247 * @param BaseAddress contains the base address of the device.
1248 * @param RegOffset contains the offset from the 1st register of the
1249 * device to the target register.
1250 *
1251 * @return The value read from the register.
1252 *
1253 * @note C-Style signature:
1254 * u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
1255 *
1256 ******************************************************************************/
XSdPs_ReadReg8(u32 BaseAddress,u8 RegOffset)1257 static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
1258 {
1259 #if defined (__MICROBLAZE__)
1260 u32 Reg;
1261 BaseAddress += RegOffset & 0xFC;
1262 Reg = XSdPs_In32(BaseAddress);
1263 Reg >>= ((RegOffset & 0x3)*8);
1264 return (u8)Reg;
1265 #else
1266 return XSdPs_In8((BaseAddress) + (RegOffset));
1267 #endif
1268 }
1269 /***************************************************************************/
1270 /**
1271 * Write to a register.
1272 *
1273 * @param BaseAddress contains the base address of the device.
1274 * @param RegOffset contains the offset from the 1st register of the
1275 * device to target register.
1276 * @param RegisterValue is the value to be written to the register.
1277 *
1278 * @return None.
1279 *
1280 * @note C-Style signature:
1281 * void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
1282 * u8 RegisterValue)
1283 *
1284 ******************************************************************************/
XSdPs_WriteReg8(u32 BaseAddress,u8 RegOffset,u8 RegisterValue)1285 static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
1286 {
1287 #if defined (__MICROBLAZE__)
1288 u32 Reg;
1289 BaseAddress += RegOffset & 0xFC;
1290 Reg = XSdPs_In32(BaseAddress);
1291 Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
1292 Reg |= RegisterValue <<((RegOffset & 0x3)*8);
1293 XSdPs_Out32(BaseAddress, Reg);
1294 #else
1295 XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
1296 #endif
1297 }
1298 /***************************************************************************/
1299 /**
1300 * Macro to get present status register
1301 *
1302 * @param BaseAddress contains the base address of the device.
1303 *
1304 * @return None.
1305 *
1306 * @note C-Style signature:
1307 * void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
1308 * u8 RegisterValue)
1309 *
1310 ******************************************************************************/
1311 #define XSdPs_GetPresentStatusReg(BaseAddress) \
1312 XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
1313
1314 /************************** Function Prototypes ******************************/
1315
1316 /************************** Variable Definitions *****************************/
1317
1318 #ifdef __cplusplus
1319 }
1320 #endif
1321
1322 #endif /* SD_HW_H_ */
1323 /** @} */
1324