1 /**
2   ******************************************************************************
3   * @file    csi_reg.h
4   * @version V1.0
5   * @date    2022-12-13
6   * @brief   This file is the description of.IP register
7   ******************************************************************************
8   * @attention
9   *
10   * <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11   *
12   * Redistribution and use in source and binary forms, with or without modification,
13   * are permitted provided that the following conditions are met:
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15   *      this list of conditions and the following disclaimer.
16   *   2. Redistributions in binary form must reproduce the above copyright notice,
17   *      this list of conditions and the following disclaimer in the documentation
18   *      and/or other materials provided with the distribution.
19   *   3. Neither the name of Bouffalo Lab nor the names of its contributors
20   *      may be used to endorse or promote products derived from this software
21   *      without specific prior written permission.
22   *
23   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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34   ******************************************************************************
35   */
36 #ifndef  __HARDWARE_CSI_H__
37 #define  __HARDWARE_CSI_H__
38 
39 /****************************************************************************
40  * Pre-processor Definitions
41 ****************************************************************************/
42 
43 /* Register offsets *********************************************************/
44 
45 #define CSI_MIPI_CONFIG_OFFSET    (0x0)/* mipi_config */
46 #define CSI_INT_STATUS_OFFSET     (0x10)/* csi_int_status */
47 #define CSI_INT_MASK_OFFSET       (0x14)/* csi_int_mask */
48 #define CSI_INT_CLEAR_OFFSET      (0x18)/* csi_int_clear */
49 #define CSI_INT_ENABLE_OFFSET     (0x1C)/* csi_int_enable */
50 #define CSI_GNR_BUF_STATUS_OFFSET (0x20)/* gnr_buf_status */
51 #define CSI_GNR_BUF_RDATA_OFFSET  (0x24)/* gnr_buf_rdata */
52 #define CSI_DPHY_CONFIG_0_OFFSET  (0x80)/* dphy_config_0 */
53 #define CSI_DPHY_CONFIG_1_OFFSET  (0x84)/* dphy_config_1 */
54 #define CSI_DPHY_CONFIG_2_OFFSET  (0x88)/* dphy_config_2 */
55 #define CSI_DPHY_CONFIG_3_OFFSET  (0x8C)/* dphy_config_3 */
56 #define CSI_DPHY_CONFIG_4_OFFSET  (0x90)/* dphy_config_4 */
57 #define CSI_DPHY_CONFIG_5_OFFSET  (0x94)/* dphy_config_5 */
58 #define CSI_DUMMY_REG_OFFSET      (0xFC)/* dummy_reg */
59 
60 /* Register Bitfield definitions *****************************************************/
61 
62 /* 0x0 : mipi_config */
63 #define CSI_CR_CSI_EN        (1<<0U)
64 #define CSI_CR_LANE_NUM      (1<<1U)
65 #define CSI_CR_LANE_INV      (1<<3U)
66 #define CSI_CR_DATA_BIT_INV  (1<<4U)
67 #define CSI_CR_SYNC_SP_EN    (1<<5U)
68 #define CSI_CR_UNPACK_EN     (1<<6U)
69 #define CSI_CR_VC_DVP0_SHIFT (12U)
70 #define CSI_CR_VC_DVP0_MASK  (0x3<<CSI_CR_VC_DVP0_SHIFT)
71 #define CSI_CR_VC_DVP1_SHIFT (14U)
72 #define CSI_CR_VC_DVP1_MASK  (0x3<<CSI_CR_VC_DVP1_SHIFT)
73 
74 /* 0x10 : csi_int_status */
75 #define CSI_INT_STATUS_SHIFT (0U)
76 #define CSI_INT_STATUS_MASK  (0x3f<<CSI_INT_STATUS_SHIFT)
77 
78 /* 0x14 : csi_int_mask */
79 #define CSI_INT_MASK_SHIFT (0U)
80 #define CSI_INT_MASK_MASK  (0x3f<<CSI_INT_MASK_SHIFT)
81 
82 /* 0x18 : csi_int_clear */
83 #define CSI_INT_CLEAR_SHIFT (0U)
84 #define CSI_INT_CLEAR_MASK  (0x3f<<CSI_INT_CLEAR_SHIFT)
85 
86 /* 0x1C : csi_int_enable */
87 #define CSI_INT_ENABLE_SHIFT (0U)
88 #define CSI_INT_ENABLE_MASK  (0x3f<<CSI_INT_ENABLE_SHIFT)
89 
90 /* 0x20 : gnr_buf_status */
91 #define CSI_ST_GNR_FIFO_CNT_SHIFT (0U)
92 #define CSI_ST_GNR_FIFO_CNT_MASK  (0xf<<CSI_ST_GNR_FIFO_CNT_SHIFT)
93 
94 /* 0x24 : gnr_buf_rdata */
95 #define CSI_GNR_BUF_RDATA_SHIFT (0U)
96 #define CSI_GNR_BUF_RDATA_MASK  (0xffffffff<<CSI_GNR_BUF_RDATA_SHIFT)
97 
98 /* 0x80 : dphy_config_0 */
99 #define CSI_DL0_ENABLE        (1<<0U)
100 #define CSI_DL1_ENABLE        (1<<1U)
101 #define CSI_CL_ENABLE         (1<<2U)
102 #define CSI_DL0_STOPSTATE     (1<<4U)
103 #define CSI_DL1_STOPSTATE     (1<<5U)
104 #define CSI_CL_STOPSTATE      (1<<6U)
105 #define CSI_DL0_ULPSACTIVENOT (1<<8U)
106 #define CSI_DL1_ULPSACTIVENOT (1<<9U)
107 #define CSI_CL_ULPSACTIVENOT  (1<<10U)
108 #define CSI_DL0_FORCERXMODE   (1<<12U)
109 #define CSI_DL1_FORCERXMODE   (1<<13U)
110 #define CSI_CL_RXCLKACTIVEHS  (1<<14U)
111 #define CSI_CL_RXULPSCLKNOT   (1<<15U)
112 #define CSI_RESET_N           (1<<31U)
113 
114 /* 0x84 : dphy_config_1 */
115 #define CSI_REG_TIME_CK_SETTLE_SHIFT  (0U)
116 #define CSI_REG_TIME_CK_SETTLE_MASK   (0xff<<CSI_REG_TIME_CK_SETTLE_SHIFT)
117 #define CSI_REG_TIME_CK_TERM_EN_SHIFT (8U)
118 #define CSI_REG_TIME_CK_TERM_EN_MASK  (0xff<<CSI_REG_TIME_CK_TERM_EN_SHIFT)
119 #define CSI_REG_TIME_HS_SETTLE_SHIFT  (16U)
120 #define CSI_REG_TIME_HS_SETTLE_MASK   (0xff<<CSI_REG_TIME_HS_SETTLE_SHIFT)
121 #define CSI_REG_TIME_HS_TERM_EN_SHIFT (24U)
122 #define CSI_REG_TIME_HS_TERM_EN_MASK  (0xff<<CSI_REG_TIME_HS_TERM_EN_SHIFT)
123 
124 /* 0x88 : dphy_config_2 */
125 #define CSI_REG_ANA_LPRXEN_CLK            (1<<0U)
126 #define CSI_REG_ANA_HSRXEN_CLK            (1<<1U)
127 #define CSI_REG_ANA_HSRX_STOP_STATE_SHIFT (2U)
128 #define CSI_REG_ANA_HSRX_STOP_STATE_MASK  (0x3<<CSI_REG_ANA_HSRX_STOP_STATE_SHIFT)
129 #define CSI_REG_ANA_HSRX_SYNC_EN_SHIFT    (4U)
130 #define CSI_REG_ANA_HSRX_SYNC_EN_MASK     (0x3<<CSI_REG_ANA_HSRX_SYNC_EN_SHIFT)
131 #define CSI_REG_ANA_LPRXEN_SHIFT          (6U)
132 #define CSI_REG_ANA_LPRXEN_MASK           (0x3<<CSI_REG_ANA_LPRXEN_SHIFT)
133 #define CSI_REG_ANA_HSRXEN_SHIFT          (8U)
134 #define CSI_REG_ANA_HSRXEN_MASK           (0x3<<CSI_REG_ANA_HSRXEN_SHIFT)
135 #define CSI_REG_ANA_TERM_EN_SHIFT         (10U)
136 #define CSI_REG_ANA_TERM_EN_MASK          (0x1f<<CSI_REG_ANA_TERM_EN_SHIFT)
137 #define CSI_REG_ANA_TEST_EN               (1<<15U)
138 #define CSI_REG_PT_LOCK_COUNTER_SHIFT     (16U)
139 #define CSI_REG_PT_LOCK_COUNTER_MASK      (0xf<<CSI_REG_PT_LOCK_COUNTER_SHIFT)
140 #define CSI_REG_PT_PRBS_OR_JITT           (1<<20U)
141 #define CSI_REG_PT_LP_MODE                (1<<21U)
142 #define CSI_REG_PT_EN                     (1<<22U)
143 #define CSI_REG_PT_LOCK                   (1<<23U)
144 #define CSI_REG_PT_PASS                   (1<<24U)
145 
146 /* 0x8C : dphy_config_3 */
147 #define CSI_REG_CSI_ANA_1_SHIFT (0U)
148 #define CSI_REG_CSI_ANA_1_MASK  (0xffff<<CSI_REG_CSI_ANA_1_SHIFT)
149 #define CSI_REG_CSI_ANA_0_SHIFT (16U)
150 #define CSI_REG_CSI_ANA_0_MASK  (0xffff<<CSI_REG_CSI_ANA_0_SHIFT)
151 
152 /* 0x90 : dphy_config_4 */
153 #define CSI_REG_CSI_DC_TP_OUT_EN (1<<0U)
154 #define CSI_REG_CSI_PW_AVDD1815  (1<<4U)
155 
156 /* 0x94 : dphy_config_5 */
157 #define CSI_REG_CSI_BYTE_CLK_INV (1<<0U)
158 #define CSI_REG_CSI_DDR_CLK_INV  (1<<1U)
159 
160 /* 0xFC : dummy_reg */
161 #define CSI_DUMMY_REG_SHIFT (0U)
162 #define CSI_DUMMY_REG_MASK  (0xffffffff<<CSI_DUMMY_REG_SHIFT)
163 
164 
165 #endif  /* __HARDWARE_CSI_H__ */
166