1 /******************************************************************************* 2 * File Name: cycfg_pins.h 3 * 4 * Description: 5 * Pin configuration 6 * This file was automatically generated and should not be modified. 7 * Configurator Backend 3.0.0 8 * device-db 4.1.0.3437 9 * mtb-pdl-cat1 3.3.0.21979 10 * 11 ******************************************************************************** 12 * Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or 13 * an affiliate of Cypress Semiconductor Corporation. 14 * SPDX-License-Identifier: Apache-2.0 15 * 16 * Licensed under the Apache License, Version 2.0 (the "License"); 17 * you may not use this file except in compliance with the License. 18 * You may obtain a copy of the License at 19 * 20 * http://www.apache.org/licenses/LICENSE-2.0 21 * 22 * Unless required by applicable law or agreed to in writing, software 23 * distributed under the License is distributed on an "AS IS" BASIS, 24 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 * See the License for the specific language governing permissions and 26 * limitations under the License. 27 ********************************************************************************/ 28 29 #if !defined(CYCFG_PINS_H) 30 #define CYCFG_PINS_H 31 32 #include "cycfg_notices.h" 33 #include "cy_gpio.h" 34 #include "cycfg_routing.h" 35 #if defined (CY_USING_HAL) 36 #include "cyhal_hwmgr.h" 37 #endif //defined (CY_USING_HAL) 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif 42 43 #define CYBSP_WCO_IN_ENABLED 1U 44 #define CYBSP_WCO_IN_PORT GPIO_PRT0 45 #define CYBSP_WCO_IN_PORT_NUM 0U 46 #define CYBSP_WCO_IN_PIN 0U 47 #define CYBSP_WCO_IN_NUM 0U 48 #define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG 49 #define CYBSP_WCO_IN_INIT_DRIVESTATE 1 50 #ifndef ioss_0_port_0_pin_0_HSIOM 51 #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO 52 #endif 53 #define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM 54 #define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn 55 #if defined (CY_USING_HAL) 56 #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0 57 #define CYBSP_WCO_IN P0_0 58 #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE 59 #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 60 #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 61 #endif //defined (CY_USING_HAL) 62 #define CYBSP_WCO_OUT_ENABLED 1U 63 #define CYBSP_WCO_OUT_PORT GPIO_PRT0 64 #define CYBSP_WCO_OUT_PORT_NUM 0U 65 #define CYBSP_WCO_OUT_PIN 1U 66 #define CYBSP_WCO_OUT_NUM 1U 67 #define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG 68 #define CYBSP_WCO_OUT_INIT_DRIVESTATE 1 69 #ifndef ioss_0_port_0_pin_1_HSIOM 70 #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO 71 #endif 72 #define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM 73 #define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn 74 #if defined (CY_USING_HAL) 75 #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1 76 #define CYBSP_WCO_OUT P0_1 77 #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE 78 #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 79 #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 80 #define CYBSP_BT_POWER (P0_2) 81 #define CYBSP_BT_DEVICE_WAKE (P0_3) 82 #define CYBSP_SW2 (P0_4) 83 #define CYBSP_USER_BTN1 CYBSP_SW2 84 #define CYBSP_USER_BTN CYBSP_SW2 85 #define CYBSP_BT_HOST_WAKE (P0_5) 86 #define CYBSP_DEBUG_UART_RX (P10_0) 87 #define CYBSP_DEBUG_UART_TX (P10_1) 88 #define CYBSP_LED4 (P11_1) 89 #define CYBSP_USER_LED1 CYBSP_LED4 90 #define CYBSP_USER_LED CYBSP_LED4 91 #define CYBSP_QSPI_SS (P11_2) 92 #define CYBSP_QSPI_D3 (P11_3) 93 #define CYBSP_QSPI_D2 (P11_4) 94 #define CYBSP_QSPI_D1 (P11_5) 95 #define CYBSP_QSPI_D0 (P11_6) 96 #define CYBSP_QSPI_SCK (P11_7) 97 #define CYBSP_WIFI_SDIO_D0 (P2_0) 98 #define CYBSP_WIFI_SDIO_D1 (P2_1) 99 #define CYBSP_WIFI_SDIO_D2 (P2_2) 100 #define CYBSP_WIFI_SDIO_D3 (P2_3) 101 #define CYBSP_WIFI_SDIO_CMD (P2_4) 102 #define CYBSP_WIFI_SDIO_CLK (P2_5) 103 #define CYBSP_WIFI_WL_REG_ON (P2_6) 104 #define CYBSP_WIFI_HOST_WAKE (P2_7) 105 #define CYBSP_BT_UART_RX (P3_0) 106 #define CYBSP_BT_UART_TX (P3_1) 107 #define CYBSP_I2C_SCL (P6_4) 108 #define CYBSP_I2C_SDA (P6_5) 109 #endif //defined (CY_USING_HAL) 110 #define CYBSP_SWDIO_ENABLED 1U 111 #define CYBSP_SWDIO_PORT GPIO_PRT6 112 #define CYBSP_SWDIO_PORT_NUM 6U 113 #define CYBSP_SWDIO_PIN 6U 114 #define CYBSP_SWDIO_NUM 6U 115 #define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP 116 #define CYBSP_SWDIO_INIT_DRIVESTATE 1 117 #ifndef ioss_0_port_6_pin_6_HSIOM 118 #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO 119 #endif 120 #define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM 121 #define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn 122 #if defined (CY_USING_HAL) 123 #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 124 #define CYBSP_SWDIO P6_6 125 #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE 126 #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 127 #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP 128 #endif //defined (CY_USING_HAL) 129 #define CYBSP_SWDCK_ENABLED 1U 130 #define CYBSP_SWDCK_PORT GPIO_PRT6 131 #define CYBSP_SWDCK_PORT_NUM 6U 132 #define CYBSP_SWDCK_PIN 7U 133 #define CYBSP_SWDCK_NUM 7U 134 #define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN 135 #define CYBSP_SWDCK_INIT_DRIVESTATE 1 136 #ifndef ioss_0_port_6_pin_7_HSIOM 137 #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO 138 #endif 139 #define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM 140 #define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn 141 #if defined (CY_USING_HAL) 142 #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 143 #define CYBSP_SWDCK P6_7 144 #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE 145 #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 146 #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN 147 #endif //defined (CY_USING_HAL) 148 #define CYBSP_CSD_SLD0_ENABLED 1U 149 #define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED 150 #define CYBSP_CSD_SLD0_PORT GPIO_PRT7 151 #define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT 152 #define CYBSP_CSD_SLD0_PORT_NUM 7U 153 #define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM 154 #define CYBSP_CSD_SLD0_PIN 0U 155 #define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN 156 #define CYBSP_CSD_SLD0_NUM 0U 157 #define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM 158 #define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG 159 #define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE 160 #define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1 161 #define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE 162 #ifndef ioss_0_port_7_pin_0_HSIOM 163 #define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_GPIO 164 #endif 165 #define CYBSP_CSD_SLD0_HSIOM ioss_0_port_7_pin_0_HSIOM 166 #define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM 167 #define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_7_IRQn 168 #define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ 169 #if defined (CY_USING_HAL) 170 #define CYBSP_CSD_SLD0_HAL_PORT_PIN P7_0 171 #define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN 172 #define CYBSP_CSD_SLD0 P7_0 173 #define CYBSP_CS_SLD0 CYBSP_CSD_SLD0 174 #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE 175 #define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ 176 #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 177 #define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR 178 #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 179 #define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE 180 #endif //defined (CY_USING_HAL) 181 #define CYBSP_CSD_SLD1_ENABLED 1U 182 #define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED 183 #define CYBSP_CSD_SLD1_PORT GPIO_PRT7 184 #define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT 185 #define CYBSP_CSD_SLD1_PORT_NUM 7U 186 #define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM 187 #define CYBSP_CSD_SLD1_PIN 1U 188 #define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN 189 #define CYBSP_CSD_SLD1_NUM 1U 190 #define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM 191 #define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG 192 #define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE 193 #define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1 194 #define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE 195 #ifndef ioss_0_port_7_pin_1_HSIOM 196 #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO 197 #endif 198 #define CYBSP_CSD_SLD1_HSIOM ioss_0_port_7_pin_1_HSIOM 199 #define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM 200 #define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_7_IRQn 201 #define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ 202 #if defined (CY_USING_HAL) 203 #define CYBSP_CSD_SLD1_HAL_PORT_PIN P7_1 204 #define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN 205 #define CYBSP_CSD_SLD1 P7_1 206 #define CYBSP_CS_SLD1 CYBSP_CSD_SLD1 207 #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE 208 #define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ 209 #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 210 #define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR 211 #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 212 #define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE 213 #endif //defined (CY_USING_HAL) 214 #define CYBSP_CSD_SLD2_ENABLED 1U 215 #define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED 216 #define CYBSP_CSD_SLD2_PORT GPIO_PRT7 217 #define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT 218 #define CYBSP_CSD_SLD2_PORT_NUM 7U 219 #define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM 220 #define CYBSP_CSD_SLD2_PIN 2U 221 #define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN 222 #define CYBSP_CSD_SLD2_NUM 2U 223 #define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM 224 #define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG 225 #define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE 226 #define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1 227 #define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE 228 #ifndef ioss_0_port_7_pin_2_HSIOM 229 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO 230 #endif 231 #define CYBSP_CSD_SLD2_HSIOM ioss_0_port_7_pin_2_HSIOM 232 #define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM 233 #define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_7_IRQn 234 #define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ 235 #if defined (CY_USING_HAL) 236 #define CYBSP_CSD_SLD2_HAL_PORT_PIN P7_2 237 #define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN 238 #define CYBSP_CSD_SLD2 P7_2 239 #define CYBSP_CS_SLD2 CYBSP_CSD_SLD2 240 #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE 241 #define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ 242 #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 243 #define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR 244 #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 245 #define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE 246 #endif //defined (CY_USING_HAL) 247 #define CYBSP_CSD_SLD3_ENABLED 1U 248 #define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED 249 #define CYBSP_CSD_SLD3_PORT GPIO_PRT7 250 #define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT 251 #define CYBSP_CSD_SLD3_PORT_NUM 7U 252 #define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM 253 #define CYBSP_CSD_SLD3_PIN 3U 254 #define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN 255 #define CYBSP_CSD_SLD3_NUM 3U 256 #define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM 257 #define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG 258 #define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE 259 #define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1 260 #define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE 261 #ifndef ioss_0_port_7_pin_3_HSIOM 262 #define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_GPIO 263 #endif 264 #define CYBSP_CSD_SLD3_HSIOM ioss_0_port_7_pin_3_HSIOM 265 #define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM 266 #define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_7_IRQn 267 #define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ 268 #if defined (CY_USING_HAL) 269 #define CYBSP_CSD_SLD3_HAL_PORT_PIN P7_3 270 #define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN 271 #define CYBSP_CSD_SLD3 P7_3 272 #define CYBSP_CS_SLD3 CYBSP_CSD_SLD3 273 #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE 274 #define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ 275 #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 276 #define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR 277 #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 278 #define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE 279 #endif //defined (CY_USING_HAL) 280 #define CYBSP_CMOD_ENABLED 1U 281 #define CYBSP_CMOD_PORT GPIO_PRT7 282 #define CYBSP_CMOD_PORT_NUM 7U 283 #define CYBSP_CMOD_PIN 7U 284 #define CYBSP_CMOD_NUM 7U 285 #define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG 286 #define CYBSP_CMOD_INIT_DRIVESTATE 1 287 #ifndef ioss_0_port_7_pin_7_HSIOM 288 #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO 289 #endif 290 #define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM 291 #define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn 292 #if defined (CY_USING_HAL) 293 #define CYBSP_CMOD_HAL_PORT_PIN P7_7 294 #define CYBSP_CMOD P7_7 295 #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE 296 #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 297 #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 298 #endif //defined (CY_USING_HAL) 299 #define CYBSP_CSD_BTN0_ENABLED 1U 300 #define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED 301 #define CYBSP_CSD_BTN0_PORT GPIO_PRT8 302 #define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT 303 #define CYBSP_CSD_BTN0_PORT_NUM 8U 304 #define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM 305 #define CYBSP_CSD_BTN0_PIN 0U 306 #define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN 307 #define CYBSP_CSD_BTN0_NUM 0U 308 #define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM 309 #define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG 310 #define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE 311 #define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1 312 #define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE 313 #ifndef ioss_0_port_8_pin_0_HSIOM 314 #define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_GPIO 315 #endif 316 #define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_0_HSIOM 317 #define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM 318 #define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn 319 #define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ 320 #if defined (CY_USING_HAL) 321 #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_0 322 #define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN 323 #define CYBSP_CSD_BTN0 P8_0 324 #define CYBSP_CS_BTN0 CYBSP_CSD_BTN0 325 #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE 326 #define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ 327 #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 328 #define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR 329 #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 330 #define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE 331 #endif //defined (CY_USING_HAL) 332 #define CYBSP_CSD_BTN1_ENABLED 1U 333 #define CYBSP_CS_BTN1_ENABLED CYBSP_CSD_BTN1_ENABLED 334 #define CYBSP_CSD_BTN1_PORT GPIO_PRT8 335 #define CYBSP_CS_BTN1_PORT CYBSP_CSD_BTN1_PORT 336 #define CYBSP_CSD_BTN1_PORT_NUM 8U 337 #define CYBSP_CS_BTN1_PORT_NUM CYBSP_CSD_BTN1_PORT_NUM 338 #define CYBSP_CSD_BTN1_PIN 1U 339 #define CYBSP_CS_BTN1_PIN CYBSP_CSD_BTN1_PIN 340 #define CYBSP_CSD_BTN1_NUM 1U 341 #define CYBSP_CS_BTN1_NUM CYBSP_CSD_BTN1_NUM 342 #define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG 343 #define CYBSP_CS_BTN1_DRIVEMODE CYBSP_CSD_BTN1_DRIVEMODE 344 #define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1 345 #define CYBSP_CS_BTN1_INIT_DRIVESTATE CYBSP_CSD_BTN1_INIT_DRIVESTATE 346 #ifndef ioss_0_port_8_pin_1_HSIOM 347 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO 348 #endif 349 #define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_1_HSIOM 350 #define CYBSP_CS_BTN1_HSIOM CYBSP_CSD_BTN1_HSIOM 351 #define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn 352 #define CYBSP_CS_BTN1_IRQ CYBSP_CSD_BTN1_IRQ 353 #if defined (CY_USING_HAL) 354 #define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_1 355 #define CYBSP_CS_BTN1_HAL_PORT_PIN CYBSP_CSD_BTN1_HAL_PORT_PIN 356 #define CYBSP_CSD_BTN1 P8_1 357 #define CYBSP_CS_BTN1 CYBSP_CSD_BTN1 358 #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE 359 #define CYBSP_CS_BTN1_HAL_IRQ CYBSP_CSD_BTN1_HAL_IRQ 360 #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 361 #define CYBSP_CS_BTN1_HAL_DIR CYBSP_CSD_BTN1_HAL_DIR 362 #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 363 #define CYBSP_CS_BTN1_HAL_DRIVEMODE CYBSP_CSD_BTN1_HAL_DRIVEMODE 364 #endif //defined (CY_USING_HAL) 365 #define CYBSP_CSD_SLD4_ENABLED 1U 366 #define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED 367 #define CYBSP_CSD_SLD4_PORT GPIO_PRT9 368 #define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT 369 #define CYBSP_CSD_SLD4_PORT_NUM 9U 370 #define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM 371 #define CYBSP_CSD_SLD4_PIN 0U 372 #define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN 373 #define CYBSP_CSD_SLD4_NUM 0U 374 #define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM 375 #define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG 376 #define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE 377 #define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1 378 #define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE 379 #ifndef ioss_0_port_9_pin_0_HSIOM 380 #define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO 381 #endif 382 #define CYBSP_CSD_SLD4_HSIOM ioss_0_port_9_pin_0_HSIOM 383 #define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM 384 #define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_9_IRQn 385 #define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ 386 #if defined (CY_USING_HAL) 387 #define CYBSP_CSD_SLD4_HAL_PORT_PIN P9_0 388 #define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN 389 #define CYBSP_CSD_SLD4 P9_0 390 #define CYBSP_CS_SLD4 CYBSP_CSD_SLD4 391 #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE 392 #define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ 393 #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 394 #define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR 395 #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG 396 #define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE 397 #define CYBSP_BT_UART_RTS (P9_2) 398 #define CYBSP_BT_UART_CTS (P9_3) 399 #endif //defined (CY_USING_HAL) 400 401 extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; 402 #if defined (CY_USING_HAL) 403 extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj; 404 #endif //defined (CY_USING_HAL) 405 extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; 406 #if defined (CY_USING_HAL) 407 extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; 408 #endif //defined (CY_USING_HAL) 409 extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; 410 #if defined (CY_USING_HAL) 411 extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; 412 #endif //defined (CY_USING_HAL) 413 extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; 414 #if defined (CY_USING_HAL) 415 extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; 416 #endif //defined (CY_USING_HAL) 417 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config; 418 #define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config 419 #if defined (CY_USING_HAL) 420 extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj; 421 #define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj 422 #endif //defined (CY_USING_HAL) 423 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config; 424 #define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config 425 #if defined (CY_USING_HAL) 426 extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj; 427 #define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj 428 #endif //defined (CY_USING_HAL) 429 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config; 430 #define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config 431 #if defined (CY_USING_HAL) 432 extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj; 433 #define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj 434 #endif //defined (CY_USING_HAL) 435 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config; 436 #define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config 437 #if defined (CY_USING_HAL) 438 extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj; 439 #define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj 440 #endif //defined (CY_USING_HAL) 441 extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config; 442 #if defined (CY_USING_HAL) 443 extern const cyhal_resource_inst_t CYBSP_CMOD_obj; 444 #endif //defined (CY_USING_HAL) 445 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config; 446 #define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config 447 #if defined (CY_USING_HAL) 448 extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj; 449 #define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj 450 #endif //defined (CY_USING_HAL) 451 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config; 452 #define CYBSP_CS_BTN1_config CYBSP_CSD_BTN1_config 453 #if defined (CY_USING_HAL) 454 extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj; 455 #define CYBSP_CS_BTN1_obj CYBSP_CSD_BTN1_obj 456 #endif //defined (CY_USING_HAL) 457 extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config; 458 #define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config 459 #if defined (CY_USING_HAL) 460 extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj; 461 #define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj 462 #endif //defined (CY_USING_HAL) 463 464 void init_cycfg_pins(void); 465 void reserve_cycfg_pins(void); 466 467 #if defined(__cplusplus) 468 } 469 #endif 470 471 472 #endif /* CYCFG_PINS_H */ 473