1 /*! 2 \file drv_usb_regs.h 3 \brief USB cell registers definition and handle macros 4 5 \version 2020-08-04, V1.1.0, firmware for GD32VF103 6 */ 7 8 /* 9 Copyright (c) 2020, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef __DRV_USB_REGS_H 36 #define __DRV_USB_REGS_H 37 38 #include "usb_conf.h" 39 40 #define USBHS_REG_BASE 0x40040000L /*!< base address of USBHS registers */ 41 #define USBFS_REG_BASE 0x50000000L /*!< base address of USBFS registers */ 42 43 #define USBFS_MAX_TX_FIFOS 15U /*!< FIFO number */ 44 45 #define USBFS_MAX_PACKET_SIZE 64U /*!< USBFS max packet size */ 46 #define USBFS_MAX_CHANNEL_COUNT 8U /*!< USBFS host channel count */ 47 #define USBFS_MAX_EP_COUNT 4U /*!< USBFS device endpoint count */ 48 #define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */ 49 50 #define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */ 51 #define USBHS_MAX_CHANNEL_COUNT 12U /*!< USBHS host channel count */ 52 #define USBHS_MAX_EP_COUNT 6U /*!< USBHS device endpoint count */ 53 #define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */ 54 55 #define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ 56 #define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ 57 58 typedef enum 59 { 60 USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ 61 USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ 62 } usb_core_enum; 63 64 enum USB_SPEED { 65 USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */ 66 USB_SPEED_LOW, /*!< USB speed low */ 67 USB_SPEED_FULL, /*!< USB speed full */ 68 USB_SPEED_HIGH, /*!< USB speed high */ 69 }; 70 71 enum usb_reg_offset { 72 USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */ 73 USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */ 74 USB_REG_OFFSET_EP = 0x0020U, 75 USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */ 76 USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */ 77 USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */ 78 USB_REG_OFFSET_CH = 0x0020U, 79 USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */ 80 USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */ 81 USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ 82 }; 83 84 typedef struct 85 { 86 __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ 87 __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ 88 __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ 89 __IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */ 90 __IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */ 91 __IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */ 92 __IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */ 93 __IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */ 94 __IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */ 95 __IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */ 96 __IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */ 97 __IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */ 98 uint32_t Reserved30[2]; /*!< Reserved 030h */ 99 __IO uint32_t GCCFG; /*!< USB global core configuration register 038h */ 100 __IO uint32_t CID; /*!< USB core ID register 03Ch */ 101 uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ 102 __IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */ 103 __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ 104 } usb_gr; 105 106 typedef struct 107 { 108 __IO uint32_t HCTL; /*!< USB host control register 400h */ 109 __IO uint32_t HFT; /*!< USB host frame interval register 404h */ 110 __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ 111 uint32_t Reserved40C; /*!< Reserved 40Ch */ 112 __IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */ 113 __IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */ 114 __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ 115 } usb_hr; 116 117 typedef struct 118 { 119 __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ 120 __IO uint32_t HCHSTCTL; /*!< Reserved 504h */ 121 __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ 122 __IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */ 123 __IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */ 124 __IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/ 125 uint32_t Reserved[2]; 126 } usb_pr; 127 128 typedef struct 129 { 130 __IO uint32_t DCFG; /*!< USB device configuration register 800h */ 131 __IO uint32_t DCTL; /*!< USB device control register 804h */ 132 __IO uint32_t DSTAT; /*!< USB device status register 808h */ 133 uint32_t Reserved0C; /*!< Reserved 80Ch */ 134 __IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */ 135 __IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */ 136 __IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */ 137 __IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */ 138 uint32_t Reserved20; /*!< Reserved 820h */ 139 uint32_t Reserved24; /*!< Reserved 824h */ 140 __IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */ 141 __IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */ 142 __IO uint32_t DTHRCTL; /*!< dev threshold control 830h */ 143 __IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */ 144 __IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */ 145 __IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */ 146 uint32_t Reserved40; /*!< Reserved 840h */ 147 __IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */ 148 uint32_t Reserved48[15]; /*!< Reserved 848-880h */ 149 __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ 150 } usb_dr; 151 152 typedef struct 153 { 154 __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ 155 uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ 156 __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ 157 uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */ 158 __IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */ 159 __IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */ 160 __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ 161 } usb_erin; 162 163 typedef struct 164 { 165 __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ 166 uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ 167 __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ 168 uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */ 169 __IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */ 170 __IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */ 171 } usb_erout; 172 173 typedef struct _usb_regs 174 { 175 usb_gr *gr; /*!< USBFS global registers */ 176 usb_dr *dr; /*!< Device control and status registers */ 177 usb_hr *hr; /*!< Host control and status registers */ 178 usb_erin *er_in[6]; /*!< USB device IN endpoint register */ 179 usb_erout *er_out[6]; /*!< USB device OUT endpoint register */ 180 usb_pr *pr[15]; /*!< USB Host channel-x control register */ 181 182 __IO uint32_t *HPCS; /*!< USB host port control and status register */ 183 __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; 184 __IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */ 185 } usb_core_regs; 186 187 /* global OTG control and status register bits definitions */ 188 #define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ 189 #define GOTGCS_ASV BIT(18) /*!< A-session valid */ 190 #define GOTGCS_DI BIT(17) /*!< debounce interval */ 191 #define GOTGCS_CIDPS BIT(16) /*!< id pin status */ 192 #define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ 193 #define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ 194 #define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ 195 #define GOTGCS_HNPS BIT(8) /*!< HNP successes */ 196 #define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ 197 #define GOTGCS_SRPS BIT(0) /*!< SRP successes */ 198 199 /* global OTG interrupt flag register bits definitions */ 200 #define GOTGINTF_DF BIT(19) /*!< debounce finish */ 201 #define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ 202 #define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ 203 #define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ 204 #define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ 205 #define GOTGINTF_SESEND BIT(2) /*!< session end */ 206 207 /* global AHB control and status register bits definitions */ 208 #define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ 209 #define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ 210 #define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ 211 #define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ 212 #define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ 213 214 /* global USB control and status register bits definitions */ 215 #define GUSBCS_FDM BIT(30) /*!< force device mode */ 216 #define GUSBCS_FHM BIT(29) /*!< force host mode */ 217 #define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ 218 #define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ 219 #define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ 220 #define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ 221 #define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ 222 #define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ 223 #define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ 224 225 /* global reset control register bits definitions */ 226 #define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ 227 #define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ 228 #define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ 229 #define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ 230 #define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ 231 #define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ 232 #define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ 233 #define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ 234 235 /* global interrupt flag register bits definitions */ 236 #define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ 237 #define GINTF_SESIF BIT(30) /*!< session interrupt flag */ 238 #define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ 239 #define GINTF_IDPSC BIT(28) /*!< id pin status change */ 240 #define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ 241 #define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ 242 #define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ 243 #define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ 244 #define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ 245 #define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ 246 #define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ 247 #define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ 248 #define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ 249 #define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ 250 #define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ 251 #define GINTF_RST BIT(12) /*!< USB reset */ 252 #define GINTF_SP BIT(11) /*!< USB suspend */ 253 #define GINTF_ESP BIT(10) /*!< early suspend */ 254 #define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ 255 #define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ 256 #define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ 257 #define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ 258 #define GINTF_SOF BIT(3) /*!< start of frame */ 259 #define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ 260 #define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ 261 #define GINTF_COPM BIT(0) /*!< current operation mode */ 262 263 /* global interrupt enable register bits definitions */ 264 #define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ 265 #define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ 266 #define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ 267 #define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ 268 #define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ 269 #define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ 270 #define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ 271 #define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ 272 #define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ 273 #define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ 274 #define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ 275 #define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ 276 #define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ 277 #define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ 278 #define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ 279 #define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ 280 #define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ 281 #define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ 282 #define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ 283 #define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ 284 #define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ 285 #define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ 286 #define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ 287 #define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ 288 #define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ 289 290 /* global receive status read and pop register bits definitions */ 291 #define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ 292 #define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ 293 #define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ 294 #define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ 295 #define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ 296 297 /* global receive FIFO length register bits definitions */ 298 #define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ 299 300 /* host non-periodic transmit FIFO length register bits definitions */ 301 #define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ 302 #define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ 303 304 /* USB IN endpoint 0 transmit FIFO length register bits definitions */ 305 #define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ 306 #define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ 307 308 /* host non-periodic transmit FIFO/queue status register bits definitions */ 309 #define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ 310 #define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ 311 #define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ 312 #define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ 313 #define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ 314 #define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ 315 #define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ 316 317 /* global core configuration register bits definitions */ 318 #define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ 319 #define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ 320 #define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ 321 #define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ 322 #define GCCFG_PWRON BIT(16) /*!< power on */ 323 324 /* core ID register bits definitions */ 325 #define CID_CID BITS(0, 31) /*!< core ID */ 326 327 /* host periodic transmit FIFO length register bits definitions */ 328 #define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ 329 #define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ 330 331 /* device IN endpoint transmit FIFO length register bits definitions */ 332 #define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ 333 #define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ 334 335 /* host control register bits definitions */ 336 #define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ 337 #define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ 338 339 /* host frame interval register bits definitions */ 340 #define HFT_FRI BITS(0, 15) /*!< frame interval */ 341 342 /* host frame information remaining register bits definitions */ 343 #define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ 344 #define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ 345 346 /* host periodic transmit FIFO/queue status register bits definitions */ 347 #define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ 348 #define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ 349 #define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ 350 #define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ 351 #define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ 352 #define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ 353 #define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ 354 #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ 355 356 #define TFQSTAT_TXFS BITS(0, 15) 357 #define TFQSTAT_CNUM BITS(27, 30) 358 359 /* host all channels interrupt register bits definitions */ 360 #define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ 361 362 /* host all channels interrupt enable register bits definitions */ 363 #define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ 364 365 /* host port control and status register bits definitions */ 366 #define HPCS_PS BITS(17, 18) /*!< port speed */ 367 #define HPCS_PP BIT(12) /*!< port power */ 368 #define HPCS_PLST BITS(10, 11) /*!< port line status */ 369 #define HPCS_PRST BIT(8) /*!< port reset */ 370 #define HPCS_PSP BIT(7) /*!< port suspend */ 371 #define HPCS_PREM BIT(6) /*!< port resume */ 372 #define HPCS_PEDC BIT(3) /*!< port enable/disable change */ 373 #define HPCS_PE BIT(2) /*!< port enable */ 374 #define HPCS_PCD BIT(1) /*!< port connect detected */ 375 #define HPCS_PCST BIT(0) /*!< port connect status */ 376 377 /* host channel-x control register bits definitions */ 378 #define HCHCTL_CEN BIT(31) /*!< channel enable */ 379 #define HCHCTL_CDIS BIT(30) /*!< channel disable */ 380 #define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ 381 #define HCHCTL_DAR BITS(22, 28) /*!< device address */ 382 #define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ 383 #define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ 384 #define HCHCTL_LSD BIT(17) /*!< low-speed device */ 385 #define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ 386 #define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ 387 #define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ 388 389 /* host channel-x split transaction register bits definitions */ 390 #define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ 391 #define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ 392 #define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ 393 #define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ 394 #define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ 395 396 /* host channel-x interrupt flag register bits definitions */ 397 #define HCHINTF_DTER BIT(10) /*!< data toggle error */ 398 #define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ 399 #define HCHINTF_BBER BIT(8) /*!< babble error */ 400 #define HCHINTF_USBER BIT(7) /*!< USB bus Error */ 401 #define HCHINTF_NYET BIT(6) /*!< NYET */ 402 #define HCHINTF_ACK BIT(5) /*!< ACK */ 403 #define HCHINTF_NAK BIT(4) /*!< NAK */ 404 #define HCHINTF_STALL BIT(3) /*!< STALL */ 405 #define HCHINTF_DMAER BIT(2) /*!< DMA error */ 406 #define HCHINTF_CH BIT(1) /*!< channel halted */ 407 #define HCHINTF_TF BIT(0) /*!< transfer finished */ 408 409 /* host channel-x interrupt enable register bits definitions */ 410 #define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ 411 #define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ 412 #define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ 413 #define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ 414 #define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ 415 #define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ 416 #define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ 417 #define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ 418 #define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ 419 #define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ 420 #define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ 421 422 /* host channel-x transfer length register bits definitions */ 423 #define HCHLEN_PING BIT(31) /*!< PING token request */ 424 #define HCHLEN_DPID BITS(29, 30) /*!< data PID */ 425 #define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ 426 #define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ 427 428 /* host channel-x DMA address register bits definitions */ 429 #define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ 430 431 #define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ 432 433 #define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ 434 #define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ 435 #define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ 436 437 #define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ 438 #define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ 439 #define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11) & HCHCTL_EPNUM) /*!< endpoint number */ 440 #define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15) & HCHCTL_EPDIR) /*!< endpoint direction */ 441 #define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0) & HCHCTL_MPL) /*!< maximum packet length */ 442 #define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17) & HCHCTL_LSD) /*!< low-Speed device */ 443 444 #define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19) & HCHLEN_PCNT) /*!< packet count */ 445 #define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29) & HCHLEN_DPID) /*!< data PID */ 446 447 #define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */ 448 #define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */ 449 #define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */ 450 #define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */ 451 452 extern const uint32_t PIPE_DPID[2]; 453 454 /* device configuration registers bits definitions */ 455 #define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ 456 #define DCFG_DAR BITS(4, 10) /*!< device address */ 457 #define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ 458 #define DCFG_DS BITS(0, 1) /*!< device speed */ 459 460 /* device control registers bits definitions */ 461 #define DCTL_POIF BIT(11) /*!< power-on initialization finished */ 462 #define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ 463 #define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ 464 #define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ 465 #define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ 466 #define DCTL_GONS BIT(3) /*!< global OUT NAK status */ 467 #define DCTL_GINS BIT(2) /*!< global IN NAK status */ 468 #define DCTL_SD BIT(1) /*!< soft disconnect */ 469 #define DCTL_RWKUP BIT(0) /*!< remote wakeup */ 470 471 /* device status registers bits definitions */ 472 #define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ 473 #define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ 474 #define DSTAT_SPST BIT(0) /*!< suspend status */ 475 476 /* device IN endpoint common interrupt enable registers bits definitions */ 477 #define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ 478 #define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ 479 #define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ 480 #define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ 481 #define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ 482 #define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ 483 #define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ 484 485 /* device OUT endpoint common interrupt enable registers bits definitions */ 486 #define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ 487 #define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ 488 #define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ 489 #define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ 490 #define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ 491 #define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ 492 493 /* device all endpoints interrupt registers bits definitions */ 494 #define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ 495 #define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ 496 497 /* device all endpoints interrupt enable registers bits definitions */ 498 #define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ 499 #define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ 500 501 /* device Vbus discharge time registers bits definitions */ 502 #define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ 503 504 /* device Vbus pulsing time registers bits definitions */ 505 #define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ 506 507 /* device IN endpoint FIFO empty interrupt enable register bits definitions */ 508 #define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ 509 510 /* device endpoint 0 control register bits definitions */ 511 #define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ 512 #define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ 513 #define DEP0CTL_SNAK BIT(27) /*!< set NAK */ 514 #define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ 515 #define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ 516 #define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ 517 #define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ 518 #define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ 519 #define DEP0CTL_NAKS BIT(17) /*!< NAK status */ 520 #define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ 521 #define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ 522 523 /* device endpoint x control register bits definitions */ 524 #define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ 525 #define DEPCTL_EPD BIT(30) /*!< endpoint disable */ 526 #define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ 527 #define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ 528 #define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ 529 #define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ 530 #define DEPCTL_SNAK BIT(27) /*!< set NAK */ 531 #define DEPCTL_CNAK BIT(26) /*!< clear NAK */ 532 #define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ 533 #define DEPCTL_STALL BIT(21) /*!< STALL handshake */ 534 #define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ 535 #define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ 536 #define DEPCTL_NAKS BIT(17) /*!< NAK status */ 537 #define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ 538 #define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ 539 #define DEPCTL_EPACT BIT(15) /*!< endpoint active */ 540 #define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ 541 542 /* device IN endpoint-x interrupt flag register bits definitions */ 543 #define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ 544 #define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ 545 #define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ 546 #define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ 547 #define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ 548 #define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ 549 #define DIEPINTF_TF BIT(0) /*!< transfer finished */ 550 551 /* device OUT endpoint-x interrupt flag register bits definitions */ 552 #define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ 553 #define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ 554 #define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ 555 #define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ 556 #define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ 557 #define DOEPINTF_TF BIT(0) /*!< transfer finished */ 558 559 /* device IN endpoint 0 transfer length register bits definitions */ 560 #define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ 561 #define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ 562 563 /* device OUT endpoint 0 transfer length register bits definitions */ 564 #define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ 565 #define DOEP0LEN_PCNT BIT(19) /*!< packet count */ 566 #define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ 567 568 /* device OUT endpoint-x transfer length register bits definitions */ 569 #define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ 570 #define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ 571 #define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ 572 #define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ 573 #define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ 574 575 /* device IN endpoint-x DMA address register bits definitions */ 576 #define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ 577 578 /* device OUT endpoint-x DMA address register bits definitions */ 579 #define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ 580 581 /* device IN endpoint-x transmit FIFO status register bits definitions */ 582 #define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ 583 584 /* USB power and clock registers bits definition */ 585 #define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ 586 #define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ 587 588 #define RSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ 589 #define RSTAT_DATA_UPDT 2U /* OUT data packet received */ 590 #define RSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ 591 #define RSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ 592 #define RSTAT_SETUP_UPDT 6U /* SETUP data packet received */ 593 594 #define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ 595 #define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ 596 #define DSTAT_EM_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ 597 #define DSTAT_EM_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ 598 599 #define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ 600 #define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ 601 #define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ 602 #define DPID_MDATA 3U /* device endpoint data PID is MDATA */ 603 604 #define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1)) /*!< AHB burst type used by DMA*/ 605 606 #define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ 607 #define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ 608 #define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ 609 #define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ 610 #define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ 611 612 #define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11)) /*!< end of periodic frame time configuration */ 613 614 #define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ 615 #define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ 616 #define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ 617 #define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ 618 619 #define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ 620 621 #define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ 622 #define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ 623 #define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ 624 625 #define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ 626 627 #define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ 628 #define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ 629 #define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ 630 #define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ 631 632 #define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0)) /*!< Transfer length */ 633 #define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19)) /*!< Packet count */ 634 #define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29)) /*!< SETUP packet count */ 635 636 #define USB_ULPI_PHY 1U /*!< ULPI interface external PHY */ 637 #define USB_EMBEDDED_PHY 2U /*!< Embedded PHY */ 638 639 #define GRXSTS_PKTSTS_IN 2U 640 #define GRXSTS_PKTSTS_IN_XFER_COMP 3U 641 #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U 642 #define GRXSTS_PKTSTS_CH_HALTED 7U 643 644 #define HCTL_30_60MHZ 0U /*!< USB clock 30-60MHZ */ 645 #define HCTL_48MHZ 1U /*!< USB clock 48MHZ */ 646 #define HCTL_6MHZ 2U /*!< USB clock 6MHZ */ 647 648 #define EP0_OUT ((uint8_t)0x00) /*!< endpoint out 0 */ 649 #define EP0_IN ((uint8_t)0x80) /*!< endpoint in 0 */ 650 #define EP1_OUT ((uint8_t)0x01) /*!< endpoint out 1 */ 651 #define EP1_IN ((uint8_t)0x81) /*!< endpoint in 1 */ 652 #define EP2_OUT ((uint8_t)0x02) /*!< endpoint out 2 */ 653 #define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */ 654 #define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */ 655 #define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */ 656 657 #endif /* __DRV_USB_REGS_H */ 658