1 //###########################################################################
2 //
3 // FILE: F2837xD_DMA.c
4 //
5 // TITLE: F2837xD Device DMA Initialization & Support Functions.
6 //
7 //###########################################################################
8 // $TI Release: F2837xD Support Library v3.05.00.00 $
9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
10 // $Copyright:
11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
12 //
13 // Redistribution and use in source and binary forms, with or without
14 // modification, are permitted provided that the following conditions
15 // are met:
16 //
17 // Redistributions of source code must retain the above copyright
18 // notice, this list of conditions and the following disclaimer.
19 //
20 // Redistributions in binary form must reproduce the above copyright
21 // notice, this list of conditions and the following disclaimer in the
22 // documentation and/or other materials provided with the
23 // distribution.
24 //
25 // Neither the name of Texas Instruments Incorporated nor the names of
26 // its contributors may be used to endorse or promote products derived
27 // from this software without specific prior written permission.
28 //
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 // $
41 //###########################################################################
42
43 //
44 // Included Files
45 //
46 #include "F2837xD_device.h"
47 #include "F2837xD_Examples.h"
48
49 //
50 // DMAInitialize - This function initializes the DMA to a known state.
51 //
DMAInitialize(void)52 void DMAInitialize(void)
53 {
54 EALLOW;
55
56 //
57 // Perform a hard reset on DMA
58 //
59 DmaRegs.DMACTRL.bit.HARDRESET = 1;
60 __asm (" nop"); // one NOP required after HARDRESET
61
62 //
63 // Allow DMA to run free on emulation suspend
64 //
65 DmaRegs.DEBUGCTRL.bit.FREE = 1;
66
67 EDIS;
68 }
69
70 //
71 // DMACH1AddrConfig - DMA Channel 1 Address Configuration
72 //
DMACH1AddrConfig(volatile Uint16 * DMA_Dest,volatile Uint16 * DMA_Source)73 void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
74 {
75 EALLOW;
76
77 //
78 // Set up SOURCE address:
79 //
80 DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to
81 // beginning of
82 // source buffer
83 DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
84
85 //
86 // Set up DESTINATION address:
87 //
88 DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to
89 // beginning of
90 // destination buffer
91 DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
92
93 EDIS;
94 }
95
96 //
97 // DMACH1BurstConfig - DMA Channel 1 Burst size configuration
98 //
DMACH1BurstConfig(Uint16 bsize,int16 srcbstep,int16 desbstep)99 void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
100 {
101 EALLOW;
102
103 //
104 // Set up BURST registers:
105 //
106 DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1)
107 // x-ferred in a burst.
108 DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between
109 // each word x-ferred.
110 DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between
111 // each word x-ferred.
112
113 EDIS;
114 }
115
116 //
117 // DMACH1TransferConfig - DMA Channel 1 Transfer size configuration
118 //
DMACH1TransferConfig(Uint16 tsize,int16 srctstep,int16 deststep)119 void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
120 {
121 EALLOW;
122
123 //
124 // Set up TRANSFER registers:
125 //
126 DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
127 // DMA interrupt will occur after
128 // completed transfer.
129 DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored
130 // when WRAP occurs.
131 DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored
132 // when WRAP occurs.
133
134 EDIS;
135 }
136
137 //
138 // DMACH1WrapConfig - DMA Channel 1 Wrap size configuration
139 //
DMACH1WrapConfig(Uint16 srcwsize,int16 srcwstep,Uint16 deswsize,int16 deswstep)140 void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
141 int16 deswstep)
142 {
143 EALLOW;
144
145 //
146 // Set up WRAP registers:
147 //
148 DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
149 DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap
150
151 DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after
152 // N bursts.
153 DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap
154
155 EDIS;
156 }
157
158 //
159 // DMACH1ModeConfig - DMA Channel 1 Mode configuration
160 //
DMACH1ModeConfig(Uint16 persel,Uint16 perinte,Uint16 oneshot,Uint16 cont,Uint16 synce,Uint16 syncsel,Uint16 ovrinte,Uint16 datasize,Uint16 chintmode,Uint16 chinte)161 void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
162 Uint16 cont, Uint16 synce, Uint16 syncsel,
163 Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
164 Uint16 chinte)
165 {
166 EALLOW;
167
168 //
169 // Set up MODE Register:
170 // persel - Source select
171 // PERINTSEL - Should be hard coded to channel, above now selects source
172 // PERINTE - Peripheral interrupt enable
173 // ONESHOT - Oneshot enable
174 // CONTINUOUS - Continuous enable
175 // OVRINTE - Enable/disable the overflow interrupt
176 // DATASIZE - 16-bit/32-bit data size transfers
177 // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
178 // CHINTE - Channel Interrupt to CPU enable
179 //
180 DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel;
181 DmaRegs.CH1.MODE.bit.PERINTSEL = 1;
182 DmaRegs.CH1.MODE.bit.PERINTE = perinte;
183 DmaRegs.CH1.MODE.bit.ONESHOT = oneshot;
184 DmaRegs.CH1.MODE.bit.CONTINUOUS = cont;
185 DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte;
186 DmaRegs.CH1.MODE.bit.DATASIZE = datasize;
187 DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode;
188 DmaRegs.CH1.MODE.bit.CHINTE = chinte;
189
190 //
191 // Clear any spurious flags: interrupt and sync error flags
192 //
193 DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;
194 DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;
195
196 //
197 // Initialize PIE vector for CPU interrupt:
198 // Enable DMA CH1 interrupt in PIE
199 //
200 PieCtrlRegs.PIEIER7.bit.INTx1 = 1;
201
202 EDIS;
203 }
204
205 //
206 // StartDMACH1 - This function starts DMA Channel 1.
207 //
StartDMACH1(void)208 void StartDMACH1(void)
209 {
210 EALLOW;
211 DmaRegs.CH1.CONTROL.bit.RUN = 1;
212 EDIS;
213 }
214
215 //
216 // DMACH2AddrConfig - DMA Channel 2 Address Configuration
217 //
DMACH2AddrConfig(volatile Uint16 * DMA_Dest,volatile Uint16 * DMA_Source)218 void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
219 {
220 EALLOW;
221
222 //
223 // Set up SOURCE address:
224 //
225 DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to
226 // beginning of
227 // source buffer.
228 DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
229
230 //
231 // Set up DESTINATION address:
232 //
233 DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
234 // of destination
235 // buffer.
236 DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
237
238 EDIS;
239 }
240
241 //
242 // DMACH2BurstConfig - DMA Channel 2 Burst size configuration
243 //
DMACH2BurstConfig(Uint16 bsize,int16 srcbstep,int16 desbstep)244 void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
245 {
246 EALLOW;
247
248 //
249 // Set up BURST registers:
250 //
251 DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
252 // a burst.
253 DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between
254 // each word x-ferred.
255 DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each
256 // word x-ferred.
257
258 EDIS;
259 }
260
261 //
262 // DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration
263 //
DMACH2TransferConfig(Uint16 tsize,int16 srctstep,int16 deststep)264 void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
265 {
266 EALLOW;
267
268 //
269 // Set up TRANSFER registers:
270 //
271 DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
272 // DMA interrupt will occur after
273 // completed transfer.
274 DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
275 // WRAP occurs.
276 DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
277 // WRAP occurs.
278
279 EDIS;
280 }
281
282 //
283 // DMACH2WrapConfig - DMA Channel 2 Wrap size configuration
284 //
DMACH2WrapConfig(Uint16 srcwsize,int16 srcwstep,Uint16 deswsize,int16 deswstep)285 void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
286 int16 deswstep)
287 {
288 EALLOW;
289
290 //
291 // Set up WRAP registers:
292 //
293 DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
294 DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap
295
296 DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after
297 // N bursts.
298 DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap
299
300 EDIS;
301 }
302
303 //
304 // DMACH2ModeConfig - DMA Channel 2 Mode configuration
305 //
DMACH2ModeConfig(Uint16 persel,Uint16 perinte,Uint16 oneshot,Uint16 cont,Uint16 synce,Uint16 syncsel,Uint16 ovrinte,Uint16 datasize,Uint16 chintmode,Uint16 chinte)306 void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
307 Uint16 cont, Uint16 synce, Uint16 syncsel,
308 Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
309 Uint16 chinte)
310 {
311 EALLOW;
312
313 //
314 // Set up MODE Register:
315 // persel - Source select
316 // PERINTSEL - Should be hard coded to channel, above now selects source
317 // PERINTE - Peripheral interrupt enable
318 // ONESHOT - Oneshot enable
319 // CONTINUOUS - Continuous enable
320 // OVRINTE - Enable/disable the overflow interrupt
321 // DATASIZE - 16-bit/32-bit data size transfers
322 // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
323 // CHINTE - Channel Interrupt to CPU enable
324 //
325 DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel;
326 DmaRegs.CH2.MODE.bit.PERINTSEL = 2;
327 DmaRegs.CH2.MODE.bit.PERINTE = perinte;
328 DmaRegs.CH2.MODE.bit.ONESHOT = oneshot;
329 DmaRegs.CH2.MODE.bit.CONTINUOUS = cont;
330 DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte;
331 DmaRegs.CH2.MODE.bit.DATASIZE = datasize;
332 DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode;
333 DmaRegs.CH2.MODE.bit.CHINTE = chinte;
334
335 //
336 // Clear any spurious flags: Interrupt flags and sync error flags
337 //
338 DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1;
339 DmaRegs.CH2.CONTROL.bit.ERRCLR = 1;
340
341 //
342 // Initialize PIE vector for CPU interrupt:
343 // Enable DMA CH2 interrupt in PIE
344 //
345 PieCtrlRegs.PIEIER7.bit.INTx2 = 1;
346
347 EDIS;
348 }
349
350 //
351 // StartDMACH2 - This function starts DMA Channel 2.
352 //
StartDMACH2(void)353 void StartDMACH2(void)
354 {
355 EALLOW;
356 DmaRegs.CH2.CONTROL.bit.RUN = 1;
357 EDIS;
358 }
359
360 //
361 // DMACH3AddrConfig - DMA Channel 3 Address configuration
362 //
DMACH3AddrConfig(volatile Uint16 * DMA_Dest,volatile Uint16 * DMA_Source)363 void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
364 {
365 EALLOW;
366
367 //
368 // Set up SOURCE address:
369 //
370 DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
371 // of source buffer.
372 DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
373
374 //
375 // Set up DESTINATION address:
376 //
377 DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
378 // of destination
379 // buffer.
380 DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
381
382 EDIS;
383 }
384
385 //
386 // DMACH3BurstConfig - DMA Channel 3 burst size configuration
387 //
DMACH3BurstConfig(Uint16 bsize,int16 srcbstep,int16 desbstep)388 void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
389 {
390 EALLOW;
391
392 //
393 // Set up BURST registers:
394 //
395 DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
396 // a burst.
397 DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between
398 // each word x-ferred.
399 DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each
400 // word x-ferred.
401
402 EDIS;
403 }
404
405 //
406 // DMACH3TransferConfig - DMA channel 3 transfer size configuration
407 //
DMACH3TransferConfig(Uint16 tsize,int16 srctstep,int16 deststep)408 void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
409 {
410 EALLOW;
411
412 //
413 // Set up TRANSFER registers:
414 //
415 DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
416 // DMA interrupt will occur after
417 // completed transfer.
418 DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
419 // WRAP occurs.
420 DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
421 // WRAP occurs.
422
423 EDIS;
424 }
425
426 //
427 // DMACH3WrapConfig - DMA Channel 3 wrap size configuration
428 //
DMACH3WrapConfig(Uint16 srcwsize,int16 srcwstep,Uint16 deswsize,int16 deswstep)429 void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
430 int16 deswstep)
431 {
432 EALLOW;
433
434 //
435 // Set up WRAP registers:
436 //
437 DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
438 DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap
439
440 DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N
441 // bursts.
442 DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap
443
444 EDIS;
445 }
446
447 //
448 // DMACH3ModeConfig - DMA Channel 3 mode configuration
449 //
DMACH3ModeConfig(Uint16 persel,Uint16 perinte,Uint16 oneshot,Uint16 cont,Uint16 synce,Uint16 syncsel,Uint16 ovrinte,Uint16 datasize,Uint16 chintmode,Uint16 chinte)450 void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
451 Uint16 cont, Uint16 synce, Uint16 syncsel,
452 Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
453 Uint16 chinte)
454 {
455 EALLOW;
456
457 //
458 // Set up MODE Register:
459 // persel - Source select
460 // PERINTSEL - Should be hard coded to channel, above now selects source
461 // PERINTE - Peripheral interrupt enable
462 // ONESHOT - Oneshot enable
463 // CONTINUOUS - Continuous enable
464 // OVRINTE - Enable/disable the overflow interrupt
465 // DATASIZE - 16-bit/32-bit data size transfers
466 // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
467 // CHINTE - Channel Interrupt to CPU enable
468 //
469 DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel;
470 DmaRegs.CH3.MODE.bit.PERINTSEL = 3;
471 DmaRegs.CH3.MODE.bit.PERINTE = perinte;
472 DmaRegs.CH3.MODE.bit.ONESHOT = oneshot;
473 DmaRegs.CH3.MODE.bit.CONTINUOUS = cont;
474 DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte;
475 DmaRegs.CH3.MODE.bit.DATASIZE = datasize;
476 DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode;
477 DmaRegs.CH3.MODE.bit.CHINTE = chinte;
478
479 //
480 // Clear any spurious flags: interrupt flags and sync error flags
481 //
482 DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1;
483 DmaRegs.CH3.CONTROL.bit.ERRCLR = 1;
484
485 //
486 // Initialize PIE vector for CPU interrupt:
487 // Enable DMA CH3 interrupt in PIE
488 //
489 PieCtrlRegs.PIEIER7.bit.INTx3 = 1;
490
491 EDIS;
492 }
493
494 //
495 // StartDMACH3 - This function starts DMA Channel 3.
496 //
StartDMACH3(void)497 void StartDMACH3(void)
498 {
499 EALLOW;
500 DmaRegs.CH3.CONTROL.bit.RUN = 1;
501 EDIS;
502 }
503
504 //
505 // DMACH4AddrConfig - DMA Channel 4 address configuration
506 //
DMACH4AddrConfig(volatile Uint16 * DMA_Dest,volatile Uint16 * DMA_Source)507 void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
508 {
509 EALLOW;
510
511 //
512 // Set up SOURCE address:
513 //
514 DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
515 // of source buffer.
516 DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
517
518 //
519 // Set up DESTINATION address:
520 //
521 DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
522 // of destination
523 // buffer.
524 DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
525
526 EDIS;
527 }
528
529 //
530 // DMACH4BurstConfig - DMA Channel 4 burst size configuration
531 //
DMACH4BurstConfig(Uint16 bsize,int16 srcbstep,int16 desbstep)532 void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
533 {
534 EALLOW;
535
536 //
537 // Set up BURST registers:
538 //
539 DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
540 // a burst.
541 DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between
542 // each word x-ferred.
543 DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each
544 // word x-ferred.
545
546 EDIS;
547 }
548
549 //
550 // DMACH4TransferConfig - DMA channel 4 transfer size configuration
551 //
DMACH4TransferConfig(Uint16 tsize,int16 srctstep,int16 deststep)552 void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
553 {
554 EALLOW;
555
556 //
557 // Set up TRANSFER registers:
558 //
559 DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
560 // DMA interrupt will occur after
561 // completed transfer.
562 DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
563 // WRAP occurs.
564 DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
565 // WRAP occurs.
566
567 EDIS;
568 }
569
570 //
571 // DMACH4WrapConfig - DMA channel 4 wrap size configuration
572 //
DMACH4WrapConfig(Uint16 srcwsize,int16 srcwstep,Uint16 deswsize,int16 deswstep)573 void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
574 int16 deswstep)
575 {
576 EALLOW;
577
578 //
579 // Set up WRAP registers:
580 //
581 DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
582 DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap
583
584 DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after
585 // N bursts.
586 DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap
587
588 EDIS;
589 }
590
591 //
592 // DMACH4ModeConfig - DMA Channel 4 mode configuration
593 //
DMACH4ModeConfig(Uint16 persel,Uint16 perinte,Uint16 oneshot,Uint16 cont,Uint16 synce,Uint16 syncsel,Uint16 ovrinte,Uint16 datasize,Uint16 chintmode,Uint16 chinte)594 void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
595 Uint16 cont, Uint16 synce, Uint16 syncsel,
596 Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
597 Uint16 chinte)
598 {
599 EALLOW;
600
601 //
602 // Set up MODE Register:
603 // persel - Source select
604 // PERINTSEL - Should be hard coded to channel, above now selects source
605 // PERINTE - Peripheral interrupt enable
606 // ONESHOT - Oneshot enable
607 // CONTINUOUS - Continuous enable
608 // OVRINTE - Enable/disable the overflow interrupt
609 // DATASIZE - 16-bit/32-bit data size transfers
610 // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
611 // CHINTE - Channel Interrupt to CPU enable
612 //
613 DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel;
614 DmaRegs.CH4.MODE.bit.PERINTSEL = 4;
615 DmaRegs.CH4.MODE.bit.PERINTE = perinte;
616 DmaRegs.CH4.MODE.bit.ONESHOT = oneshot;
617 DmaRegs.CH4.MODE.bit.CONTINUOUS = cont;
618 DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte;
619 DmaRegs.CH4.MODE.bit.DATASIZE = datasize;
620 DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode;
621 DmaRegs.CH4.MODE.bit.CHINTE = chinte;
622
623 //
624 // Clear any spurious flags: Interrupt flags and sync error flags
625 //
626 DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1;
627 DmaRegs.CH4.CONTROL.bit.ERRCLR = 1;
628
629 //
630 // Initialize PIE vector for CPU interrupt:
631 // Enable DMA CH4 interrupt in PIE
632 //
633 PieCtrlRegs.PIEIER7.bit.INTx4 = 1;
634
635 EDIS;
636 }
637
638 //
639 // StartDMACH4 - This function starts DMA Channel 4.
640 //
StartDMACH4(void)641 void StartDMACH4(void)
642 {
643 EALLOW;
644 DmaRegs.CH4.CONTROL.bit.RUN = 1;
645 EDIS;
646 }
647
648 //
649 // DMACH5AddrConfig - DMA channel 5 address configuration
650 //
DMACH5AddrConfig(volatile Uint16 * DMA_Dest,volatile Uint16 * DMA_Source)651 void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
652 {
653 EALLOW;
654
655 //
656 // Set up SOURCE address:
657 //
658 DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
659 // of source buffer
660 DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
661
662 //
663 // Set up DESTINATION address:
664 //
665 DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
666 // of destination
667 // buffer.
668 DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
669
670 EDIS;
671 }
672
673 //
674 // DMACH5BurstConfig - DMA Channel 5 burst size configuration
675 //
DMACH5BurstConfig(Uint16 bsize,int16 srcbstep,int16 desbstep)676 void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
677 {
678 EALLOW;
679
680 //
681 // Set up BURST registers:
682 //
683 DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
684 // a burst.
685 DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between
686 // each word x-ferred.
687 DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each
688 // word x-ferred.
689
690 EDIS;
691 }
692
693 //
694 // DMACH5TransferConfig - DMA channel 5 transfer size configuration
695 //
DMACH5TransferConfig(Uint16 tsize,int16 srctstep,int16 deststep)696 void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
697 {
698 EALLOW;
699
700 //
701 // Set up TRANSFER registers:
702 //
703 DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
704 // DMA interrupt will occur after
705 // completed transfer.
706 DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
707 // WRAP occurs.
708 DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
709 // WRAP occurs.
710
711 EDIS;
712 }
713
714 //
715 // DMACH5WrapConfig - DMA Channel 5 wrap size configuration
716 //
DMACH5WrapConfig(Uint16 srcwsize,int16 srcwstep,Uint16 deswsize,int16 deswstep)717 void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
718 int16 deswstep)
719 {
720 EALLOW;
721
722 //
723 // Set up WRAP registers:
724 //
725 DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
726 DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap
727
728 DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after
729 // N bursts.
730 DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap
731
732 EDIS;
733 }
734
735 //
736 // DMACH5ModeConfig - DMA Channel 5 mode configuration
737 //
DMACH5ModeConfig(Uint16 persel,Uint16 perinte,Uint16 oneshot,Uint16 cont,Uint16 synce,Uint16 syncsel,Uint16 ovrinte,Uint16 datasize,Uint16 chintmode,Uint16 chinte)738 void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
739 Uint16 cont, Uint16 synce, Uint16 syncsel,
740 Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
741 Uint16 chinte)
742 {
743 EALLOW;
744
745 //
746 // Set up MODE Register:
747 // persel - Source select
748 // PERINTSEL - Should be hard coded to channel, above now selects source
749 // PERINTE - Peripheral interrupt enable
750 // ONESHOT - Oneshot enable
751 // CONTINUOUS - Continuous enable
752 // OVRINTE - Enable/disable the overflow interrupt
753 // DATASIZE - 16-bit/32-bit data size transfers
754 // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
755 // CHINTE - Channel Interrupt to CPU enable
756 //
757 DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel;
758 DmaRegs.CH5.MODE.bit.PERINTSEL = 5;
759 DmaRegs.CH5.MODE.bit.PERINTE = perinte;
760 DmaRegs.CH5.MODE.bit.ONESHOT = oneshot;
761 DmaRegs.CH5.MODE.bit.CONTINUOUS = cont;
762 DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte;
763 DmaRegs.CH5.MODE.bit.DATASIZE = datasize;
764 DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode;
765 DmaRegs.CH5.MODE.bit.CHINTE = chinte;
766
767 //
768 // Clear any spurious flags: Interrupt flags and sync error flags
769 //
770 DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1;
771 DmaRegs.CH5.CONTROL.bit.ERRCLR = 1;
772
773 //
774 // Initialize PIE vector for CPU interrupt:
775 // Enable DMA CH5 interrupt in PIE
776 //
777 PieCtrlRegs.PIEIER7.bit.INTx5 = 1;
778
779 EDIS;
780 }
781
782 //
783 // StartDMACH5 - This function starts DMA Channel 5.
784 //
StartDMACH5(void)785 void StartDMACH5(void)
786 {
787 EALLOW;
788 DmaRegs.CH5.CONTROL.bit.RUN = 1;
789 EDIS;
790 }
791
792 //
793 // DMACH6AddrConfig - DMA Channel 6 address configuration
794 //
DMACH6AddrConfig(volatile Uint16 * DMA_Dest,volatile Uint16 * DMA_Source)795 void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
796 {
797 EALLOW;
798
799 //
800 // Set up SOURCE address:
801 //
802 DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
803 // of source buffer.
804 DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
805
806 //
807 // Set up DESTINATION address:
808 //
809 DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
810 // of destination
811 // buffer.
812 DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
813
814 EDIS;
815 }
816
817 //
818 // DMACH6BurstConfig - DMA Channel 6 burst size configuration
819 //
DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep,int16 desbstep)820 void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep)
821 {
822 EALLOW;
823
824 //
825 // Set up BURST registers:
826 //
827 DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in
828 // a burst.
829 DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between
830 // each word x-ferred.
831 DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each
832 // word x-ferred.
833
834 EDIS;
835 }
836
837 //
838 // DMACH6TransferConfig - DMA channel 6 transfer size configuration
839 //
DMACH6TransferConfig(Uint16 tsize,int16 srctstep,int16 deststep)840 void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
841 {
842 EALLOW;
843
844 //
845 // Set up TRANSFER registers:
846 //
847 DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer,
848 // DMA interrupt will occur after
849 // completed transfer.
850 DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when
851 // WRAP occurs.
852 DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when
853 // WRAP occurs.
854
855 EDIS;
856 }
857
858 //
859 // DMACH6WrapConfig - DMA Channel 6 wrap size configuration
860 //
DMACH6WrapConfig(Uint16 srcwsize,int16 srcwstep,Uint16 deswsize,int16 deswstep)861 void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
862 int16 deswstep)
863 {
864 EALLOW;
865
866 //
867 // Set up WRAP registers:
868 //
869 DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
870 DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap
871
872 DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N
873 // bursts.
874 DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap
875
876 EDIS;
877 }
878
879 //
880 // DMACH6ModeConfig - DMA Channel 6 mode configuration
881 //
DMACH6ModeConfig(Uint16 persel,Uint16 perinte,Uint16 oneshot,Uint16 cont,Uint16 synce,Uint16 syncsel,Uint16 ovrinte,Uint16 datasize,Uint16 chintmode,Uint16 chinte)882 void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
883 Uint16 cont, Uint16 synce, Uint16 syncsel,
884 Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
885 Uint16 chinte)
886 {
887 EALLOW;
888
889 //
890 // Set up MODE Register:
891 // persel - Source select
892 // PERINTSEL - Should be hard coded to channel, above now selects source
893 // PERINTE - Peripheral interrupt enable
894 // ONESHOT - Oneshot enable
895 // CONTINUOUS - Continuous enable
896 // OVRINTE - Enable/disable the overflow interrupt
897 // DATASIZE - 16-bit/32-bit data size transfers
898 // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer
899 // CHINTE - Channel Interrupt to CPU enable
900 //
901 DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel;
902 DmaRegs.CH6.MODE.bit.PERINTSEL = 6;
903 DmaRegs.CH6.MODE.bit.PERINTE = perinte;
904 DmaRegs.CH6.MODE.bit.ONESHOT = oneshot;
905 DmaRegs.CH6.MODE.bit.CONTINUOUS = cont;
906 DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte;
907 DmaRegs.CH6.MODE.bit.DATASIZE = datasize;
908 DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode;
909 DmaRegs.CH6.MODE.bit.CHINTE = chinte;
910
911 //
912 // Clear any spurious flags: Interrupt flags and sync error flags
913 //
914 DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1;
915 DmaRegs.CH6.CONTROL.bit.ERRCLR = 1;
916
917 //
918 // Initialize PIE vector for CPU interrupt:
919 // Enable DMA CH6 interrupt in PIE
920 //
921 PieCtrlRegs.PIEIER7.bit.INTx6 = 1;
922
923 EDIS;
924 }
925
926 //
927 // StartDMACH6 - This function starts DMA Channel 6.
928 //
StartDMACH6(void)929 void StartDMACH6(void)
930 {
931 EALLOW;
932 DmaRegs.CH6.CONTROL.bit.RUN = 1;
933 EDIS;
934 }
935
936 //
937 // NOTE:
938 // Following functions are required for EMIF as the address is out of
939 // 22bit range
940 //
941
942 //
943 // DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit
944 //
DMACH1AddrConfig32bit(volatile Uint32 * DMA_Dest,volatile Uint32 * DMA_Source)945 void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest,
946 volatile Uint32 *DMA_Source)
947 {
948 EALLOW;
949
950 //
951 // Set up SOURCE address:
952 //
953 DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
954 // of source buffer
955 DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
956
957 //
958 // Set up DESTINATION address:
959 //
960 DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
961 // of destination
962 // buffer
963 DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
964
965 EDIS;
966 }
967
968 //
969 // DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit
970 //
DMACH2AddrConfig32bit(volatile Uint32 * DMA_Dest,volatile Uint32 * DMA_Source)971 void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest,
972 volatile Uint32 *DMA_Source)
973 {
974 EALLOW;
975
976 //
977 // Set up SOURCE address:
978 //
979 DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
980 // of source buffer
981 DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
982
983 //
984 // Set up DESTINATION address:
985 //
986 DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
987 // of destination
988 // buffer
989 DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
990
991 EDIS;
992 }
993
994 //
995 // DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit
996 //
DMACH3AddrConfig32bit(volatile Uint32 * DMA_Dest,volatile Uint32 * DMA_Source)997 void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest,
998 volatile Uint32 *DMA_Source)
999 {
1000 EALLOW;
1001
1002 //
1003 // Set up SOURCE address:
1004 //
1005 DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
1006 // of source buffer
1007 DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
1008
1009 //
1010 // Set up DESTINATION address:
1011 //
1012 DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
1013 // of destination
1014 // buffer.
1015 DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
1016
1017 EDIS;
1018 }
1019
1020 //
1021 // DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit
1022 //
DMACH4AddrConfig32bit(volatile Uint32 * DMA_Dest,volatile Uint32 * DMA_Source)1023 void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest,
1024 volatile Uint32 *DMA_Source)
1025 {
1026 EALLOW;
1027
1028 //
1029 // Set up SOURCE address:
1030 //
1031 DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
1032 // of source buffer
1033 DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
1034
1035 //
1036 // Set up DESTINATION address:
1037 //
1038 DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
1039 // of destination
1040 // buffer
1041 DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
1042
1043 EDIS;
1044 }
1045
1046 //
1047 // DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit
1048 //
DMACH5AddrConfig32bit(volatile Uint32 * DMA_Dest,volatile Uint32 * DMA_Source)1049 void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest,
1050 volatile Uint32 *DMA_Source)
1051 {
1052 EALLOW;
1053
1054 //
1055 // Set up SOURCE address:
1056 //
1057 DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
1058 // of source buffer
1059 DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
1060
1061 //
1062 // Set up DESTINATION address:
1063 //
1064 DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
1065 // of destination
1066 // buffer
1067 DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
1068
1069 EDIS;
1070 }
1071
1072 //
1073 // DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit
1074 //
DMACH6AddrConfig32bit(volatile Uint32 * DMA_Dest,volatile Uint32 * DMA_Source)1075 void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest,
1076 volatile Uint32 *DMA_Source)
1077 {
1078 EALLOW;
1079
1080 //
1081 // Set up SOURCE address:
1082 //
1083 DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning
1084 // of source buffer
1085 DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
1086
1087 //
1088 // Set up DESTINATION address:
1089 //
1090 DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning
1091 // of destination
1092 // buffer
1093 DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
1094
1095 EDIS;
1096 }
1097
1098 //
1099 // End of file
1100 //
1101