1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_dma.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_DMA_H 22 #define __REG_DMA_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 //////////////////////////////////////////////////////////////////////////////// 45 /// @brief DMA Base Address Definition 46 //////////////////////////////////////////////////////////////////////////////// 47 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) ///< Base Address: 0x40020000 48 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) ///< Base Address: 0x40020008 49 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) ///< Base Address: 0x4002001C 50 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) ///< Base Address: 0x40020030 51 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) ///< Base Address: 0x40020044 52 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) ///< Base Address: 0x40020058 53 54 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) ///< Base Address: 0x4002006C 55 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) ///< Base Address: 0x40020080 56 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) ///< Base Address: 0x40020400 57 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) ///< Base Address: 0x40020408 58 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) ///< Base Address: 0x4002041C 59 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) ///< Base Address: 0x40020430 60 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) ///< Base Address: 0x40020444 61 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) ///< Base Address: 0x40020458 62 63 //////////////////////////////////////////////////////////////////////////////// 64 /// @brief DMA Register Structure Definition 65 //////////////////////////////////////////////////////////////////////////////// 66 typedef struct { 67 __IO u32 CCR; ///< DMA channel x configuration register offset: 0x00 68 __IO u32 CNDTR; ///< DMA channel x number of data register offset: 0x04 69 __IO u32 CPAR; ///< DMA channel x peripheral address register offset: 0x08 70 __IO u32 CMAR; ///< DMA channel x memory address register offset: 0x0C 71 } DMA_Channel_TypeDef; 72 73 typedef struct { 74 __IO u32 ISR; ///< Interrupt Status Register offset: 0x00 75 __IO u32 IFCR; ///< Interrupt Flag Clear Register offset: 0x04 76 __IO u32 CCRx; ///< Channel X configures registers offset: 0x08 77 __IO u32 CNDTRx; ///< Channel X transfer quantity register offset: 0x0C 78 __IO u32 CPARx; ///< Channel X peripheral address register offset: 0x10 79 __IO u32 CMARx; ///< Channel X memory address register offset: 0x14 80 } DMA_TypeDef; 81 82 83 84 //////////////////////////////////////////////////////////////////////////////// 85 /// @brief DMA type pointer Definition 86 //////////////////////////////////////////////////////////////////////////////// 87 #define DMA1 ((DMA_TypeDef*) DMA1_BASE) 88 #define DMA1_ch1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE) 89 #define DMA1_ch2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE) 90 #define DMA1_ch3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE) 91 #define DMA1_ch4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE) 92 #define DMA1_ch5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE) 93 94 #define DMA1_Channel1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE) 95 #define DMA1_Channel2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE) 96 #define DMA1_Channel3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE) 97 #define DMA1_Channel4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE) 98 #define DMA1_Channel5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE) 99 100 101 #define DMA1_ch6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE) 102 #define DMA1_ch7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE) 103 104 #define DMA1_Channel6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE) 105 #define DMA1_Channel7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE) 106 107 #define DMA2 ((DMA_TypeDef*) DMA2_BASE) 108 #define DMA2_ch1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE) 109 #define DMA2_ch2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE) 110 #define DMA2_ch3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE) 111 #define DMA2_ch4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE) 112 #define DMA2_ch5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE) 113 #define DMA2_Channel1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE) 114 #define DMA2_Channel2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE) 115 #define DMA2_Channel3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE) 116 #define DMA2_Channel4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE) 117 #define DMA2_Channel5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE) 118 119 120 //////////////////////////////////////////////////////////////////////////////// 121 /// @brief DMA_ISR Register Bit Definition 122 //////////////////////////////////////////////////////////////////////////////// 123 #define DMA_ISR_GIF1_Pos (0) 124 #define DMA_ISR_GIF1 (0x01U << DMA_ISR_GIF1_Pos) ///< Channel 1 Global interrupt flag 125 #define DMA_ISR_TCIF1_Pos (1) 126 #define DMA_ISR_TCIF1 (0x01U << DMA_ISR_TCIF1_Pos) ///< Channel 1 Transfer Complete flag 127 #define DMA_ISR_HTIF1_Pos (2) 128 #define DMA_ISR_HTIF1 (0x01U << DMA_ISR_HTIF1_Pos) ///< Channel 1 Half Transfer flag 129 #define DMA_ISR_TEIF1_Pos (3) 130 #define DMA_ISR_TEIF1 (0x01U << DMA_ISR_TEIF1_Pos) ///< Channel 1 Transfer Error flag 131 #define DMA_ISR_GIF2_Pos (4) 132 #define DMA_ISR_GIF2 (0x01U << DMA_ISR_GIF2_Pos) ///< Channel 2 Global interrupt flag 133 #define DMA_ISR_TCIF2_Pos (5) 134 #define DMA_ISR_TCIF2 (0x01U << DMA_ISR_TCIF2_Pos) ///< Channel 2 Transfer Complete flag 135 #define DMA_ISR_HTIF2_Pos (6) 136 #define DMA_ISR_HTIF2 (0x01U << DMA_ISR_HTIF2_Pos) ///< Channel 2 Half Transfer flag 137 #define DMA_ISR_TEIF2_Pos (7) 138 #define DMA_ISR_TEIF2 (0x01U << DMA_ISR_TEIF2_Pos) ///< Channel 2 Transfer Error flag 139 #define DMA_ISR_GIF3_Pos (8) 140 #define DMA_ISR_GIF3 (0x01U << DMA_ISR_GIF3_Pos) ///< Channel 3 Global interrupt flag 141 #define DMA_ISR_TCIF3_Pos (9) 142 #define DMA_ISR_TCIF3 (0x01U << DMA_ISR_TCIF3_Pos) ///< Channel 3 Transfer Complete flag 143 #define DMA_ISR_HTIF3_Pos (10) 144 #define DMA_ISR_HTIF3 (0x01U << DMA_ISR_HTIF3_Pos) ///< Channel 3 Half Transfer flag 145 #define DMA_ISR_TEIF3_Pos (11) 146 #define DMA_ISR_TEIF3 (0x01U << DMA_ISR_TEIF3_Pos) ///< Channel 3 Transfer Error flag 147 #define DMA_ISR_GIF4_Pos (12) 148 #define DMA_ISR_GIF4 (0x01U << DMA_ISR_GIF4_Pos) ///< Channel 4 Global interrupt flag 149 #define DMA_ISR_TCIF4_Pos (13) 150 #define DMA_ISR_TCIF4 (0x01U << DMA_ISR_TCIF4_Pos) ///< Channel 4 Transfer Complete flag 151 #define DMA_ISR_HTIF4_Pos (14) 152 #define DMA_ISR_HTIF4 (0x01U << DMA_ISR_HTIF4_Pos) ///< Channel 4 Half Transfer flag 153 #define DMA_ISR_TEIF4_Pos (15) 154 #define DMA_ISR_TEIF4 (0x01U << DMA_ISR_TEIF4_Pos) ///< Channel 4 Transfer Error flag 155 #define DMA_ISR_GIF5_Pos (16) 156 #define DMA_ISR_GIF5 (0x01U << DMA_ISR_GIF5_Pos) ///< Channel 5 Global interrupt flag 157 #define DMA_ISR_TCIF5_Pos (17) 158 #define DMA_ISR_TCIF5 (0x01U << DMA_ISR_TCIF5_Pos) ///< Channel 5 Transfer Complete flag 159 #define DMA_ISR_HTIF5_Pos (18) 160 #define DMA_ISR_HTIF5 (0x01U << DMA_ISR_HTIF5_Pos) ///< Channel 5 Half Transfer flag 161 #define DMA_ISR_TEIF5_Pos (19) 162 #define DMA_ISR_TEIF5 (0x01U << DMA_ISR_TEIF5_Pos) ///< Channel 5 Transfer Error flag 163 164 #define DMA_ISR_GIF6_Pos (20) 165 #define DMA_ISR_GIF6 (0x01U << DMA_ISR_GIF6_Pos) ///< Channel 6 Global interrupt flag 166 #define DMA_ISR_TCIF6_Pos (21) 167 #define DMA_ISR_TCIF6 (0x01U << DMA_ISR_TCIF6_Pos) ///< Channel 6 Transfer Complete flag 168 #define DMA_ISR_HTIF6_Pos (22) 169 #define DMA_ISR_HTIF6 (0x01U << DMA_ISR_HTIF6_Pos) ///< Channel 6 Half Transfer flag 170 #define DMA_ISR_TEIF6_Pos (23) 171 #define DMA_ISR_TEIF6 (0x01U << DMA_ISR_TEIF6_Pos) ///< Channel 6 Transfer Error flag 172 #define DMA_ISR_GIF7_Pos (24) 173 #define DMA_ISR_GIF7 (0x01U << DMA_ISR_GIF7_Pos) ///< Channel 7 Global interrupt flag 174 #define DMA_ISR_TCIF7_Pos (25) 175 #define DMA_ISR_TCIF7 (0x01U << DMA_ISR_TCIF7_Pos) ///< Channel 7 Transfer Complete flag 176 #define DMA_ISR_HTIF7_Pos (26) 177 #define DMA_ISR_HTIF7 (0x01U << DMA_ISR_HTIF7_Pos) ///< Channel 7 Half Transfer flag 178 #define DMA_ISR_TEIF7_Pos (27) 179 #define DMA_ISR_TEIF7 (0x01U << DMA_ISR_TEIF7_Pos) ///< Channel 7 Transfer Error flag 180 181 //////////////////////////////////////////////////////////////////////////////// 182 /// @brief DMA_IFCR Register Bit Definition 183 //////////////////////////////////////////////////////////////////////////////// 184 #define DMA_IFCR_CGIF1_Pos (0) 185 #define DMA_IFCR_CGIF1 (0x01U << DMA_IFCR_CGIF1_Pos) ///< Channel 1 Global interrupt clearr 186 #define DMA_IFCR_CTCIF1_Pos (1) 187 #define DMA_IFCR_CTCIF1 (0x01U << DMA_IFCR_CTCIF1_Pos) ///< Channel 1 Transfer Complete clear 188 #define DMA_IFCR_CHTIF1_Pos (2) 189 #define DMA_IFCR_CHTIF1 (0x01U << DMA_IFCR_CHTIF1_Pos) ///< Channel 1 Half Transfer clear 190 #define DMA_IFCR_CTEIF1_Pos (3) 191 #define DMA_IFCR_CTEIF1 (0x01U << DMA_IFCR_CTEIF1_Pos) ///< Channel 1 Transfer Error clear 192 #define DMA_IFCR_CGIF2_Pos (4) 193 #define DMA_IFCR_CGIF2 (0x01U << DMA_IFCR_CGIF2_Pos) ///< Channel 2 Global interrupt clear 194 #define DMA_IFCR_CTCIF2_Pos (5) 195 #define DMA_IFCR_CTCIF2 (0x01U << DMA_IFCR_CTCIF2_Pos) ///< Channel 2 Transfer Complete clear 196 #define DMA_IFCR_CHTIF2_Pos (6) 197 #define DMA_IFCR_CHTIF2 (0x01U << DMA_IFCR_CHTIF2_Pos) ///< Channel 2 Half Transfer clear 198 #define DMA_IFCR_CTEIF2_Pos (7) 199 #define DMA_IFCR_CTEIF2 (0x01U << DMA_IFCR_CTEIF2_Pos) ///< Channel 2 Transfer Error clear 200 #define DMA_IFCR_CGIF3_Pos (8) 201 #define DMA_IFCR_CGIF3 (0x01U << DMA_IFCR_CGIF3_Pos) ///< Channel 3 Global interrupt clear 202 #define DMA_IFCR_CTCIF3_Pos (9) 203 #define DMA_IFCR_CTCIF3 (0x01U << DMA_IFCR_CTCIF3_Pos) ///< Channel 3 Transfer Complete clear 204 #define DMA_IFCR_CHTIF3_Pos (10) 205 #define DMA_IFCR_CHTIF3 (0x01U << DMA_IFCR_CHTIF3_Pos) ///< Channel 3 Half Transfer clear 206 #define DMA_IFCR_CTEIF3_Pos (11) 207 #define DMA_IFCR_CTEIF3 (0x01U << DMA_IFCR_CTEIF3_Pos) ///< Channel 3 Transfer Error clear 208 #define DMA_IFCR_CGIF4_Pos (12) 209 #define DMA_IFCR_CGIF4 (0x01U << DMA_IFCR_CGIF4_Pos) ///< Channel 4 Global interrupt clear 210 #define DMA_IFCR_CTCIF4_Pos (13) 211 #define DMA_IFCR_CTCIF4 (0x01U << DMA_IFCR_CTCIF4_Pos) ///< Channel 4 Transfer Complete clear 212 #define DMA_IFCR_CHTIF4_Pos (14) 213 #define DMA_IFCR_CHTIF4 (0x01U << DMA_IFCR_CHTIF4_Pos) ///< Channel 4 Half Transfer clear 214 #define DMA_IFCR_CTEIF4_Pos (15) 215 #define DMA_IFCR_CTEIF4 (0x01U << DMA_IFCR_CTEIF4_Pos) ///< Channel 4 Transfer Error clear 216 #define DMA_IFCR_CGIF5_Pos (16) 217 #define DMA_IFCR_CGIF5 (0x01U << DMA_IFCR_CGIF5_Pos) ///< Channel 5 Global interrupt clear 218 #define DMA_IFCR_CTCIF5_Pos (17) 219 #define DMA_IFCR_CTCIF5 (0x01U << DMA_IFCR_CTCIF5_Pos) ///< Channel 5 Transfer Complete clear 220 #define DMA_IFCR_CHTIF5_Pos (18) 221 #define DMA_IFCR_CHTIF5 (0x01U << DMA_IFCR_CHTIF5_Pos) ///< Channel 5 Half Transfer clear 222 #define DMA_IFCR_CTEIF5_Pos (19) 223 #define DMA_IFCR_CTEIF5 (0x01U << DMA_IFCR_CTEIF5_Pos) ///< Channel 5 Transfer Error clear 224 225 #define DMA_IFCR_CGIF6_Pos (20) 226 #define DMA_IFCR_CGIF6 (0x01U << DMA_IFCR_CGIF6_Pos) ///< Channel 6 Global interrupt clear 227 #define DMA_IFCR_CTCIF6_Pos (21) 228 #define DMA_IFCR_CTCIF6 (0x01U << DMA_IFCR_CTCIF6_Pos) ///< Channel 6 Transfer Complete clear 229 #define DMA_IFCR_CHTIF6_Pos (22) 230 #define DMA_IFCR_CHTIF6 (0x01U << DMA_IFCR_CHTIF6_Pos) ///< Channel 6 Half Transfer clear 231 #define DMA_IFCR_CTEIF6_Pos (23) 232 #define DMA_IFCR_CTEIF6 (0x01U << DMA_IFCR_CTEIF6_Pos) ///< Channel 6 Transfer Error clear 233 #define DMA_IFCR_CGIF7_Pos (24) 234 #define DMA_IFCR_CGIF7 (0x01U << DMA_IFCR_CGIF7_Pos) ///< Channel 7 Global interrupt clear 235 #define DMA_IFCR_CTCIF7_Pos (25) 236 #define DMA_IFCR_CTCIF7 (0x01U << DMA_IFCR_CTCIF7_Pos) ///< Channel 7 Transfer Complete clear 237 #define DMA_IFCR_CHTIF7_Pos (26) 238 #define DMA_IFCR_CHTIF7 (0x01U << DMA_IFCR_CHTIF7_Pos) ///< Channel 7 Half Transfer clear 239 #define DMA_IFCR_CTEIF7_Pos (27) 240 #define DMA_IFCR_CTEIF7 (0x01U << DMA_IFCR_CTEIF7_Pos) ///< Channel 7 Transfer Error clear 241 242 //////////////////////////////////////////////////////////////////////////////// 243 /// @brief DMA_CCR Register Bit Definition 244 //////////////////////////////////////////////////////////////////////////////// 245 #define DMA_CCR_EN_Pos (0) 246 #define DMA_CCR_EN (0x01U << DMA_CCR_EN_Pos) ///< Channel enabl 247 #define DMA_CCR_TCIE_Pos (1) 248 #define DMA_CCR_TCIE (0x01U << DMA_CCR_TCIE_Pos) ///< Transfer complete interrupt enable 249 #define DMA_CCR_HTIE_Pos (2) 250 #define DMA_CCR_HTIE (0x01U << DMA_CCR_HTIE_Pos) ///< Half Transfer interrupt enable 251 #define DMA_CCR_TEIE_Pos (3) 252 #define DMA_CCR_TEIE (0x01U << DMA_CCR_TEIE_Pos) ///< Transfer error interrupt enable 253 #define DMA_CCR_DIR_Pos (4) 254 #define DMA_CCR_DIR (0x01U << DMA_CCR_DIR_Pos) ///< Data transfer direction 255 #define DMA_CCR_CIRC_Pos (5) 256 #define DMA_CCR_CIRC (0x01U << DMA_CCR_CIRC_Pos) ///< Circular mode 257 #define DMA_CCR_PINC_Pos (6) 258 #define DMA_CCR_PINC (0x01U << DMA_CCR_PINC_Pos) ///< Peripheral increment mode 259 #define DMA_CCR_MINC_Pos (7) 260 #define DMA_CCR_MINC (0x01U << DMA_CCR_MINC_Pos) ///< Memory increment mode 261 262 #define DMA_CCR_PSIZE_Pos (8) 263 #define DMA_CCR_PSIZE (0x03U << DMA_CCR_PSIZE_Pos) ///< PSIZE[1:0] bits (Peripheral size) 264 #define DMA_CCR_PSIZE_0 (0x01U << DMA_CCR_PSIZE_Pos) ///< Bit0 265 #define DMA_CCR_PSIZE_1 (0x02U << DMA_CCR_PSIZE_Pos) ///< Bit1 266 267 #define DMA_CCR_PSIZE_BYTE (0x00U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Byte 268 #define DMA_CCR_PSIZE_HALFWORD (0x01U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size HalfWord 269 #define DMA_CCR_PSIZE_WORD (0x02U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Word 270 271 #define DMA_CCR_MSIZE_Pos (10) 272 #define DMA_CCR_MSIZE (0x03U << DMA_CCR_MSIZE_Pos) ///< MSIZE[1:0] bits (Memory size) 273 #define DMA_CCR_MSIZE_0 (0x01U << DMA_CCR_MSIZE_Pos) ///< Bit0 274 #define DMA_CCR_MSIZE_1 (0x02U << DMA_CCR_MSIZE_Pos) ///< Bit1 275 276 #define DMA_CCR_MSIZE_BYTE (0x00U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Byte 277 #define DMA_CCR_MSIZE_HALFWORD (0x01U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size HalfWord 278 #define DMA_CCR_MSIZE_WORD (0x02U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Word 279 280 #define DMA_CCR_PL_Pos (12) 281 #define DMA_CCR_PL (0x03U << DMA_CCR_PL_Pos) ///< PL[1:0] bits(Channel Priority level) 282 #define DMA_CCR_PL_0 (0x01U << DMA_CCR_PL_Pos) ///< Bit0 283 #define DMA_CCR_PL_1 (0x02U << DMA_CCR_PL_Pos) ///< Bit1 284 285 #define DMA_CCR_PL_Low (0x00U << DMA_CCR_PL_Pos) ///< DMA Priority Low 286 #define DMA_CCR_PL_Medium (0x01U << DMA_CCR_PL_Pos) ///< DMA Priority Medium 287 #define DMA_CCR_PL_High (0x02U << DMA_CCR_PL_Pos) ///< DMA Priority High 288 #define DMA_CCR_PL_VeryHigh (0x03U << DMA_CCR_PL_Pos) ///< DMA Priority VeryHigh 289 #define DMA_CCR_M2M_Pos (14) 290 #define DMA_CCR_M2M (0x01U << DMA_CCR_M2M_Pos) ///< Memory to memory mode 291 292 #define DMA_CCR_ARE_Pos (15) 293 #define DMA_CCR_ARE (0x01U << DMA_CCR_ARE_Pos) ///< Auto-Reload Enable bit 294 295 //////////////////////////////////////////////////////////////////////////////// 296 /// @brief DMA_CNDTR Register Bit Definition 297 //////////////////////////////////////////////////////////////////////////////// 298 #define DMA_CNDTR_NDT_Pos (0) 299 #define DMA_CNDTR_NDT (0xFFFFU << DMA_CNDTR_NDT_Pos) ///< Number of data to Transfer 300 301 //////////////////////////////////////////////////////////////////////////////// 302 /// @brief DMA_CPAR Register Bit Definition 303 //////////////////////////////////////////////////////////////////////////////// 304 #define DMA_CPAR_PA_Pos (0) 305 #define DMA_CPAR_PA (0xFFFFFFFFU << DMA_CPAR_PA_Pos) ///< Peripheral Address 306 307 //////////////////////////////////////////////////////////////////////////////// 308 /// @brief DMA_CMAR Register Bit Definition 309 //////////////////////////////////////////////////////////////////////////////// 310 #define DMA_CMAR_MA_Pos (0) 311 #define DMA_CMAR_MA (0xFFFFFFFFU << DMA_CMAR_MA_Pos) ///< Peripheral Address 312 313 314 315 316 317 /// @} 318 319 /// @} 320 321 /// @} 322 323 //////////////////////////////////////////////////////////////////////////////// 324 #endif 325 //////////////////////////////////////////////////////////////////////////////// 326