1 /* 2 * Copyright (c) 2022 OpenLuat & AirM2M 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy of 5 * this software and associated documentation files (the "Software"), to deal in 6 * the Software without restriction, including without limitation the rights to 7 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 8 * the Software, and to permit persons to whom the Software is furnished to do so, 9 * subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in all 12 * copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 16 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 17 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 18 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22 23 #ifndef __AIR105_DMA_H 24 #define __AIR105_DMA_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "air105.h" 32 33 typedef struct 34 { 35 uint32_t DMA_Peripheral; 36 37 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ 38 39 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ 40 41 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. 42 This parameter can be a value of @ref DMA_data_transfer_direction */ 43 44 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. 45 This parameter can be a value of @ref DMA_incremented_mode */ 46 47 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. 48 This parameter can be a value of @ref DMA_incremented_mode */ 49 50 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data item width. 51 This parameter can be a value of @ref DMA_data_size */ 52 53 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data item width. 54 This parameter can be a value of @ref DMA_data_size */ 55 56 uint32_t DMA_PeripheralBurstSize; /*!< Specifies the Peripheral Number of data items during per burst transaction. 57 read or write from the Peripheral every time a burst transaction request 58 This parameter can be a value of @ref DMA_burst_size */ 59 60 uint32_t DMA_MemoryBurstSize; /*!< Specifies the Memory Number of data items during per burst transaction. 61 read or write from the Memory every time a burst transaction request 62 This parameter can be a value of @ref DMA_burst_size */ 63 64 uint32_t DMA_PeripheralHandShake; /*!< Specifies the HandShake to control the DMA transacation. 65 This parameter can be a value of @ref DMA_peripheral_handshake */ 66 67 uint32_t DMA_BlockSize; /*!< Specifies the Total Number of data items during the transaction. */ 68 69 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. 70 This parameter can be a value of @ref DMA_priority_level */ 71 }DMA_InitTypeDef; 72 73 /** 74 * DMA多块传输内存表 75 * 76 */ 77 typedef struct _lli 78 { 79 uint32_t SAR; 80 uint32_t DAR; 81 uint32_t LLP; 82 uint32_t CTL_L; 83 uint32_t CTL_H; 84 uint32_t DSTAT; 85 }LLI; 86 87 /**多块传输模式 88 * @} 89 */ 90 #define Multi_Block_MODE01 (uint8_t)0x00 /*Single-block or last transfer of multi-block*/ 91 #define Multi_Block_MODE02 (uint8_t)0x01 /*Auto-reload multi-block transfer with contiguous SAR*/ 92 #define Multi_Block_MODE03 (uint8_t)0x02 /*Auto-reload multi-block transfer with contiguous DAR*/ 93 #define Multi_Block_MODE04 (uint8_t)0x03 /*Auto-reload multi-block transfer*/ 94 #define Multi_Block_MODE05 (uint8_t)0x04 /*Single-block or last transfer of multi-block*/ 95 #define Multi_Block_MODE06 (uint8_t)0x05 /*Linked list multi-block transfer with contiguous SAR*/ 96 #define Multi_Block_MODE07 (uint8_t)0x06 /*Linked list multi-block transfer with auto-reload SAR*/ 97 #define Multi_Block_MODE08 (uint8_t)0x07 /*Linked list multi-block transfer with contiguous DAR*/ 98 #define Multi_Block_MODE09 (uint8_t)0x08 /*Linked list multi-block transfer with auto-reload DAR*/ 99 #define Multi_Block_MODE10 (uint8_t)0x09 /*Linked list multi-block transfer*/ 100 101 /** @defgroup DMA_data_transfer_direction 102 * @{ 103 */ 104 105 #define DMA_DIR_Memory_To_Memory ((uint32_t)0x0000) 106 #define DMA_DIR_Memory_To_Peripheral ((uint32_t)0x0001) 107 #define DMA_DIR_Peripheral_To_Memory ((uint32_t)0x0002) 108 109 /** 110 * @} 111 */ 112 113 /** @defgroup DMA_incremented_mode 114 * @{ 115 */ 116 117 #define DMA_Inc_Increment ((uint32_t)0x00000000) 118 #define DMA_Inc_Decrement ((uint32_t)0x00000001) 119 #define DMA_Inc_Nochange ((uint32_t)0x00000002) 120 #define IS_DMA_INC_STATE(STATE) (((STATE) == DMA_Inc_Increment) || \ 121 ((STATE) == DMA_Inc_Decrement) || \ 122 ((STATE) == DMA_Inc_Nochange)) 123 /** 124 * @} 125 */ 126 127 /** @defgroup DMA_data_size 128 * @{ 129 */ 130 131 #define DMA_DataSize_Byte ((uint32_t)0x0000) 132 #define DMA_DataSize_HalfWord ((uint32_t)0x0001) 133 #define DMA_DataSize_Word ((uint32_t)0x0002) 134 #define IS_DMA_DATA_SIZE(SIZE) (((SIZE) == DMA_DataSize_Byte) || \ 135 ((SIZE) == DMA_DataSize_HalfWord) || \ 136 ((SIZE) == DMA_DataSize_Word)) 137 /** 138 * @} 139 */ 140 141 /** @defgroup DMA_burst_size 142 * @{ 143 */ 144 #define DMA_BurstSize_1 ((uint32_t)0x00) 145 #define DMA_BurstSize_4 ((uint32_t)0x01) 146 #define DMA_BurstSize_8 ((uint32_t)0x02) 147 #define DMA_BurstSize_16 ((uint32_t)0x03) 148 #define DMA_BurstSize_32 ((uint32_t)0x04) 149 /** 150 * @} 151 */ 152 153 /** @defgroup DMA_peripheral_handshake 154 * @{ 155 */ 156 #define DMA_PeripheralHandShake_Hardware ((uint32_t)0x0000) 157 #define DMA_PeripheralHandShake_Software ((uint32_t)0x0001) 158 /** 159 * @} 160 */ 161 162 /** @defgroup DMA_Priority 163 * @{ 164 */ 165 #define DMA_Priority_0 ((uint32_t)0x00000000) 166 #define DMA_Priority_1 ((uint32_t)0x00000020) 167 #define DMA_Priority_2 ((uint32_t)0x00000040) 168 #define DMA_Priority_3 ((uint32_t)0x00000060) 169 #define DMA_Priority_4 ((uint32_t)0x00000080) 170 #define DMA_Priority_5 ((uint32_t)0x000000A0) 171 #define DMA_Priority_6 ((uint32_t)0x000000C0) 172 173 /** 174 * @} 175 */ 176 177 /** @defgroup DMA_IT 178 * @{ 179 */ 180 #define DMA_IT_BlockTransferComplete ((uint32_t)0x01) 181 #define DMA_IT_DestinationTransactionComplete ((uint32_t)0x02) 182 #define DMA_IT_Error ((uint32_t)0x04) 183 #define DMA_IT_SourceTransactionComplete ((uint32_t)0x08) 184 #define DMA_IT_DMATransferComplete ((uint32_t)0x10) 185 /** 186 * @} 187 */ 188 189 void DMA_Init(DMA_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct); 190 void DMA_ChannelCmd(DMA_TypeDef* DMA_Channelx, FunctionalState NewState); 191 void DMA_Cmd(FunctionalState NewState); 192 void DMA_ChannelConfig(DMA_TypeDef* DMA_Channelx, uint32_t DMA_Peripheral, uint32_t DMA_DIR); 193 void DMA_SetSRCAddress(DMA_TypeDef* DMA_Channelx, uint32_t Address); 194 void DMA_SetDSRAddress(DMA_TypeDef* DMA_Channelx, uint32_t Address); 195 196 void DMA_ITConfig(DMA_TypeDef* DMA_Channelx, uint32_t DMA_IT, FunctionalState NewState); 197 198 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); 199 void DMA_ClearFlag(uint32_t DMA_FLAG); 200 201 FunctionalState DMA_IsChannelEnabled(DMA_TypeDef* DMA_Channelx); 202 203 ITStatus DMA_GetITStatus(DMA_TypeDef* DMA_Channelx,uint32_t DMA_IT); 204 FlagStatus DMA_GetRawStatus(DMA_TypeDef* DMA_Channelx,uint32_t DMA_IT); 205 void DMA_ClearITPendingBit(DMA_TypeDef* DMA_Channelx,uint32_t DMA_IT); 206 207 void DMA_MultiBlockInit(DMA_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct ,\ 208 LLI *first_lli,uint8_t Multi_Block_Mode); 209 void DMA_InitLLI(DMA_TypeDef* DMA_Channelx,LLI *lli,LLI *next_lli, 210 void *src_addr,void *dest_addr,uint16_t btsize); 211 uint32_t DMA_GetTransferNum(DMA_TypeDef* DMA_Channelx, uint32_t first_adr); 212 213 #ifdef __cplusplus 214 } 215 #endif 216 217 #endif 218 219 /************************** (C) COPYRIGHT Megahunt *****END OF FILE****/ 220