1 /*
2  * Copyright 2021 MindMotion Microelectronics Co., Ltd.
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include "hal_dma.h"
9 
10 /* clear all the interrupt enables and disable the dma channel. */
DMA_InitChannel(DMA_Type * DMAx,uint32_t channel,DMA_Channel_Init_Type * init)11 uint32_t DMA_InitChannel(DMA_Type * DMAx, uint32_t channel, DMA_Channel_Init_Type * init)
12 {
13     uint32_t ccr = 0u;
14 
15     if (   (init->XferMode == DMA_XferMode_MemoryToPeriph)
16         || (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) )
17     {
18         ccr |= DMA_CCR_DIR_MASK;
19     }
20 
21     if (   (init->XferMode == DMA_XferMode_PeriphToMemoryBurst)
22         || (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) )
23     {
24         ccr |= DMA_CCR_MEM2MEM_MASK;
25     }
26 
27     if (init->ReloadMode == DMA_ReloadMode_AutoReload)
28     {
29         ccr |= DMA_CCR_ARE_MASK;
30     }
31     else if (init->ReloadMode == DMA_ReloadMode_AutoReloadContinuous)
32     {
33         ccr |= (DMA_CCR_ARE_MASK | DMA_CCR_CIRC_MASK);
34     }
35 
36     ccr |= DMA_CCR_PINC(init->PeriphAddrIncMode)
37          | DMA_CCR_MINC(init->MemAddrIncMode)
38          | DMA_CCR_PSIZE(init->XferWidth)
39          | DMA_CCR_MSIZE(init->XferWidth)
40          | DMA_CCR_PL(init->Priority)
41          ;
42 
43     DMAx->CH[channel].CCR = ccr;
44     DMAx->CH[channel].CNDTR = init->XferCount;
45     DMAx->CH[channel].CPAR = init->PeriphAddr;
46     DMAx->CH[channel].CMAR = init->MemAddr;
47 
48     return 0u;
49 }
50 
DMA_EnableChannelInterrupts(DMA_Type * DMAx,uint32_t channel,uint32_t interrupts,bool enable)51 void DMA_EnableChannelInterrupts(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts, bool enable)
52 {
53     if (enable)
54     {
55         DMAx->CH[channel].CCR |= (interrupts & 0xEu);
56     }
57     else
58     {
59         DMAx->CH[channel].CCR &= ~(interrupts & 0xEu);
60     }
61 }
62 
DMA_GetChannelInterruptStatus(DMA_Type * DMAx,uint32_t channel)63 uint32_t DMA_GetChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel)
64 {
65     return (DMAx->ISR >> (channel * 4u)) & 0xFu;
66 }
67 
DMA_ClearChannelInterruptStatus(DMA_Type * DMAx,uint32_t channel,uint32_t interrupts)68 void DMA_ClearChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts)
69 {
70     DMAx->IFCR = ( (interrupts & 0xFu) << (channel * 4u) );
71 }
72 
DMA_EnableChannel(DMA_Type * DMAx,uint32_t channel,bool enable)73 void DMA_EnableChannel(DMA_Type * DMAx, uint32_t channel, bool enable)
74 {
75     if (enable)
76     {
77         DMAx->CH[channel].CCR |= DMA_CCR_EN_MASK;
78     }
79     else
80     {
81         DMAx->CH[channel].CCR &= ~DMA_CCR_EN_MASK;
82     }
83 }
84 
85 /* EOF. */
86 
87