1 /** 2 ********************************************************************************* 3 * 4 * @file ald_dma.h 5 * @brief DMA module Library. 6 * 7 * @version V1.0 8 * @date 09 Nov 2019 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 09 Nov 2019 AE Team The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 #ifndef __ALD_DMA_H__ 34 #define __ALD_DMA_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include "utils.h" 41 42 43 /** @addtogroup ES32FXXX_ALD 44 * @{ 45 */ 46 47 /** @addtogroup DMA 48 * @{ 49 */ 50 51 /** 52 * @defgroup DMA_Public_Macros DMA Public Macros 53 * @{ 54 */ 55 #define DMA_CH_COUNT 12U 56 #define DMA_ERR 31U 57 /** 58 * @} 59 */ 60 61 /** 62 * @defgroup DMA_Public_Types DMA Public Types 63 * @{ 64 */ 65 66 /** 67 * @brief Input source to DMA channel 68 * @verbatim 69 In this module, for the convenience of code maintenance, 70 TIMERx is used to indicate the sequence of the timer peripheral. 71 Different product series TIMERx represent different meanings: 72 1. For ES32F36xx series: 73 TIMER0 ----> AD16C4T0 74 TIMER1 ----> AD16C4T1 75 TIMER2 ----> GP32C4T0 76 TIMER3 ----> GP32C4T1 77 TIMER4 ----> BS16T0 78 TIMER5 ----> BS16T1 79 TIMER6 ----> GP16C4T0 80 TIMER7 ----> GP16C4T1 81 82 2. For ES32F393x/ES32F336x/ES32F392x series: 83 TIMER0 ----> GP16C4T0 84 TIMER1 ----> GP16C4T1 85 TIMER2 ----> GP32C4T0 86 TIMER3 ----> GP32C4T1 87 TIMER4 ----> BS16T0 88 TIMER5 ----> BS16T1 89 TIMER6 ----> GP16C4T2 90 TIMER7 ----> GP16C4T3 91 @endverbatim 92 */ 93 typedef enum { 94 DMA_MSEL_NONE = 0x0U, /**< NONE */ 95 DMA_MSEL_GPIO = 0x1U, /**< GPIO */ 96 DMA_MSEL_CRYPT = 0x2U, /**< CRYPT */ 97 DMA_MSEL_DAC0 = 0x4U, /**< DAC0 */ 98 DMA_MSEL_ADC0 = 0x6U, /**< ADC0 */ 99 DMA_MSEL_CRC = 0x7U, /**< CRC */ 100 DMA_MSEL_UART0 = 0x8U, /**< UART0 */ 101 DMA_MSEL_UART1 = 0x9U, /**< UART1 */ 102 DMA_MSEL_UART2 = 0xAU, /**< UART2 */ 103 DMA_MSEL_UART3 = 0xBU, /**< UART3 */ 104 DMA_MSEL_UART4 = 0xCU, /**< UART4 */ 105 DMA_MSEL_UART5 = 0xDU, /**< UART5 */ 106 DMA_MSEL_SPI0 = 0xEU, /**< SPI0 */ 107 DMA_MSEL_SPI1 = 0xFU, /**< SPI1 */ 108 DMA_MSEL_I2C0 = 0x10U, /**< I2C0 */ 109 DMA_MSEL_I2C1 = 0x11U, /**< I2C1 */ 110 DMA_MSEL_TIMER0 = 0x12U, /**< TIMER0 */ 111 DMA_MSEL_TIMER1 = 0x13U, /**< TIMER1 */ 112 DMA_MSEL_TIMER2 = 0x14U, /**< TIMER2 */ 113 DMA_MSEL_TIMER3 = 0x15U, /**< TIMER3 */ 114 DMA_MSEL_LPUART0 = 0x18U, /**< LPUART0 */ 115 DMA_MSEL_SPI2 = 0x1AU, /**< SPI2 */ 116 DMA_MSEL_TIMER4 = 0x1BU, /**< TIMER4 */ 117 DMA_MSEL_TIMER5 = 0x1CU, /**< TIMER5 */ 118 DMA_MSEL_TIMER6 = 0x1DU, /**< TIMER6 */ 119 DMA_MSEL_TIMER7 = 0x1EU, /**< TIMER7 */ 120 DMA_MSEL_ADC1 = 0x1FU, /**< ADC1 */ 121 DMA_MSEL_PIS = 0x20U, /**< PIS */ 122 DMA_MSEL_TRNG = 0x21U, /**< TRNG */ 123 DMA_MSEL_QSPI = 0x22U, /**< QSPI */ 124 DMA_MSEL_USB = 0x23U, /**< USB */ 125 } dma_msel_t; 126 127 /** 128 * @brief Input signal to DMA channel 129 */ 130 typedef enum { 131 DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ 132 DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ 133 DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ 134 DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ 135 DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ 136 DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ 137 DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ 138 DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ 139 DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ 140 DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ 141 DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ 142 DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ 143 DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ 144 DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ 145 DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ 146 DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ 147 DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ 148 DMA_MSIGSEL_CRYPT_WRITE = 0x0U, /**< CRYPT write mode */ 149 DMA_MSIGSEL_CRYPT_READ = 0x1U, /**< CRYPT read mode */ 150 DMA_MSIGSEL_DAC0_CH0 = 0x0U, /**< DAC0 channel 0 complete */ 151 DMA_MSIGSEL_DAC0_CH1 = 0x1U, /**< DAC0 channel 1 complete */ 152 DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ 153 DMA_MSIGSEL_UART_TXEMPTY = 0x0U, /**< UART0/UART1/UART2/UART3 transmit */ 154 DMA_MSIGSEL_UART_RNR = 0x1U, /**< UART0/UART1/UART2/UART3 receive */ 155 DMA_MSIGSEL_UART45_RNR = 0x0U, /**< UART4/UART5 reveive */ 156 DMA_MSIGSEL_UART45_TXEMPTY = 0x1U, /**< UART4/UART5 transmit */ 157 DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ 158 DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ 159 DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ 160 DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ 161 DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ 162 DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ 163 DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ 164 DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ 165 DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ 166 DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ 167 DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ 168 DMA_MSIGSEL_LPUART_RNR = 0x0U, /**< LPUART receive */ 169 DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, /**< LPUART transmit */ 170 DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ 171 DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ 172 DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ 173 DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ 174 DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ 175 DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ 176 DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ 177 DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ 178 DMA_MSIGSEL_PIS_CH8 = 0x8U, /**< PIS channal 8 */ 179 DMA_MSIGSEL_PIS_CH9 = 0x9U, /**< PIS channal 9 */ 180 DMA_MSIGSEL_PIS_CH10 = 0xAU, /**< PIS channal 10 */ 181 DMA_MSIGSEL_PIS_CH11 = 0xBU, /**< PIS channal 11 */ 182 DMA_MSIGSEL_PIS_CH12 = 0xCU, /**< PIS channal 12 */ 183 DMA_MSIGSEL_PIS_CH13 = 0xDU, /**< PIS channal 13 */ 184 DMA_MSIGSEL_PIS_CH14 = 0xEU, /**< PIS channal 14 */ 185 DMA_MSIGSEL_PIS_CH15 = 0xFU, /**< PIS channal 15 */ 186 DMA_MSIGSEL_QSPI_WRITE = 0x0U, /**< QSPI Write */ 187 DMA_MSIGSEL_QSPI_READ = 0x1U, /**< QSPI Read */ 188 DMA_MSIGSEL_EP_TX1 = 0x0U, /**< USB TX Endport 0 */ 189 DMA_MSIGSEL_EP_TX2 = 0x1U, /**< USB TX Endport 1 */ 190 DMA_MSIGSEL_EP_TX3 = 0x2U, /**< USB TX Endport 2 */ 191 DMA_MSIGSEL_EP_TX4 = 0x3U, /**< USB TX Endport 3 */ 192 DMA_MSIGSEL_EP_TX5 = 0x4U, /**< USB TX Endport 4 */ 193 DMA_MSIGSEL_EP_RX1 = 0x8U, /**< USB RX Endport 0 */ 194 DMA_MSIGSEL_EP_RX2 = 0x9U, /**< USB RX Endport 1 */ 195 DMA_MSIGSEL_EP_RX3 = 0xAU, /**< USB RX Endport 2 */ 196 DMA_MSIGSEL_EP_RX4 = 0xBU, /**< USB RX Endport 3 */ 197 DMA_MSIGSEL_EP_RX5 = 0xCU, /**< USB RX Endport 4 */ 198 } dma_msigsel_t; 199 200 /** 201 * @brief DMA Descriptor control type 202 */ 203 typedef union { 204 struct { 205 uint32_t cycle_ctrl :3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ 206 uint32_t next_useburst :1; /**< Uses the alternate data structure when complete a DMA cycle */ 207 uint32_t n_minus_1 :10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ 208 uint32_t R_power :4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ 209 uint32_t src_prot_ctrl :3; /**< Control the state of HPROT when reads the source data. */ 210 uint32_t dst_prot_ctrl :3; /**< Control the state of HPROT when writes the destination data */ 211 uint32_t src_size :2; /**< Source data size @ref dma_data_size_t */ 212 uint32_t src_inc :2; /**< Control the source address increment. @ref dma_data_inc_t */ 213 uint32_t dst_size :2; /**< Destination data size. @ref dma_data_size_t */ 214 uint32_t dst_inc :2; /**< Destination address increment. @ref dma_data_inc_t */ 215 }; 216 uint32_t word; 217 } dma_ctrl_t; 218 219 /** 220 * @brief Channel control data structure 221 */ 222 typedef struct { 223 void *src; /**< Source data end pointer */ 224 void *dst; /**< Destination data end pointer */ 225 dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ 226 uint32_t use; /**< Reserve for user */ 227 } dma_descriptor_t; 228 229 /** 230 * @brief data increment 231 */ 232 typedef enum { 233 DMA_DATA_INC_BYTE = 0x0U, /**< Address increment by byte */ 234 DMA_DATA_INC_HALFWORD = 0x1U, /**< Address increment by halfword */ 235 DMA_DATA_INC_WORD = 0x2U, /**< Address increment by word */ 236 DMA_DATA_INC_NONE = 0x3U, /**< No increment */ 237 } dma_data_inc_t; 238 239 /** 240 * @brief Data size 241 */ 242 typedef enum { 243 DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ 244 DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ 245 DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ 246 } dma_data_size_t; 247 248 /** 249 * @brief The operating mode of the DMA cycle 250 */ 251 typedef enum { 252 DMA_CYCLE_CTRL_NONE = 0x0U, /**< Stop */ 253 DMA_CYCLE_CTRL_BASIC = 0x1U, /**< Basic */ 254 DMA_CYCLE_CTRL_AUTO = 0x2U, /**< Auto-request */ 255 DMA_CYCLE_CTRL_PINGPONG = 0x3U, /**< Ping-pong */ 256 DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, /**< Memory scatter-gather using the primary structure */ 257 DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, /**< Memory scatter-gather using the alternate structure */ 258 DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, /**< Peripheral scatter-gather using the primary structure */ 259 DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U, /**< Peripheral scatter-gather using the alternate structure */ 260 } dma_cycle_ctrl_t; 261 262 /** 263 * @brief Control how many DMA transfers can occur 264 * before the controller re-arbitrates 265 */ 266 typedef enum { 267 DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ 268 DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ 269 DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ 270 DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ 271 DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ 272 DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ 273 DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ 274 DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ 275 DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ 276 DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ 277 DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ 278 } dma_arbiter_config_t; 279 280 /** 281 * @brief Callback function pointer and param 282 */ 283 typedef struct { 284 void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ 285 void (*err_cbk)(void* arg); /**< DMA occurs error callback */ 286 void *cplt_arg; /**< The parameter of cplt_cbk() */ 287 void *err_arg; /**< The parameter of err_cbk() */ 288 } dma_call_back_t; 289 290 /** 291 * @brief DMA channal configure structure 292 */ 293 typedef struct { 294 void *src; /**< Source data begin pointer */ 295 void *dst; /**< Destination data begin pointer */ 296 uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ 297 dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ 298 dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ 299 dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ 300 dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ 301 type_func_t primary; /**< Use primary descriptor or alternate descriptor */ 302 type_func_t burst; /**< Enable/Disable the useburst setting for this channel */ 303 type_func_t high_prio; /**< High priority or default priority */ 304 type_func_t interrupt; /**< Enable/disable interrupt */ 305 dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ 306 dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ 307 uint8_t channel; /**< Channel index */ 308 } dma_config_t; 309 310 /** 311 * @brief DMA handle structure definition 312 */ 313 typedef struct { 314 DMA_TypeDef *perh; /**< DMA registers base address */ 315 dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ 316 void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ 317 void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ 318 void *cplt_arg; /**< The parameter of cplt_cbk() */ 319 void *err_arg; /**< The parameter of err_cbk() */ 320 } dma_handle_t; 321 322 /** 323 * @brief Descriptor complete state 324 */ 325 typedef enum { 326 DMA_DESCP_CPLT_PRI = 0x0U, /**< Primary descriptor has been completed */ 327 DMA_DESCP_CPLT_ALT = 0x1U, /**< Alternate descriptor has been completed */ 328 DMA_DESCP_CPLT_ALL = 0x2U, /**< Both primary and alternate descriptors have been completed */ 329 } dma_descrp_cplt_t; 330 /** 331 * @} 332 */ 333 334 /** 335 * @defgroup DMA_Private_Macros DMA Private Macros 336 * @{ 337 */ 338 #define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_USB) 339 #define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF) 340 #define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \ 341 ((x) == DMA_DATA_INC_HALFWORD) || \ 342 ((x) == DMA_DATA_INC_WORD) || \ 343 ((x) == DMA_DATA_INC_NONE)) 344 #define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ 345 ((x) == DMA_DATA_SIZE_HALFWORD) || \ 346 ((x) == DMA_DATA_SIZE_WORD)) 347 #define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ 348 ((x) == DMA_CYCLE_CTRL_BASIC) || \ 349 ((x) == DMA_CYCLE_CTRL_AUTO) || \ 350 ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ 351 ((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \ 352 ((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \ 353 ((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \ 354 ((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE)) 355 #define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ 356 ((x) == DMA_R_POWER_2) || \ 357 ((x) == DMA_R_POWER_4) || \ 358 ((x) == DMA_R_POWER_8) || \ 359 ((x) == DMA_R_POWER_16) || \ 360 ((x) == DMA_R_POWER_32) || \ 361 ((x) == DMA_R_POWER_64) || \ 362 ((x) == DMA_R_POWER_128) || \ 363 ((x) == DMA_R_POWER_256) || \ 364 ((x) == DMA_R_POWER_512) || \ 365 ((x) == DMA_R_POWER_1024)) 366 #define IS_DMA(x) ((x) == DMA0) 367 #define IS_DMA_CHANNEL(x) ((x) <= 11) 368 #define IS_DMA_DATA_SIZE(x) ((x) <= 1024) 369 #define IS_DMA_IT_TYPE(x) (((x) <= 11) || ((x) == 31)) 370 /** 371 * @} 372 */ 373 374 /** 375 * @addtogroup DMA_Public_Functions 376 * @{ 377 */ 378 379 /** @addtogroup DMA_Public_Functions_Group1 380 * @{ 381 */ 382 /* Initialization functions */ 383 extern void ald_dma_reset(DMA_TypeDef *DMAx); 384 extern void ald_dma_init(DMA_TypeDef *DMAx); 385 extern void ald_dma_config_struct(dma_config_t *p); 386 extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory); 387 /** 388 * @} 389 */ 390 391 392 /** @addtogroup DMA_Public_Functions_Group2 393 * @{ 394 */ 395 /* Configure DMA channel functions */ 396 extern void ald_dma_config_auto(dma_handle_t *hperh); 397 extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); 398 extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, 399 uint16_t size, uint8_t channel, void (*cbk)(void *arg)); 400 extern void ald_dma_config_basic(dma_handle_t *hperh); 401 extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); 402 extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, 403 dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); 404 extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, 405 uint8_t first, void (*cbk)(void *arg)); 406 extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, 407 uint32_t nr, uint8_t channel, void (*cbk)(void *arg)); 408 extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, 409 dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); 410 /** 411 * @} 412 */ 413 414 /** @addtogroup DMA_Public_Functions_Group3 415 * @{ 416 */ 417 /* DMA control functions */ 418 extern void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); 419 extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); 420 extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); 421 extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); 422 extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); 423 extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel); 424 extern void ald_dma_irq_handler(void); 425 /** 426 * @} 427 */ 428 429 /** 430 * @} 431 */ 432 433 434 /** 435 * @} 436 */ 437 438 /** 439 * @} 440 */ 441 442 #ifdef __cplusplus 443 } 444 #endif 445 446 #endif /*__ALD_DMA_H__ */ 447