1 /*
2  * Copyright (c) 2021-2022 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_DP83867_REGS_H
10 #define HPM_DP83867_REGS_H
11 
12 typedef enum {
13     DP83867_BMCR                        = 0,   /* 0x0: Basic Mode Control Register */
14     DP83867_BMSR                        = 1,   /* 0x1: Basic Mode Status Register */
15     DP83867_PHYIDR1                     = 2,   /* 0x2: PHY Identifier Register #1 */
16     DP83867_PHYIDR2                     = 3,   /* 0x3: PHY Identifier Register #2 */
17     DP83867_ANAR                        = 4,   /* 0x4: MII Interrupt Control Register */
18     DP83867_ANLPAR                      = 5,   /* 0x5: Auto-Negotiation Link Partner Ability Register */
19     DP83867_ANER                        = 6,   /* 0x6: Auto-Negotiate Expansion Register */
20     DP83867_ANNPTR                      = 7,   /* 0x7: Auto-Negotiation Next Page Transmit Register */
21     DP83867_ANNPRR                      = 8,   /* 0x8: Auto-Negotiation Next Page Receive Register */
22     DP83867_CFG1                        = 9,   /* 0x9: Configuration Register 1 */
23     DP83867_STS1                        = 10,  /* 0xA: Status Register 1 */
24     DP83867_REGCR                       = 13,  /* 0xD: Register Control Register */
25     DP83867_ADDAR                       = 14,  /* 0xE: Address or Data Register */
26     DP83867_1KSCR                       = 15,  /* 0xF: 1000BASE-T Status Register */
27     DP83867_PHYCR                       = 16,  /* 0x10: PHY Control Register */
28     DP83867_PHYSTS                      = 17,  /* 0x11: PHY Status Register */
29     DP83867_MICR                        = 18,  /* 0x12: MII Interrupt Control Register */
30     DP83867_ISR                         = 19,  /* 0x13: Interrupt Status Register */
31     DP83867_CRG2                        = 20,  /* 0x14: Configuration Register 2 */
32     DP83867_RECR                        = 21,  /* 0x15: Receiver Error Counter Register */
33     DP83867_STS2                        = 23,  /* 0x17: Status Register 2 */
34     DP83867_LEDCR1                      = 24,  /* 0x18: LED Configuration Register 1 */
35     DP83867_LEDCR2                      = 25,  /* 0x19: LED Configuration Register 2 */
36     DP83867_LEDCR3                      = 26,  /* 0x1A: LED Configuration Register 3 */
37     DP83867_CFG3                        = 30,  /* 0x1E: Configuration Register 3 */
38     DP83867_CTRL                        = 31,  /* 0x1F: Control Register */
39     DP83867_RGMIIDCTL                   = 134, /* 0x86: RGMII Delay Control Register */
40 } DP83867_REG_Type;
41 
42 
43 /* Bitfield definition for register: BMCR */
44 /*
45  * RESET (RW/SC)
46  *
47  * Reset:
48  * 1 = Initiate software Reset / Reset in Process.
49  * 0 = Normal operation.
50  * This bit, which is self-clearing, returns a value of one until the reset
51  * process is complete. The configuration is restrapped.
52  */
53 #define DP83867_BMCR_RESET_MASK (0x8000U)
54 #define DP83867_BMCR_RESET_SHIFT (15U)
55 #define DP83867_BMCR_RESET_SET(x) (((uint16_t)(x) << DP83867_BMCR_RESET_SHIFT) & DP83867_BMCR_RESET_MASK)
56 #define DP83867_BMCR_RESET_GET(x) (((uint16_t)(x) & DP83867_BMCR_RESET_MASK) >> DP83867_BMCR_RESET_SHIFT)
57 
58 /*
59  * LOOPBACK (RW)
60  *
61  * Loopback:
62  * 1 = Loopback enabled.
63  * 0 = Normal operation.
64  * The loopback function enables MAC transmit data to be routed to
65  * the MAC receive data path.
66  * Setting this bit may cause the descrambler to lose synchronization
67  * and produce a 500-µs dead time before any valid data will appear at
68  * the MII receive outputs.
69  */
70 #define DP83867_BMCR_LOOPBACK_MASK (0x4000U)
71 #define DP83867_BMCR_LOOPBACK_SHIFT (14U)
72 #define DP83867_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << DP83867_BMCR_LOOPBACK_SHIFT) & DP83867_BMCR_LOOPBACK_MASK)
73 #define DP83867_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & DP83867_BMCR_LOOPBACK_MASK) >> DP83867_BMCR_LOOPBACK_SHIFT)
74 
75 /*
76  * SPEED0 (RW)
77  *
78  * Speed Select (Bits 6, 13):
79  * When auto-negotiation is disabled writing to this bit allows the port
80  * speed to be selected.
81  * 11 = Reserved
82  * 10 = 1000 Mbps
83  * 1 = 100 Mbps
84  * 0 = 10 Mbps
85  */
86 #define DP83867_BMCR_SPEED0_MASK (0x2000U)
87 #define DP83867_BMCR_SPEED0_SHIFT (13U)
88 #define DP83867_BMCR_SPEED0_SET(x) (((uint16_t)(x) << DP83867_BMCR_SPEED0_SHIFT) & DP83867_BMCR_SPEED0_MASK)
89 #define DP83867_BMCR_SPEED0_GET(x) (((uint16_t)(x) & DP83867_BMCR_SPEED0_MASK) >> DP83867_BMCR_SPEED0_SHIFT)
90 
91 /*
92  * ANE (STRAP, RW)
93  *
94  * Auto-Negotiation Enable:
95  * Strap controls initial value at reset.
96  * 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are
97  * ignored when this bit is set.
98  * 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port
99  * speed and duplex mode.
100  */
101 #define DP83867_BMCR_ANE_MASK (0x1000U)
102 #define DP83867_BMCR_ANE_SHIFT (12U)
103 #define DP83867_BMCR_ANE_SET(x) (((uint16_t)(x) << DP83867_BMCR_ANE_SHIFT) & DP83867_BMCR_ANE_MASK)
104 #define DP83867_BMCR_ANE_GET(x) (((uint16_t)(x) & DP83867_BMCR_ANE_MASK) >> DP83867_BMCR_ANE_SHIFT)
105 
106 /*
107  * PWD (RW)
108  *
109  * Power Down:
110  * 1 = Power down.
111  * 0 = Normal operation.
112  * Setting this bit powers down the PHY. Only the register block is
113  * enabled during a power down condition. This bit is ORd with the
114  * input from the PWRDOWN_INT pin. When the active low
115  * PWRDOWN_INT pin is asserted, this bit will be set.
116  */
117 #define DP83867_BMCR_PWD_MASK (0x800U)
118 #define DP83867_BMCR_PWD_SHIFT (11U)
119 #define DP83867_BMCR_PWD_SET(x) (((uint16_t)(x) << DP83867_BMCR_PWD_SHIFT) & DP83867_BMCR_PWD_MASK)
120 #define DP83867_BMCR_PWD_GET(x) (((uint16_t)(x) & DP83867_BMCR_PWD_MASK) >> DP83867_BMCR_PWD_SHIFT)
121 
122 /*
123  * ISOLATE (RW)
124  *
125  * Isolate:
126  * 1 = Isolates the Port from the MII with the exception of the serial
127  * management.
128  * 0 = Normal operation.
129  */
130 #define DP83867_BMCR_ISOLATE_MASK (0x400U)
131 #define DP83867_BMCR_ISOLATE_SHIFT (10U)
132 #define DP83867_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << DP83867_BMCR_ISOLATE_SHIFT) & DP83867_BMCR_ISOLATE_MASK)
133 #define DP83867_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & DP83867_BMCR_ISOLATE_MASK) >> DP83867_BMCR_ISOLATE_SHIFT)
134 
135 /*
136  * RESTART_AN (RW/SC)
137  *
138  * Restart Auto-Negotiation:
139  * 1 = Restart Auto-Negotiation. Reinitiates the Auto-Negotiation
140  * process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is
141  * ignored. This bit is self-clearing and will return a value of 1 until
142  * Auto-Negotiation is initiated, whereupon it will self-clear. Operation of
143  * the Auto-Negotiation process is not affected by the management
144  * entity clearing this bit.
145  * 0 = Normal operation.
146  */
147 #define DP83867_BMCR_RESTART_AN_MASK (0x200U)
148 #define DP83867_BMCR_RESTART_AN_SHIFT (9U)
149 #define DP83867_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << DP83867_BMCR_RESTART_AN_SHIFT) & DP83867_BMCR_RESTART_AN_MASK)
150 #define DP83867_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & DP83867_BMCR_RESTART_AN_MASK) >> DP83867_BMCR_RESTART_AN_SHIFT)
151 
152 /*
153  * DUPLEX (STRAP, RW)
154  *
155  * Duplex Mode:
156  * When auto-negotiation is disabled writing to this bit allows the port
157  * Duplex capability to be selected.
158  * 1 = Full Duplex operation.
159  * 0 = Half Duplex operation.
160  */
161 #define DP83867_BMCR_DUPLEX_MASK (0x100U)
162 #define DP83867_BMCR_DUPLEX_SHIFT (8U)
163 #define DP83867_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_BMCR_DUPLEX_SHIFT) & DP83867_BMCR_DUPLEX_MASK)
164 #define DP83867_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMCR_DUPLEX_MASK) >> DP83867_BMCR_DUPLEX_SHIFT)
165 
166 /*
167  * COLLISION_TEST (RW)
168  *
169  * Collision Test:
170  * 1 = Collision test enabled.
171  * 0 = Normal operation.
172  * When set, this bit will cause the COL signal to be asserted in
173  * response to the assertion of TX_EN within 512-bit times. The COL
174  * signal will be deasserted within 4-bit times in response to the
175  * deassertion of TX_EN.
176  */
177 #define DP83867_BMCR_COLLISION_TEST_MASK (0x80U)
178 #define DP83867_BMCR_COLLISION_TEST_SHIFT (7U)
179 #define DP83867_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << DP83867_BMCR_COLLISION_TEST_SHIFT) & DP83867_BMCR_COLLISION_TEST_MASK)
180 #define DP83867_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & DP83867_BMCR_COLLISION_TEST_MASK) >> DP83867_BMCR_COLLISION_TEST_SHIFT)
181 
182 /*
183  * SPEED1 (RW)
184  *
185  * Speed Select: See description for bit 13.
186  */
187 #define DP83867_BMCR_SPEED1_MASK (0x40U)
188 #define DP83867_BMCR_SPEED1_SHIFT (6U)
189 #define DP83867_BMCR_SPEED1_SET(x) (((uint16_t)(x) << DP83867_BMCR_SPEED1_SHIFT) & DP83867_BMCR_SPEED1_MASK)
190 #define DP83867_BMCR_SPEED1_GET(x) (((uint16_t)(x) & DP83867_BMCR_SPEED1_MASK) >> DP83867_BMCR_SPEED1_SHIFT)
191 
192 /* Bitfield definition for register: BMSR */
193 /*
194  * 100BASE_T4 (RO/P)
195  *
196  * 100BASE-T4 Capable:
197  * 0 = Device not able to perform 100BASE-T4 mode.
198  */
199 #define DP83867_BMSR_100BASE_T4_MASK (0x8000U)
200 #define DP83867_BMSR_100BASE_T4_SHIFT (15U)
201 #define DP83867_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T4_MASK) >> DP83867_BMSR_100BASE_T4_SHIFT)
202 
203 /*
204  * 100BASE_TX_FULL_DUPLEX (RO/P)
205  *
206  * 100BASE-TX Full Duplex Capable:
207  * 1 = Device able to perform 100BASE-TX in full duplex mode.
208  */
209 #define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK (0x4000U)
210 #define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT (14U)
211 #define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT)
212 
213 /*
214  * 100BASE_TX_HALF_DUPLEX (RO/P)
215  *
216  * 100BASE-TX Half Duplex Capable:
217  * 1 = Device able to perform 100BASE-TX in half duplex mode.
218  */
219 #define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK (0x2000U)
220 #define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT (13U)
221 #define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT)
222 
223 /*
224  * 10BASE_TE_FULL_DUPLEX (RO/P)
225  *
226  * 10BASE-Te Full Duplex Capable:
227  * 1 = Device able to perform 10BASE-Te in full duplex mode.
228  */
229 #define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK (0x1000U)
230 #define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT (12U)
231 #define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT)
232 
233 /*
234  * 10BASE_TE_HALF_DUPLEX (RO/P)
235  *
236  * 10BASE-Te Half Duplex Capable:
237  * 1 = Device able to perform 10BASE-Te in half duplex mode.
238  */
239 #define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK (0x800U)
240 #define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT (11U)
241 #define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT)
242 
243 /*
244  * 100BASE_T2_FULL_DUPLEX (RO/P)
245  *
246  * 100BASE-T2 Full Duplex Capable:
247  * 0 = Device not able to perform 100BASE-T2 in full duplex mode.
248  */
249 #define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK (0x400U)
250 #define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT (10U)
251 #define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT)
252 
253 /*
254  * 100BASE_T2_HALF_DUPLEX (RO/P)
255  *
256  * 100BASE-T2 Half Duplex Capable:
257  * 0 = Device not able to perform 100BASE-T2 in half duplex mode.
258  */
259 #define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK (0x200U)
260 #define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT (9U)
261 #define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT)
262 
263 /*
264  * EXTENDED_STATUS (RO/P)
265  *
266  * 1000BASE-T Extended Status Register:
267  * 1 = Device supports Extended Status Register 0x0F.
268  */
269 #define DP83867_BMSR_EXTENDED_STATUS_MASK (0x100U)
270 #define DP83867_BMSR_EXTENDED_STATUS_SHIFT (8U)
271 #define DP83867_BMSR_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & DP83867_BMSR_EXTENDED_STATUS_MASK) >> DP83867_BMSR_EXTENDED_STATUS_SHIFT)
272 
273 /*
274  * MF_PREAMBLE_SUPPRESSION (RO/P)
275  *
276  * Preamble Suppression Capable:
277  * 1 = Device able to perform management transaction with preamble
278  * suppressed, 32-bits of preamble needed only once after reset,
279  * invalid opcode or invalid turnaround.
280  * 0 = Normal management operation.
281  */
282 #define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK (0x40U)
283 #define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT (6U)
284 #define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT)
285 
286 /*
287  * AUTO_NEGOTIATION_COMPLETE (RO)
288  *
289  * Auto-Negotiation Complete:
290  * 1 = Auto-Negotiation process complete.
291  * 0 = Auto-Negotiation process not complete.
292  */
293 #define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U)
294 #define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U)
295 #define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT)
296 
297 /*
298  * REMOTE_FAULT (RO/LH)
299  *
300  * Remote Fault:
301  * 1 = Remote Fault condition detected (cleared on read or by reset).
302  * Fault criteria: Far-End Fault Indication or notification from Link
303  * Partner of Remote Fault.
304  * 0 = No remote fault condition detected.
305  */
306 #define DP83867_BMSR_REMOTE_FAULT_MASK (0x10U)
307 #define DP83867_BMSR_REMOTE_FAULT_SHIFT (4U)
308 #define DP83867_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83867_BMSR_REMOTE_FAULT_MASK) >> DP83867_BMSR_REMOTE_FAULT_SHIFT)
309 
310 /*
311  * AUTO_NEGOTIATION_ABILITY ( RO/P )
312  *
313  * Auto Negotiation Ability:
314  * 1 = Device is able to perform Auto-Negotiation.
315  * 0 = Device is not able to perform Auto-Negotiation.
316  */
317 #define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U)
318 #define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U)
319 #define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT)
320 
321 /*
322  * LINK_STATUS ( RO/LL)
323  *
324  * Link Status:
325  * 1 = Valid link established.
326  * 0 = Link not established.
327  * The criteria for link validity is implementation specific. The
328  * occurrence of a link failure condition will causes the Link Status bit
329  * to clear. Once cleared, this bit may only be set by establishing a
330  * good link condition and a read through the management interface.
331  */
332 #define DP83867_BMSR_LINK_STATUS_MASK (0x4U)
333 #define DP83867_BMSR_LINK_STATUS_SHIFT (2U)
334 #define DP83867_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83867_BMSR_LINK_STATUS_MASK) >> DP83867_BMSR_LINK_STATUS_SHIFT)
335 
336 /*
337  * JABBER_DETECT ( RO/LH)
338  *
339  * Jabber Detect: This bit only has meaning in 10-Mbps mode.
340  * 1 = Jabber condition detected.
341  * 0 = No Jabber.
342  * This bit is implemented with a latching function, such that the
343  * occurrence of a jabber condition causes it to set until it is cleared by
344  * a read to this register by the management interface or by a reset.
345  */
346 #define DP83867_BMSR_JABBER_DETECT_MASK (0x2U)
347 #define DP83867_BMSR_JABBER_DETECT_SHIFT (1U)
348 #define DP83867_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83867_BMSR_JABBER_DETECT_MASK) >> DP83867_BMSR_JABBER_DETECT_SHIFT)
349 
350 /*
351  * EXTENDED_CAPABILITY (RO/P)
352  *
353  * Extended Capability:
354  * 1 = Extended register capabilities.
355  * 0 = Basic register set capabilities only.
356  */
357 #define DP83867_BMSR_EXTENDED_CAPABILITY_MASK (0x1U)
358 #define DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT (0U)
359 #define DP83867_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & DP83867_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT)
360 
361 /* Bitfield definition for register: PHYIDR1 */
362 /*
363  * OUI_MSB (RO/P)
364  *
365  * OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are
366  * stored in bits 15 to 0 of this register. The most significant two bits of
367  * the OUI are ignored (the IEEE standard refers to these as bits 1 and
368  * 2).
369  */
370 #define DP83867_PHYIDR1_OUI_MSB_MASK (0xFFFFU)
371 #define DP83867_PHYIDR1_OUI_MSB_SHIFT (0U)
372 #define DP83867_PHYIDR1_OUI_MSB_GET(x) (((uint16_t)(x) & DP83867_PHYIDR1_OUI_MSB_MASK) >> DP83867_PHYIDR1_OUI_MSB_SHIFT)
373 
374 /* Bitfield definition for register: PHYIDR2 */
375 /*
376  * OUI_LSB (RO/P)
377  *
378  * OUI Least Significant Bits:
379  * Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of
380  * this register respectively.
381  */
382 #define DP83867_PHYIDR2_OUI_LSB_MASK (0xFC00U)
383 #define DP83867_PHYIDR2_OUI_LSB_SHIFT (10U)
384 #define DP83867_PHYIDR2_OUI_LSB_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_OUI_LSB_MASK) >> DP83867_PHYIDR2_OUI_LSB_SHIFT)
385 
386 /*
387  * VNDR_MDL (RO/P)
388  *
389  * Vendor Model Number:
390  * The six bits of vendor model number are mapped from bits 9 to 4
391  * (most significant bit to bit 9).
392  */
393 #define DP83867_PHYIDR2_VNDR_MDL_MASK (0x3F0U)
394 #define DP83867_PHYIDR2_VNDR_MDL_SHIFT (4U)
395 #define DP83867_PHYIDR2_VNDR_MDL_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_VNDR_MDL_MASK) >> DP83867_PHYIDR2_VNDR_MDL_SHIFT)
396 
397 /*
398  * MDL_REV (RO/P)
399  *
400  * Model Revision Number:
401  * Four bits of the vendor model revision number are mapped from bits
402  * 3 to 0 (most significant bit to bit 3). This field will be incremented for
403  * all major device changes.
404  */
405 #define DP83867_PHYIDR2_MDL_REV_MASK (0xFU)
406 #define DP83867_PHYIDR2_MDL_REV_SHIFT (0U)
407 #define DP83867_PHYIDR2_MDL_REV_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_MDL_REV_MASK) >> DP83867_PHYIDR2_MDL_REV_SHIFT)
408 
409 /* Bitfield definition for register: ANAR */
410 /*
411  * NP (RW)
412  *
413  * Next Page Indication:
414  * 0 = Next Page Transfer not desired.
415  * 1 = Next Page Transfer desired.
416  */
417 #define DP83867_ANAR_NP_MASK (0x8000U)
418 #define DP83867_ANAR_NP_SHIFT (15U)
419 #define DP83867_ANAR_NP_SET(x) (((uint16_t)(x) << DP83867_ANAR_NP_SHIFT) & DP83867_ANAR_NP_MASK)
420 #define DP83867_ANAR_NP_GET(x) (((uint16_t)(x) & DP83867_ANAR_NP_MASK) >> DP83867_ANAR_NP_SHIFT)
421 
422 /*
423  * RF (RW)
424  *
425  * Remote Fault:
426  * 1 = Advertises that this device has detected a Remote Fault.
427  * 0 = No Remote Fault detected.
428  */
429 #define DP83867_ANAR_RF_MASK (0x2000U)
430 #define DP83867_ANAR_RF_SHIFT (13U)
431 #define DP83867_ANAR_RF_SET(x) (((uint16_t)(x) << DP83867_ANAR_RF_SHIFT) & DP83867_ANAR_RF_MASK)
432 #define DP83867_ANAR_RF_GET(x) (((uint16_t)(x) & DP83867_ANAR_RF_MASK) >> DP83867_ANAR_RF_SHIFT)
433 
434 /*
435  * ASM_DIR (RW)
436  *
437  * Asymmetric PAUSE Support for Full Duplex Links:
438  * The ASM_DIR bit indicates that asymmetric PAUSE is supported.
439  * Encoding and resolution of PAUSE bits is defined in IEEE 802.3
440  * Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution
441  * status is reported in PHYCR[13:12].
442  * 1 = Advertise that the DTE (MAC) has implemented both the
443  * optional MAC control sublayer and the pause function as specified
444  * in clause 31 and annex 31B of 802.3u.
445  * 0 = No MAC based full duplex flow control.
446  */
447 #define DP83867_ANAR_ASM_DIR_MASK (0x800U)
448 #define DP83867_ANAR_ASM_DIR_SHIFT (11U)
449 #define DP83867_ANAR_ASM_DIR_SET(x) (((uint16_t)(x) << DP83867_ANAR_ASM_DIR_SHIFT) & DP83867_ANAR_ASM_DIR_MASK)
450 #define DP83867_ANAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83867_ANAR_ASM_DIR_MASK) >> DP83867_ANAR_ASM_DIR_SHIFT)
451 
452 /*
453  * PAUSE (RW)
454  *
455  * PAUSE Support for Full Duplex Links:
456  * The PAUSE bit indicates that the device is capable of providing the
457  * symmetric PAUSE functions as defined in Annex 31B.
458  * Encoding and resolution of PAUSE bits is defined in IEEE 802.3
459  * Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution
460  * status is reported in PHYCR[13:12].
461  * 1 = Advertise that the DTE (MAC) has implemented both the
462  * optional MAC control sublayer and the pause function as specified
463  * in clause 31 and annex 31B of 802.3u.
464  * 0 = No MAC based full duplex flow control.
465  */
466 #define DP83867_ANAR_PAUSE_MASK (0x400U)
467 #define DP83867_ANAR_PAUSE_SHIFT (10U)
468 #define DP83867_ANAR_PAUSE_SET(x) (((uint16_t)(x) << DP83867_ANAR_PAUSE_SHIFT) & DP83867_ANAR_PAUSE_MASK)
469 #define DP83867_ANAR_PAUSE_GET(x) (((uint16_t)(x) & DP83867_ANAR_PAUSE_MASK) >> DP83867_ANAR_PAUSE_SHIFT)
470 
471 /*
472  * T4 (RO/P)
473  *
474  * 100BASE-T4 Support:
475  * 1 = 100BASE-T4 is supported by the local device.
476  * 0 = 100BASE-T4 not supported.
477  */
478 #define DP83867_ANAR_T4_MASK (0x200U)
479 #define DP83867_ANAR_T4_SHIFT (9U)
480 #define DP83867_ANAR_T4_GET(x) (((uint16_t)(x) & DP83867_ANAR_T4_MASK) >> DP83867_ANAR_T4_SHIFT)
481 
482 /*
483  * TX_FD (STRAP, RW)
484  *
485  * 100BASE-TX Full Duplex Support:
486  * 1 = 100BASE-TX Full Duplex is supported by the local device.
487  * 0 = 100BASE-TX Full Duplex not supported.
488  */
489 #define DP83867_ANAR_TX_FD_MASK (0x100U)
490 #define DP83867_ANAR_TX_FD_SHIFT (8U)
491 #define DP83867_ANAR_TX_FD_SET(x) (((uint16_t)(x) << DP83867_ANAR_TX_FD_SHIFT) & DP83867_ANAR_TX_FD_MASK)
492 #define DP83867_ANAR_TX_FD_GET(x) (((uint16_t)(x) & DP83867_ANAR_TX_FD_MASK) >> DP83867_ANAR_TX_FD_SHIFT)
493 
494 /*
495  * TX (STRAP, RW)
496  *
497  * 100BASE-TX Support:
498  * 1 = 100BASE-TX is supported by the local device.
499  * 0 = 100BASE-TX not supported.
500  */
501 #define DP83867_ANAR_TX_MASK (0x80U)
502 #define DP83867_ANAR_TX_SHIFT (7U)
503 #define DP83867_ANAR_TX_SET(x) (((uint16_t)(x) << DP83867_ANAR_TX_SHIFT) & DP83867_ANAR_TX_MASK)
504 #define DP83867_ANAR_TX_GET(x) (((uint16_t)(x) & DP83867_ANAR_TX_MASK) >> DP83867_ANAR_TX_SHIFT)
505 
506 /*
507  * 10_FD (STRAP, RW)
508  *
509  * 10BASE-Te Full Duplex Support:
510  * 1 = 10BASE-Te Full Duplex is supported by the local device.
511  * 0 = 10BASE-Te Full Duplex not supported.
512  */
513 #define DP83867_ANAR_10_FD_MASK (0x40U)
514 #define DP83867_ANAR_10_FD_SHIFT (6U)
515 #define DP83867_ANAR_10_FD_SET(x) (((uint16_t)(x) << DP83867_ANAR_10_FD_SHIFT) & DP83867_ANAR_10_FD_MASK)
516 #define DP83867_ANAR_10_FD_GET(x) (((uint16_t)(x) & DP83867_ANAR_10_FD_MASK) >> DP83867_ANAR_10_FD_SHIFT)
517 
518 /*
519  * 10BASETE_EN (STRAP, RW)
520  *
521  * 10BASE-Te Support:
522  * 1 = 10BASE-Te is supported by the local device.
523  * 0 = 10BASE-Te not supported.
524  */
525 #define DP83867_ANAR_10BASETE_EN_MASK (0x20U)
526 #define DP83867_ANAR_10BASETE_EN_SHIFT (5U)
527 #define DP83867_ANAR_10BASETE_EN_SET(x) (((uint16_t)(x) << DP83867_ANAR_10BASETE_EN_SHIFT) & DP83867_ANAR_10BASETE_EN_MASK)
528 #define DP83867_ANAR_10BASETE_EN_GET(x) (((uint16_t)(x) & DP83867_ANAR_10BASETE_EN_MASK) >> DP83867_ANAR_10BASETE_EN_SHIFT)
529 
530 /*
531  * SELECTOR (RW)
532  *
533  * Protocol Selection Bits:
534  * These bits contain the binary encoded protocol selector supported
535  * by this port. <00001> indicates that this device supports IEEE
536  * 802.3u.
537  */
538 #define DP83867_ANAR_SELECTOR_MASK (0x1FU)
539 #define DP83867_ANAR_SELECTOR_SHIFT (0U)
540 #define DP83867_ANAR_SELECTOR_SET(x) (((uint16_t)(x) << DP83867_ANAR_SELECTOR_SHIFT) & DP83867_ANAR_SELECTOR_MASK)
541 #define DP83867_ANAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83867_ANAR_SELECTOR_MASK) >> DP83867_ANAR_SELECTOR_SHIFT)
542 
543 /* Bitfield definition for register: ANLPAR */
544 /*
545  * NP (RO)
546  *
547  * Next Page Indication:
548  * 0 = Link Partner does not desire Next Page Transfer.
549  * 1 = Link Partner desires Next Page Transfer.
550  */
551 #define DP83867_ANLPAR_NP_MASK (0x8000U)
552 #define DP83867_ANLPAR_NP_SHIFT (15U)
553 #define DP83867_ANLPAR_NP_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_NP_MASK) >> DP83867_ANLPAR_NP_SHIFT)
554 
555 /*
556  * ACK (RO)
557  *
558  * Acknowledge:
559  * 1 = Link Partner acknowledges reception of the ability data word.
560  * 0 = Not acknowledged.
561  * The Auto-Negotiation state machine will automatically control this bit
562  * based on the incoming FLP bursts.
563  */
564 #define DP83867_ANLPAR_ACK_MASK (0x4000U)
565 #define DP83867_ANLPAR_ACK_SHIFT (14U)
566 #define DP83867_ANLPAR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_ACK_MASK) >> DP83867_ANLPAR_ACK_SHIFT)
567 
568 /*
569  * RF (RO)
570  *
571  * Remote Fault:
572  * 1 = Remote Fault indicated by Link Partner.
573  * 0 = No Remote Fault indicated by Link Partner.
574  */
575 #define DP83867_ANLPAR_RF_MASK (0x2000U)
576 #define DP83867_ANLPAR_RF_SHIFT (13U)
577 #define DP83867_ANLPAR_RF_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_RF_MASK) >> DP83867_ANLPAR_RF_SHIFT)
578 
579 /*
580  * ASM_DIR (RO)
581  *
582  * ASYMMETRIC PAUSE:
583  * 1 = Asymmetric pause is supported by the Link Partner.
584  * 0 = Asymmetric pause is not supported by the Link Partner.
585  */
586 #define DP83867_ANLPAR_ASM_DIR_MASK (0x800U)
587 #define DP83867_ANLPAR_ASM_DIR_SHIFT (11U)
588 #define DP83867_ANLPAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_ASM_DIR_MASK) >> DP83867_ANLPAR_ASM_DIR_SHIFT)
589 
590 /*
591  * PAUSE (RO)
592  *
593  * PAUSE:
594  * 1 = Pause function is supported by the Link Partner.
595  * 0 = Pause function is not supported by the Link Partner.
596  */
597 #define DP83867_ANLPAR_PAUSE_MASK (0x400U)
598 #define DP83867_ANLPAR_PAUSE_SHIFT (10U)
599 #define DP83867_ANLPAR_PAUSE_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_PAUSE_MASK) >> DP83867_ANLPAR_PAUSE_SHIFT)
600 
601 /*
602  * T4 (RO)
603  *
604  * 100BASE-T4 Support:
605  * 1 = 100BASE-T4 is supported by the Link Partner.
606  * 0 = 100BASE-T4 not supported by the Link Partner.
607  */
608 #define DP83867_ANLPAR_T4_MASK (0x200U)
609 #define DP83867_ANLPAR_T4_SHIFT (9U)
610 #define DP83867_ANLPAR_T4_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_T4_MASK) >> DP83867_ANLPAR_T4_SHIFT)
611 
612 /*
613  * TX_FD (RO)
614  *
615  * 100BASE-TX Full Duplex Support:
616  * 1 = 100BASE-TX Full Duplex is supported by the Link Partner.
617  * 0 = 100BASE-TX Full Duplex not supported by the Link Partner.
618  */
619 #define DP83867_ANLPAR_TX_FD_MASK (0x100U)
620 #define DP83867_ANLPAR_TX_FD_SHIFT (8U)
621 #define DP83867_ANLPAR_TX_FD_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_TX_FD_MASK) >> DP83867_ANLPAR_TX_FD_SHIFT)
622 
623 /*
624  * TX (RO)
625  *
626  * 100BASE-TX Support:
627  * 1 = 100BASE-TX is supported by the Link Partner.
628  * 0 = 100BASE-TX not supported by the Link Partner.
629  */
630 #define DP83867_ANLPAR_TX_MASK (0x80U)
631 #define DP83867_ANLPAR_TX_SHIFT (7U)
632 #define DP83867_ANLPAR_TX_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_TX_MASK) >> DP83867_ANLPAR_TX_SHIFT)
633 
634 /*
635  * 10_FD (RO)
636  *
637  * 10BASE-Te Full Duplex Support:
638  * 1 = 10BASE-Te Full Duplex is supported by the Link Partner.
639  * 0 = 10BASE-Te Full Duplex not supported by the Link Partner.
640  */
641 #define DP83867_ANLPAR_10_FD_MASK (0x40U)
642 #define DP83867_ANLPAR_10_FD_SHIFT (6U)
643 #define DP83867_ANLPAR_10_FD_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_10_FD_MASK) >> DP83867_ANLPAR_10_FD_SHIFT)
644 
645 /*
646  * 10 (RO)
647  *
648  * 10BASE-Te Support:
649  * 1 = 10BASE-Te is supported by the Link Partner.
650  * 0 = 10BASE-Te not supported by the Link Partner.
651  */
652 #define DP83867_ANLPAR_10_MASK (0x20U)
653 #define DP83867_ANLPAR_10_SHIFT (5U)
654 #define DP83867_ANLPAR_10_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_10_MASK) >> DP83867_ANLPAR_10_SHIFT)
655 
656 /*
657  * SELECTOR (RO)
658  *
659  * Protocol Selection Bits:
660  * Link Partner's binary encoded protocol selector.
661  */
662 #define DP83867_ANLPAR_SELECTOR_MASK (0x1FU)
663 #define DP83867_ANLPAR_SELECTOR_SHIFT (0U)
664 #define DP83867_ANLPAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_SELECTOR_MASK) >> DP83867_ANLPAR_SELECTOR_SHIFT)
665 
666 /* Bitfield definition for register: ANER */
667 /*
668  * RX_NEXT_PAGE_LOC_ABLE (RO)
669  *
670  * Receive Next Page Location Able:
671  * 1 = Received Next Page storage location is specified by bit 6.5.
672  * 0 = Received Next Page storage location is not specified by bit 6.5.
673  */
674 #define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK (0x40U)
675 #define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT (6U)
676 #define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK) >> DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT)
677 
678 /*
679  * RX_NEXT_PAGE_STOR_LOC (RO)
680  *
681  * Receive Next Page Storage Location:
682  * 1 = Link Partner Next Pages are stored in register 8.
683  * 0 = Link Partner Next Pages are stored in register 5.
684  */
685 #define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK (0x20U)
686 #define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT (5U)
687 #define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_GET(x) (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK) >> DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT)
688 
689 /*
690  * PDF (RO)
691  *
692  * Parallel Detection Fault:
693  * 1 = A fault has been detected via the Parallel Detection function.
694  * 0 = A fault has not been detected.
695  */
696 #define DP83867_ANER_PDF_MASK (0x10U)
697 #define DP83867_ANER_PDF_SHIFT (4U)
698 #define DP83867_ANER_PDF_GET(x) (((uint16_t)(x) & DP83867_ANER_PDF_MASK) >> DP83867_ANER_PDF_SHIFT)
699 
700 /*
701  * LP_NP_ABLE (RO)
702  *
703  * Link Partner Next Page Able:
704  * 1 = Link Partner does support Next Page.
705  * 0 = Link Partner does not support Next Page.
706  */
707 #define DP83867_ANER_LP_NP_ABLE_MASK (0x8U)
708 #define DP83867_ANER_LP_NP_ABLE_SHIFT (3U)
709 #define DP83867_ANER_LP_NP_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_LP_NP_ABLE_MASK) >> DP83867_ANER_LP_NP_ABLE_SHIFT)
710 
711 /*
712  * NP_ABLE (RO/P)
713  *
714  * Next Page Able:
715  * 1 = Indicates local device is able to send additional Next Pages.
716  */
717 #define DP83867_ANER_NP_ABLE_MASK (0x4U)
718 #define DP83867_ANER_NP_ABLE_SHIFT (2U)
719 #define DP83867_ANER_NP_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_NP_ABLE_MASK) >> DP83867_ANER_NP_ABLE_SHIFT)
720 
721 /*
722  * PAGE_RX (RO/COR)
723  *
724  * Link Code Word Page Received:
725  * 1 = Link Code Word has been received, cleared on a read.
726  * 0 = Link Code Word has not been received.
727  */
728 #define DP83867_ANER_PAGE_RX_MASK (0x2U)
729 #define DP83867_ANER_PAGE_RX_SHIFT (1U)
730 #define DP83867_ANER_PAGE_RX_GET(x) (((uint16_t)(x) & DP83867_ANER_PAGE_RX_MASK) >> DP83867_ANER_PAGE_RX_SHIFT)
731 
732 /*
733  * LP_AN_ABLE (RO)
734  *
735  * Link Partner Auto-Negotiation Able:
736  * 1 = Indicates that the Link Partner supports Auto-Negotiation.
737  * 0 = Indicates that the Link Partner does not support Auto-
738  * Negotiation.
739  */
740 #define DP83867_ANER_LP_AN_ABLE_MASK (0x1U)
741 #define DP83867_ANER_LP_AN_ABLE_SHIFT (0U)
742 #define DP83867_ANER_LP_AN_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_LP_AN_ABLE_MASK) >> DP83867_ANER_LP_AN_ABLE_SHIFT)
743 
744 /* Bitfield definition for register: ANNPTR */
745 /*
746  * NP (RW)
747  *
748  * Next Page Indication:
749  * 0 = No other Next Page Transfer desired.
750  * 1 = Another Next Page desired.
751  */
752 #define DP83867_ANNPTR_NP_MASK (0x8000U)
753 #define DP83867_ANNPTR_NP_SHIFT (15U)
754 #define DP83867_ANNPTR_NP_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_NP_SHIFT) & DP83867_ANNPTR_NP_MASK)
755 #define DP83867_ANNPTR_NP_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_NP_MASK) >> DP83867_ANNPTR_NP_SHIFT)
756 
757 /*
758  * ACK (RO)
759  *
760  * Acknowledge:
761  * 1 = Acknowledge reception of link code word
762  * 0 = Do not acknowledge of link code word.
763  */
764 #define DP83867_ANNPTR_ACK_MASK (0x4000U)
765 #define DP83867_ANNPTR_ACK_SHIFT (14U)
766 #define DP83867_ANNPTR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_ACK_MASK) >> DP83867_ANNPTR_ACK_SHIFT)
767 
768 /*
769  * MP (RW)
770  *
771  * Message Page:
772  * 1 = Current page is a Message Page.
773  * 0 = Current page is an Unformatted Page.
774  */
775 #define DP83867_ANNPTR_MP_MASK (0x2000U)
776 #define DP83867_ANNPTR_MP_SHIFT (13U)
777 #define DP83867_ANNPTR_MP_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_MP_SHIFT) & DP83867_ANNPTR_MP_MASK)
778 #define DP83867_ANNPTR_MP_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_MP_MASK) >> DP83867_ANNPTR_MP_SHIFT)
779 
780 /*
781  * ACK2 (RW)
782  *
783  * Acknowledge2:
784  * 1 = Will comply with message.
785  * 0 = Cannot comply with message.
786  * Acknowledge2 is used by the next page function to indicate that
787  * Local Device has the ability to comply with the message received.
788  */
789 #define DP83867_ANNPTR_ACK2_MASK (0x1000U)
790 #define DP83867_ANNPTR_ACK2_SHIFT (12U)
791 #define DP83867_ANNPTR_ACK2_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_ACK2_SHIFT) & DP83867_ANNPTR_ACK2_MASK)
792 #define DP83867_ANNPTR_ACK2_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_ACK2_MASK) >> DP83867_ANNPTR_ACK2_SHIFT)
793 
794 /*
795  * TOG_TX (RO)
796  *
797  * Toggle:
798  * 1 = Value of toggle bit in previously transmitted Link Code Word
799  * was 0.
800  * 0 = Value of toggle bit in previously transmitted Link Code Word
801  * was 1.
802  * Toggle is used by the Arbitration function within Auto-Negotiation to
803  * ensure synchronization with the Link Partner during Next Page
804  * exchange. This bit shall always take the opposite value of the
805  * Toggle bit in the previously exchanged Link Code Word.
806  */
807 #define DP83867_ANNPTR_TOG_TX_MASK (0x800U)
808 #define DP83867_ANNPTR_TOG_TX_SHIFT (11U)
809 #define DP83867_ANNPTR_TOG_TX_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_TOG_TX_MASK) >> DP83867_ANNPTR_TOG_TX_SHIFT)
810 
811 /*
812  * CODE (RW)
813  *
814  * Code:
815  * This field represents the code field of the next page transmission. If
816  * the MP bit is set (bit 13 of this register), then the code shall be
817  * interpreted as a "Message Page”, as defined in Annex 28C of IEEE
818  * 802.3u. Otherwise, the code shall be interpreted as an "Unformatted
819  * Page”, and the interpretation is application specific.
820  * The default value of the CODE represents a Null Page as defined in
821  * Annex 28C of IEEE 802.3u.
822  */
823 #define DP83867_ANNPTR_CODE_MASK (0x7FFU)
824 #define DP83867_ANNPTR_CODE_SHIFT (0U)
825 #define DP83867_ANNPTR_CODE_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_CODE_SHIFT) & DP83867_ANNPTR_CODE_MASK)
826 #define DP83867_ANNPTR_CODE_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_CODE_MASK) >> DP83867_ANNPTR_CODE_SHIFT)
827 
828 /* Bitfield definition for register: ANNPRR */
829 /*
830  * NP (RW)
831  *
832  * Next Page Indication:
833  * 0 = No other Next Page Transfer desired by the link partner.
834  * 1 = Another Next Page desired by the link partner.
835  */
836 #define DP83867_ANNPRR_NP_MASK (0x8000U)
837 #define DP83867_ANNPRR_NP_SHIFT (15U)
838 #define DP83867_ANNPRR_NP_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_NP_SHIFT) & DP83867_ANNPRR_NP_MASK)
839 #define DP83867_ANNPRR_NP_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_NP_MASK) >> DP83867_ANNPRR_NP_SHIFT)
840 
841 /*
842  * ACK (RO)
843  *
844  * Acknowledge:
845  * 1 = Acknowledge reception of link code word by the link partner.
846  * 0 = Link partner does not acknowledge reception of link code word.
847  */
848 #define DP83867_ANNPRR_ACK_MASK (0x4000U)
849 #define DP83867_ANNPRR_ACK_SHIFT (14U)
850 #define DP83867_ANNPRR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_ACK_MASK) >> DP83867_ANNPRR_ACK_SHIFT)
851 
852 /*
853  * MP (RW)
854  *
855  * Message Page:
856  * 1 = Received page is a Message Page.
857  * 0 = Received page is an Unformatted Page.
858  */
859 #define DP83867_ANNPRR_MP_MASK (0x2000U)
860 #define DP83867_ANNPRR_MP_SHIFT (13U)
861 #define DP83867_ANNPRR_MP_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_MP_SHIFT) & DP83867_ANNPRR_MP_MASK)
862 #define DP83867_ANNPRR_MP_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_MP_MASK) >> DP83867_ANNPRR_MP_SHIFT)
863 
864 /*
865  * ACK2 (RW)
866  *
867  * Acknowledge2:
868  * 1 = Link partner sets the ACK2 bit.
869  * 0 = Link partner coes not set the ACK2 bit.
870  * Acknowledge2 is used by the next page function to indicate that link
871  * partner has the ability to comply with the message received.
872  */
873 #define DP83867_ANNPRR_ACK2_MASK (0x1000U)
874 #define DP83867_ANNPRR_ACK2_SHIFT (12U)
875 #define DP83867_ANNPRR_ACK2_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_ACK2_SHIFT) & DP83867_ANNPRR_ACK2_MASK)
876 #define DP83867_ANNPRR_ACK2_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_ACK2_MASK) >> DP83867_ANNPRR_ACK2_SHIFT)
877 
878 /*
879  * TOG_TX (RO)
880  *
881  * Toggle:
882  * 1 = Value of toggle bit in previously transmitted Link Code Word
883  * was 0.
884  * 0 = Value of toggle bit in previously transmitted Link Code Word
885  * was 1.
886  * Toggle is used by the Arbitration function within Auto-Negotiation to
887  * ensure synchronization with the Link Partner during Next Page
888  * exchange. This bit shall always take the opposite value of the
889  * Toggle bit in the previously exchanged Link Code Word.
890  */
891 #define DP83867_ANNPRR_TOG_TX_MASK (0x800U)
892 #define DP83867_ANNPRR_TOG_TX_SHIFT (11U)
893 #define DP83867_ANNPRR_TOG_TX_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_TOG_TX_MASK) >> DP83867_ANNPRR_TOG_TX_SHIFT)
894 
895 /*
896  * CODE (RW)
897  *
898  * Code:
899  * This field represents the code field of the next page transmission. If
900  * the MP bit is set (bit 13 of this register), then the code shall be
901  * interpreted as a "Message Page”, as defined in Annex 28C of IEEE
902  * 802.3u. Otherwise, the code shall be interpreted as an "Unformatted
903  * Page”, and the interpretation is application specific.
904  * The default value of the CODE represents a Null Page as defined in
905  * Annex 28C of IEEE 802.3u.
906  */
907 #define DP83867_ANNPRR_CODE_MASK (0x7FFU)
908 #define DP83867_ANNPRR_CODE_SHIFT (0U)
909 #define DP83867_ANNPRR_CODE_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_CODE_SHIFT) & DP83867_ANNPRR_CODE_MASK)
910 #define DP83867_ANNPRR_CODE_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_CODE_MASK) >> DP83867_ANNPRR_CODE_SHIFT)
911 
912 /* Bitfield definition for register: CFG1 */
913 /*
914  * TEST_MODE (RW)
915  *
916  * Test Mode Select:
917  * 111 = Test Mode 7 - Repetitive {Pulse, 63 zeros}
918  * 110 = Test Mode 6 - Repetitive 0001 sequence
919  * 101 = Test Mode 5 - Scrambled MLT3 Idles
920  * 100 = Test Mode 4 - Transmit Distortion Test
921  * 011 = Test Mode 3 - Transmit Jitter Test (Slave Mode)
922  * 010 = Test Mode 2 - Transmit Jitter Test (Master Mode)
923  * 001 = Test Mode 1 - Transmit Waveform Test
924  * 000 = Normal Mode
925  */
926 #define DP83867_CFG1_TEST_MODE_MASK (0xE000U)
927 #define DP83867_CFG1_TEST_MODE_SHIFT (13U)
928 #define DP83867_CFG1_TEST_MODE_SET(x) (((uint16_t)(x) << DP83867_CFG1_TEST_MODE_SHIFT) & DP83867_CFG1_TEST_MODE_MASK)
929 #define DP83867_CFG1_TEST_MODE_GET(x) (((uint16_t)(x) & DP83867_CFG1_TEST_MODE_MASK) >> DP83867_CFG1_TEST_MODE_SHIFT)
930 
931 /*
932  * MASTER_SLAVE_MANUAL_CONFIGURATION (RW)
933  *
934  * Enable Manual Master / Slave Configuration:
935  * 1 = Enable Manual Master/Slave Configuration control.
936  * 0 = Disable Manual Master/Slave Configuration control.
937  * Using the manual configuration feature may prevent the PHY from
938  * establishing link in 1000Base-T mode if a conflict with the link
939  * partner’s setting exists.
940  */
941 #define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK (0x1000U)
942 #define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT (12U)
943 #define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SET(x) (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK)
944 #define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_GET(x) (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK) >> DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT)
945 
946 /*
947  * MASTER_SLAVE_CONFIGURATION_VALUE (RW)
948  *
949  * Manual Master / Slave Configuration Value:
950  * 1 = Set PHY as MASTER when register 09h bit 12 = 1.
951  * 0 = Set PHY as SLAVE when register 09h bit 12 = 1.
952  * Using the manual configuration feature may prevent the PHY from
953  * establishing link in 1000Base-T mode if a conflict with the link
954  * partner’s setting exists.
955  */
956 #define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK (0x800U)
957 #define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT (11U)
958 #define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SET(x) (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK)
959 #define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_GET(x) (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK) >> DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT)
960 
961 /*
962  * PORT_TYPE (RW)
963  *
964  * Advertise Device Type: Multi or single port:
965  * 1 = Multi-port device.
966  * 0 = Single-port device.
967  */
968 #define DP83867_CFG1_PORT_TYPE_MASK (0x400U)
969 #define DP83867_CFG1_PORT_TYPE_SHIFT (10U)
970 #define DP83867_CFG1_PORT_TYPE_SET(x) (((uint16_t)(x) << DP83867_CFG1_PORT_TYPE_SHIFT) & DP83867_CFG1_PORT_TYPE_MASK)
971 #define DP83867_CFG1_PORT_TYPE_GET(x) (((uint16_t)(x) & DP83867_CFG1_PORT_TYPE_MASK) >> DP83867_CFG1_PORT_TYPE_SHIFT)
972 
973 /*
974  * 1000BASE_T_FULL_DUPLEX (RW)
975  *
976  * Advertise 1000BASE-T Full Duplex Capable:
977  * 1 = Advertise 1000Base-T Full Duplex ability.
978  * 0 = Do not advertise 1000Base-T Full Duplex ability.
979  */
980 #define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK (0x200U)
981 #define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT (9U)
982 #define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK)
983 #define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT)
984 
985 /*
986  * 1000BASE_T_HALF_DUPLEX (RW)
987  *
988  * Advertise 1000BASE-T Half Duplex Capable:
989  * 1 = Advertise 1000Base-T Half Duplex ability.
990  * 0 = Do not advertise 1000Base-T Half Duplex ability.
991  */
992 #define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK (0x100U)
993 #define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT (8U)
994 #define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK)
995 #define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT)
996 
997 /*
998  * TDR_AUTO_RUN (RW)
999  *
1000  * Automatic TDR on Link Down:
1001  * 1 = Enable execution of TDR procedure after link down event.
1002  * 0 = Disable automatic execution of TDR.
1003  */
1004 #define DP83867_CFG1_TDR_AUTO_RUN_MASK (0x80U)
1005 #define DP83867_CFG1_TDR_AUTO_RUN_SHIFT (7U)
1006 #define DP83867_CFG1_TDR_AUTO_RUN_SET(x) (((uint16_t)(x) << DP83867_CFG1_TDR_AUTO_RUN_SHIFT) & DP83867_CFG1_TDR_AUTO_RUN_MASK)
1007 #define DP83867_CFG1_TDR_AUTO_RUN_GET(x) (((uint16_t)(x) & DP83867_CFG1_TDR_AUTO_RUN_MASK) >> DP83867_CFG1_TDR_AUTO_RUN_SHIFT)
1008 
1009 /* Bitfield definition for register: STS1 */
1010 /*
1011  * MASTER_SLAVE_CONFIGURATION_FAULT (RO, LH, COR)
1012  *
1013  * Master / Slave Manual Configuration Fault Detected:
1014  * 1 = Manual Master/Slave Configuration fault detected.
1015  * 0 = No Manual Master/Slave Configuration fault detected.
1016  */
1017 #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK (0x8000U)
1018 #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT (15U)
1019 #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_GET(x) (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT)
1020 
1021 /*
1022  * MASTER_SLAVE_CONFIGURATION_RESOLUTION (RO)
1023  *
1024  * Master / Slave Configuration Results:
1025  * 1 = Configuration resolved to MASTER.
1026  * 0 = Configuration resolved to SLAVE.
1027  */
1028 #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK (0x4000U)
1029 #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT (14U)
1030 #define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_GET(x) (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT)
1031 
1032 /*
1033  * LOCAL_RECEIVER_STATUS (RO)
1034  *
1035  * Local Receiver Status:
1036  * 1 = Local receiver is OK.
1037  * 0 = Local receiver is not OK.
1038  */
1039 #define DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK (0x2000U)
1040 #define DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT (13U)
1041 #define DP83867_STS1_LOCAL_RECEIVER_STATUS_GET(x) (((uint16_t)(x) & DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK) >> DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT)
1042 
1043 /*
1044  * REMOTE_RECEIVER_STATUS (RO)
1045  *
1046  * Remote Receiver Status:
1047  * 1 = Remote receiver is OK.
1048  * 0 = Remote receiver is not OK.
1049  */
1050 #define DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK (0x1000U)
1051 #define DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT (12U)
1052 #define DP83867_STS1_REMOTE_RECEIVER_STATUS_GET(x) (((uint16_t)(x) & DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK) >> DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT)
1053 
1054 /*
1055  * 1000BASE_T_FULL_DUPLEX (RO)
1056  *
1057  * Link Partner 1000BASE-T Full Duplex Capable:
1058  * 1 = Link Partner capable of 1000Base-T Full Duplex.
1059  * 0 = Link partner not capable of 1000Base-T Full Duplex.
1060  */
1061 #define DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK (0x800U)
1062 #define DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT (11U)
1063 #define DP83867_STS1_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT)
1064 
1065 /*
1066  * 1000BASE_T_HALF_DUPLEX (RO)
1067  *
1068  * Link Partner 1000BASE-T Half Duplex Capable:
1069  * 1 = Link Partner capable of 1000Base-T Half Duplex.
1070  * 0 = Link partner not capable of 1000Base-T Half Duplex.
1071  */
1072 #define DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK (0x400U)
1073 #define DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT (10U)
1074 #define DP83867_STS1_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT)
1075 
1076 /*
1077  * IDLE_ERROR_COUNTER (RO,COR)
1078  *
1079  * 1000BASE-T Idle Error Counter
1080  */
1081 #define DP83867_STS1_IDLE_ERROR_COUNTER_MASK (0xFFU)
1082 #define DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT (0U)
1083 #define DP83867_STS1_IDLE_ERROR_COUNTER_GET(x) (((uint16_t)(x) & DP83867_STS1_IDLE_ERROR_COUNTER_MASK) >> DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT)
1084 
1085 /* Bitfield definition for register: REGCR */
1086 /*
1087  * FUNCTION (RW)
1088  *
1089  * 00 = Address
1090  * 01 = Data, no post increment
1091  * 10 = Data, post increment on read and write
1092  * 11 = Data, post increment on write only
1093  */
1094 #define DP83867_REGCR_FUNCTION_MASK (0xC000U)
1095 #define DP83867_REGCR_FUNCTION_SHIFT (14U)
1096 #define DP83867_REGCR_FUNCTION_SET(x) (((uint16_t)(x) << DP83867_REGCR_FUNCTION_SHIFT) & DP83867_REGCR_FUNCTION_MASK)
1097 #define DP83867_REGCR_FUNCTION_GET(x) (((uint16_t)(x) & DP83867_REGCR_FUNCTION_MASK) >> DP83867_REGCR_FUNCTION_SHIFT)
1098 
1099 /*
1100  * DEVAD (RW)
1101  *
1102  * Device Address: In general, these bits [4:0] are the device address
1103  * DEVAD that directs any accesses of ADDAR register (0x000E) to
1104  * the appropriate MMD. Specifically, the DP83867 uses the vendor
1105  * specific DEVAD [4:0] = 11111 for accesses. All accesses through
1106  * registers REGCR and ADDAR should use this DEVAD.
1107  * Transactions with other DEVAD are ignored.
1108  */
1109 #define DP83867_REGCR_DEVAD_MASK (0x1FU)
1110 #define DP83867_REGCR_DEVAD_SHIFT (0U)
1111 #define DP83867_REGCR_DEVAD_SET(x) (((uint16_t)(x) << DP83867_REGCR_DEVAD_SHIFT) & DP83867_REGCR_DEVAD_MASK)
1112 #define DP83867_REGCR_DEVAD_GET(x) (((uint16_t)(x) & DP83867_REGCR_DEVAD_MASK) >> DP83867_REGCR_DEVAD_SHIFT)
1113 
1114 /* Bitfield definition for register: ADDAR */
1115 /*
1116  * ADDRESS_OR_DATA_REGISTER (RW)
1117  *
1118  * If REGCR register 15:14 = 00, holds the MMD DEVAD's address
1119  * register, otherwise holds the MMD DEVAD's data register
1120  */
1121 #define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK (0xFFFFU)
1122 #define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT (0U)
1123 #define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SET(x) (((uint16_t)(x) << DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK)
1124 #define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_GET(x) (((uint16_t)(x) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK) >> DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT)
1125 
1126 /* Bitfield definition for register: 1KSCR */
1127 /*
1128  * 1000BASE_X_FULL_DUPLEX (RO/P)
1129  *
1130  * 1000BASE-X Full Duplex Support:
1131  * 1 = 1000BASE-X Full Duplex is supported by the local device.
1132  * 0 = 1000BASE-X Full Duplex is not supported by the local device.
1133  */
1134 #define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK (0x8000U)
1135 #define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT (15U)
1136 #define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT)
1137 
1138 /*
1139  * 1000BASE_X_HALF_DUPLEX (RO/P)
1140  *
1141  * 1000BASE-X Half Duplex Support:
1142  * 1 = 1000BASE-X Half Duplex is supported by the local device.
1143  * 0 = 1000BASE-X Half Duplex is not supported by the local device.
1144  */
1145 #define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK (0x4000U)
1146 #define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT (14U)
1147 #define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT)
1148 
1149 /*
1150  * 1000BASE_T_FULL_DUPLEX (RO/P)
1151  *
1152  * 1000BASE-T Full Duplex Support:
1153  * 1 = 1000BASE-T Full Duplex is supported by the local device.
1154  * 0 = 1000BASE-T Full Duplex is not supported by the local device.
1155  */
1156 #define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK (0x2000U)
1157 #define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT (13U)
1158 #define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT)
1159 
1160 /*
1161  * 1000BASE_T_HALF_DUPLEX (RO/P)
1162  *
1163  * 1000BASE-T Half Duplex Support:
1164  * 1 = 1000BASE-T Half Duplex is supported by the local device.
1165  * 0 = 1000BASE-T Half Duplex is not supported by the local device.
1166  */
1167 #define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK (0x1000U)
1168 #define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT (12U)
1169 #define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT)
1170 
1171 /* Bitfield definition for register: PHYCR */
1172 /*
1173  * TX_FIFO_DEPTH (RW)
1174  *
1175  * TX FIFO Depth:
1176  * 11 = 8 bytes/nibbles (1000Mbps/Other Speeds)
1177  * 10 = 6 bytes/nibbles (1000Mbps/Other Speeds)
1178  * 01 = 4 bytes/nibbles (1000Mbps/Other Speeds)
1179  * 00 = 3 bytes/nibbles (1000Mbps/Other Speeds)
1180  * Note: FIFO is enabled only in the following modes:
1181  * 1000BaseT + GMII
1182  * 10BaseT/100BaseTX/1000BaseT + SGMII
1183  */
1184 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK (0xC000U)
1185 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT (14U)
1186 #define DP83867_PHYCR_TX_FIFO_DEPTH_SET(x) (((uint16_t)(x) << DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK)
1187 #define DP83867_PHYCR_TX_FIFO_DEPTH_GET(x) (((uint16_t)(x) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT)
1188 
1189 /*
1190  * RX_FIFO_DEPTH (RW)
1191  *
1192  * RX FIFO Depth:
1193  * 11 = 8 bytes/nibbles (1000 Mbps/Other Speeds)
1194  * 10 = 6 bytes/nibbles (1000 Mbps/Other Speeds)
1195  * 01 = 4 bytes/nibbles (1000 Mbps/Other Speeds)
1196  * 00 = 3 bytes/nibbles (1000 Mbps/Other Speeds)
1197  * Note: FIFO is enabled only in SGMII
1198  */
1199 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK (0x3000U)
1200 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT (12U)
1201 #define DP83867_PHYCR_RX_FIFO_DEPTH_SET(x) (((uint16_t)(x) << DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK)
1202 #define DP83867_PHYCR_RX_FIFO_DEPTH_GET(x) (((uint16_t)(x) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT)
1203 
1204 /*
1205  * SGMII_EN (RW)
1206  *
1207  * SGMII Enable:
1208  * 1 = Enable SGMII
1209  * 0 = Disable SGMII
1210  */
1211 #define DP83867_PHYCR_SGMII_EN_MASK (0x800U)
1212 #define DP83867_PHYCR_SGMII_EN_SHIFT (11U)
1213 #define DP83867_PHYCR_SGMII_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_SGMII_EN_SHIFT) & DP83867_PHYCR_SGMII_EN_MASK)
1214 #define DP83867_PHYCR_SGMII_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_SGMII_EN_MASK) >> DP83867_PHYCR_SGMII_EN_SHIFT)
1215 
1216 /*
1217  * FORCE_LINK_GOOD (RW)
1218  *
1219  * Force Link Good:
1220  * 1 = Force link good according to the selected speed.
1221  * 0 = Normal operation
1222  */
1223 #define DP83867_PHYCR_FORCE_LINK_GOOD_MASK (0x400U)
1224 #define DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT (10U)
1225 #define DP83867_PHYCR_FORCE_LINK_GOOD_SET(x) (((uint16_t)(x) << DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK)
1226 #define DP83867_PHYCR_FORCE_LINK_GOOD_GET(x) (((uint16_t)(x) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK) >> DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT)
1227 
1228 /*
1229  * POWER_SAVE_MODE (RW)
1230  *
1231  * Power-Saving Modes:
1232  * 11 = Passive Sleep mode: Power down all digital and analog
1233  * blocks.
1234  * 10 =Active Sleep mode: Power down all digital and analog blocks.
1235  * Automatic power-up is performed when link partner is detected. Link
1236  * pulses are transmitted approximately once per 1.4 Sec in this mode
1237  * to wake up any potential link partner.
1238  * 01 = IEEE mode: power down all digital and analog blocks.
1239  * Note: If DISABLE_CLK_125 (bit [4]of this register) is set to zero, the
1240  * PLL is also powered down.
1241  * 00 = Normal mode
1242  */
1243 #define DP83867_PHYCR_POWER_SAVE_MODE_MASK (0x300U)
1244 #define DP83867_PHYCR_POWER_SAVE_MODE_SHIFT (8U)
1245 #define DP83867_PHYCR_POWER_SAVE_MODE_SET(x) (((uint16_t)(x) << DP83867_PHYCR_POWER_SAVE_MODE_SHIFT) & DP83867_PHYCR_POWER_SAVE_MODE_MASK)
1246 #define DP83867_PHYCR_POWER_SAVE_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYCR_POWER_SAVE_MODE_MASK) >> DP83867_PHYCR_POWER_SAVE_MODE_SHIFT)
1247 
1248 /*
1249  * DEEP_POWER_DOWN_EN (RW)
1250  *
1251  * Deep power-down mode enable
1252  * 1 = When power down is initiated through assertion of the external
1253  * power-down pin or through the POWER_DOWN bit in the BMCR,
1254  * the device enters a deep power-down mode.
1255  * 0 = Normal operation.
1256  */
1257 #define DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK (0x80U)
1258 #define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT (7U)
1259 #define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK)
1260 #define DP83867_PHYCR_DEEP_POWER_DOWN_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK) >> DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT)
1261 
1262 /*
1263  * MDI_CROSSOVER (RW)
1264  *
1265  * MDI Crosssover Mode:
1266  * 1x = Enable automatic crossover
1267  * 01 = Manual MDI-X configuration
1268  * 00 = Manual MDI configuration
1269  */
1270 #define DP83867_PHYCR_MDI_CROSSOVER_MASK (0x60U)
1271 #define DP83867_PHYCR_MDI_CROSSOVER_SHIFT (5U)
1272 #define DP83867_PHYCR_MDI_CROSSOVER_SET(x) (((uint16_t)(x) << DP83867_PHYCR_MDI_CROSSOVER_SHIFT) & DP83867_PHYCR_MDI_CROSSOVER_MASK)
1273 #define DP83867_PHYCR_MDI_CROSSOVER_GET(x) (((uint16_t)(x) & DP83867_PHYCR_MDI_CROSSOVER_MASK) >> DP83867_PHYCR_MDI_CROSSOVER_SHIFT)
1274 
1275 /*
1276  * DISABLE_CLK_125 (RW)
1277  *
1278  * Disable 125MHz Clock:
1279  * This bit may be used in conjunction with POWER_SAVE_MODE
1280  * (bits 9:8 of this register).
1281  * 1 = Disable CLK125.
1282  * 0 = Enable CLK125.
1283  */
1284 #define DP83867_PHYCR_DISABLE_CLK_125_MASK (0x10U)
1285 #define DP83867_PHYCR_DISABLE_CLK_125_SHIFT (4U)
1286 #define DP83867_PHYCR_DISABLE_CLK_125_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DISABLE_CLK_125_SHIFT) & DP83867_PHYCR_DISABLE_CLK_125_MASK)
1287 #define DP83867_PHYCR_DISABLE_CLK_125_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DISABLE_CLK_125_MASK) >> DP83867_PHYCR_DISABLE_CLK_125_SHIFT)
1288 
1289 /*
1290  * STANDBY_MODE (RW)
1291  *
1292  * Standby Mode:
1293  * 1 = Enable standby mode. Digital and analog circuitry are powered
1294  * up, but no link can be established.
1295  * 0 = Normal operation.
1296  */
1297 #define DP83867_PHYCR_STANDBY_MODE_MASK (0x4U)
1298 #define DP83867_PHYCR_STANDBY_MODE_SHIFT (2U)
1299 #define DP83867_PHYCR_STANDBY_MODE_SET(x) (((uint16_t)(x) << DP83867_PHYCR_STANDBY_MODE_SHIFT) & DP83867_PHYCR_STANDBY_MODE_MASK)
1300 #define DP83867_PHYCR_STANDBY_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYCR_STANDBY_MODE_MASK) >> DP83867_PHYCR_STANDBY_MODE_SHIFT)
1301 
1302 /*
1303  * LINE_DRIVER_INV_EN (RW)
1304  *
1305  * Line Driver Inversion Enable:
1306  * 1 = Invert Line Driver Transmission.
1307  * 0 = Normal operation.
1308  */
1309 #define DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK (0x2U)
1310 #define DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT (1U)
1311 #define DP83867_PHYCR_LINE_DRIVER_INV_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK)
1312 #define DP83867_PHYCR_LINE_DRIVER_INV_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK) >> DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT)
1313 
1314 /*
1315  * DISABLE_JABBER (RW)
1316  *
1317  * Disable Jabber
1318  * 1 = Disable Jabber function.
1319  * 0 = Enable Jabber function.
1320  */
1321 #define DP83867_PHYCR_DISABLE_JABBER_MASK (0x1U)
1322 #define DP83867_PHYCR_DISABLE_JABBER_SHIFT (0U)
1323 #define DP83867_PHYCR_DISABLE_JABBER_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DISABLE_JABBER_SHIFT) & DP83867_PHYCR_DISABLE_JABBER_MASK)
1324 #define DP83867_PHYCR_DISABLE_JABBER_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DISABLE_JABBER_MASK) >> DP83867_PHYCR_DISABLE_JABBER_SHIFT)
1325 
1326 /* Bitfield definition for register: PHYSTS */
1327 /*
1328  * SPEED_SELECTION (RO)
1329  *
1330  * Speed Select Status:
1331  * These two bits indicate the speed of operation as determined by
1332  * Auto-Negotiation or as set by manual configuration.
1333  * 11 = Reserved
1334  * 10 = 1000 Mbps
1335  * 01 = 100 Mbps
1336  * 00 = 10 Mbps
1337  */
1338 #define DP83867_PHYSTS_SPEED_SELECTION_MASK (0xC000U)
1339 #define DP83867_PHYSTS_SPEED_SELECTION_SHIFT (14U)
1340 #define DP83867_PHYSTS_SPEED_SELECTION_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_SELECTION_MASK) >> DP83867_PHYSTS_SPEED_SELECTION_SHIFT)
1341 
1342 /*
1343  * DUPLEX_MODE (RO)
1344  *
1345  * Duplex Mode Status:
1346  * 1 = Full Duplex
1347  * 0 = Half Duplex.
1348  */
1349 #define DP83867_PHYSTS_DUPLEX_MODE_MASK (0x2000U)
1350 #define DP83867_PHYSTS_DUPLEX_MODE_SHIFT (13U)
1351 #define DP83867_PHYSTS_DUPLEX_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_DUPLEX_MODE_MASK) >> DP83867_PHYSTS_DUPLEX_MODE_SHIFT)
1352 
1353 /*
1354  * PAGE_RECEIVED ( RO, LH, COR)
1355  *
1356  * Page Received:
1357  * This bit is latched high and will be cleared upon a read.
1358  * 1 = Page received.
1359  * 0 = No page received.
1360  */
1361 #define DP83867_PHYSTS_PAGE_RECEIVED_MASK (0x1000U)
1362 #define DP83867_PHYSTS_PAGE_RECEIVED_SHIFT (12U)
1363 #define DP83867_PHYSTS_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_PAGE_RECEIVED_MASK) >> DP83867_PHYSTS_PAGE_RECEIVED_SHIFT)
1364 
1365 /*
1366  * SPEED_DUPLEX_RESOLVED (RO)
1367  *
1368  * Speed Duplex Resolution Status:
1369  * 1 = Auto-Negotiation has completed or is disabled.
1370  * 0 = Auto-Negotiation is enabled and has not completed.
1371  */
1372 #define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK (0x800U)
1373 #define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT (11U)
1374 #define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK) >> DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT)
1375 
1376 /*
1377  * LINK_STATUS (RO)
1378  *
1379  * Link Status:
1380  * 1 = Link is up.
1381  * 0 = Link is down.
1382  */
1383 #define DP83867_PHYSTS_LINK_STATUS_MASK (0x400U)
1384 #define DP83867_PHYSTS_LINK_STATUS_SHIFT (10U)
1385 #define DP83867_PHYSTS_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_LINK_STATUS_MASK) >> DP83867_PHYSTS_LINK_STATUS_SHIFT)
1386 
1387 /*
1388  * MDI_X_MODE_CD (RO)
1389  *
1390  * MDI/MDIX Resolution Status for C and D Line Driver Pairs:
1391  * 1 = Resolved as MDIX
1392  * 0 = Resolved as MDI.
1393  */
1394 #define DP83867_PHYSTS_MDI_X_MODE_CD_MASK (0x200U)
1395 #define DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT (9U)
1396 #define DP83867_PHYSTS_MDI_X_MODE_CD_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_CD_MASK) >> DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT)
1397 
1398 /*
1399  * MDI_X_MODE_AB (RO)
1400  *
1401  * MDI/MDIX Resolution Status for A and B Line Driver Pairs:
1402  * 1 = Resolved as MDIX
1403  * 0 = Resolved as MDI.
1404  */
1405 #define DP83867_PHYSTS_MDI_X_MODE_AB_MASK (0x100U)
1406 #define DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT (8U)
1407 #define DP83867_PHYSTS_MDI_X_MODE_AB_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_AB_MASK) >> DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT)
1408 
1409 /*
1410  * SPEED_OPT_STATUS (RO)
1411  *
1412  * Speed Optimization Status:
1413  * 1 = Auto-Negotiation is currently being performed with Speed
1414  * Optimization masking 1000BaseT abilities (Valid only during Auto-
1415  * Negotiation).
1416  * 0 = Auto-Negotiation is currently being performed without Speed
1417  * Optimization.
1418  */
1419 #define DP83867_PHYSTS_SPEED_OPT_STATUS_MASK (0x80U)
1420 #define DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT (7U)
1421 #define DP83867_PHYSTS_SPEED_OPT_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_OPT_STATUS_MASK) >> DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT)
1422 
1423 /*
1424  * SLEEP_MODE (RO)
1425  *
1426  * Sleep Mode Status:
1427  * 1 = Device currently in sleep mode.
1428  * 0 = Device currently in active mode.
1429  */
1430 #define DP83867_PHYSTS_SLEEP_MODE_MASK (0x40U)
1431 #define DP83867_PHYSTS_SLEEP_MODE_SHIFT (6U)
1432 #define DP83867_PHYSTS_SLEEP_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SLEEP_MODE_MASK) >> DP83867_PHYSTS_SLEEP_MODE_SHIFT)
1433 
1434 /*
1435  * WIRE_CROSS (RO)
1436  *
1437  * Crossed Wire Indication:
1438  * Indicates channel polarity in 1000BASE-T linked status. Bits [5:2]
1439  * correspond to channels [D,C,B,A], respectively.
1440  * 1 = Channel polarity is reversed.
1441  * 0 = Channel polarity is normal.
1442  */
1443 #define DP83867_PHYSTS_WIRE_CROSS_MASK (0x3CU)
1444 #define DP83867_PHYSTS_WIRE_CROSS_SHIFT (2U)
1445 #define DP83867_PHYSTS_WIRE_CROSS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_WIRE_CROSS_MASK) >> DP83867_PHYSTS_WIRE_CROSS_SHIFT)
1446 
1447 /*
1448  * POLARITY_STATUS (RO)
1449  *
1450  * 10BASE-Te Polarity Status:
1451  * 1 = Correct Polarity detected.
1452  * 0 = Inverted Polarity detected.
1453  */
1454 #define DP83867_PHYSTS_POLARITY_STATUS_MASK (0x2U)
1455 #define DP83867_PHYSTS_POLARITY_STATUS_SHIFT (1U)
1456 #define DP83867_PHYSTS_POLARITY_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_POLARITY_STATUS_MASK) >> DP83867_PHYSTS_POLARITY_STATUS_SHIFT)
1457 
1458 /*
1459  * JABBER_DETECT (RO)
1460  *
1461  * Jabber Detect: This bit only has meaning in 10 Mbps mode.
1462  * This bit is a duplicate of the Jabber Detect bit in the BMSR register,
1463  * except that it is not cleared upon a read of the PHYSTS register.
1464  * 1 = Jabber condition detected.
1465  * 0 = No Jabber.
1466  */
1467 #define DP83867_PHYSTS_JABBER_DETECT_MASK (0x1U)
1468 #define DP83867_PHYSTS_JABBER_DETECT_SHIFT (0U)
1469 #define DP83867_PHYSTS_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_JABBER_DETECT_MASK) >> DP83867_PHYSTS_JABBER_DETECT_SHIFT)
1470 
1471 /* Bitfield definition for register: MICR */
1472 /*
1473  * AUTONEG_ERR_INT_EN (RW)
1474  *
1475  * Enable Auto-Negotiation Error Interrupt:
1476  * 1 = Enable Auto-Negotiation Error interrupt.
1477  * 0 = Disable Auto-Negotiation Error interrupt.
1478  */
1479 #define DP83867_MICR_AUTONEG_ERR_INT_EN_MASK (0x8000U)
1480 #define DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT (15U)
1481 #define DP83867_MICR_AUTONEG_ERR_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK)
1482 #define DP83867_MICR_AUTONEG_ERR_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK) >> DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT)
1483 
1484 /*
1485  * SPEED_CHNG_INT_EN (RW)
1486  *
1487  * Enable Speed Change Interrupt:
1488  * 1 = Enable Speed Change interrupt.
1489  * 0 = Disable Speed Change interrupt.
1490  */
1491 #define DP83867_MICR_SPEED_CHNG_INT_EN_MASK (0x4000U)
1492 #define DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT (14U)
1493 #define DP83867_MICR_SPEED_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK)
1494 #define DP83867_MICR_SPEED_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK) >> DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT)
1495 
1496 /*
1497  * DUPLEX_MODE_CHNG_INT_EN (RW)
1498  *
1499  * Enable Duplex Mode Change Interrupt:
1500  * 1 = Enable Duplex Mode Change interrupt.
1501  * 0 = Disable Duplex Mode Change interrupt.
1502  */
1503 #define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK (0x2000U)
1504 #define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT (13U)
1505 #define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK)
1506 #define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT)
1507 
1508 /*
1509  * PAGE_RECEIVED_INT_EN (RW)
1510  *
1511  * Enable Page Received Interrupt:
1512  * 1 = Enable Page Received Interrupt.
1513  * 0 = Disable Page Received Interrupt.
1514  */
1515 #define DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK (0x1000U)
1516 #define DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT (12U)
1517 #define DP83867_MICR_PAGE_RECEIVED_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK)
1518 #define DP83867_MICR_PAGE_RECEIVED_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK) >> DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT)
1519 
1520 /*
1521  * AUTONEG_COMP_INT_EN (RW)
1522  *
1523  * Enable Auto-Negotiation Complete Interrupt:
1524  * 1 = Enable Auto-Negotiation Complete Interrupt.
1525  * 0 = Disable Auto-Negotiation Complete Interrupt.
1526  */
1527 #define DP83867_MICR_AUTONEG_COMP_INT_EN_MASK (0x800U)
1528 #define DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT (11U)
1529 #define DP83867_MICR_AUTONEG_COMP_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK)
1530 #define DP83867_MICR_AUTONEG_COMP_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK) >> DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT)
1531 
1532 /*
1533  * LINK_STATUS_CHNG_INT_EN (RW)
1534  *
1535  * Enable Link Status Change Interrupt:
1536  * 1 = Enable Link Status Change interrupt.
1537  * 0 = Disable Link Status Change interrupt.
1538  */
1539 #define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK (0x400U)
1540 #define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT (10U)
1541 #define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK)
1542 #define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK) >> DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT)
1543 
1544 /*
1545  * FALSE_CARRIER_INT_EN (RW)
1546  *
1547  * Enable False Carrier Interrupt:
1548  * 1 = Enable False Carrier interrupt.
1549  * 0 = Disable False Carrier interrupt.
1550  */
1551 #define DP83867_MICR_FALSE_CARRIER_INT_EN_MASK (0x100U)
1552 #define DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT (8U)
1553 #define DP83867_MICR_FALSE_CARRIER_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK)
1554 #define DP83867_MICR_FALSE_CARRIER_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK) >> DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT)
1555 
1556 /*
1557  * MDI_CROSSOVER_CHNG_INT_EN (RW)
1558  *
1559  * Enable MDI Crossover Change Interrupt:
1560  * 1 = Enable MDI Crossover Change interrupt.
1561  * 0 = Disable MDI Crossover Change interrupt.
1562  */
1563 #define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK (0x40U)
1564 #define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT (6U)
1565 #define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK)
1566 #define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK) >> DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT)
1567 
1568 /*
1569  * SPEED_OPT_EVENT_INT_EN (RW)
1570  *
1571  * Enable Speed Optimization Event Interrupt:
1572  * 1 = Enable Speed Optimization Event Interrupt.
1573  * 0 = Disable Speed Optimization Event Interrupt.
1574  */
1575 #define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK (0x20U)
1576 #define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT (5U)
1577 #define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK)
1578 #define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK) >> DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT)
1579 
1580 /*
1581  * SLEEP_MODE_CHNG_INT_EN (RW)
1582  *
1583  * Enable Sleep Mode Change Interrupt:
1584  * 1 = Enable Sleep Mode Change Interrupt.
1585  * 0 = Disable Sleep Mode Change Interrupt.
1586  */
1587 #define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK (0x10U)
1588 #define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT (4U)
1589 #define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK)
1590 #define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT)
1591 
1592 /*
1593  * WOL_INT_EN (RW)
1594  *
1595  * Enable Wake-on-LAN Interrupt:
1596  * 1 = Enable Wake-on-LAN Interrupt.
1597  * 0 = Disable Wake-on-LAN Interrupt.
1598  */
1599 #define DP83867_MICR_WOL_INT_EN_MASK (0x8U)
1600 #define DP83867_MICR_WOL_INT_EN_SHIFT (3U)
1601 #define DP83867_MICR_WOL_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_WOL_INT_EN_SHIFT) & DP83867_MICR_WOL_INT_EN_MASK)
1602 #define DP83867_MICR_WOL_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_WOL_INT_EN_MASK) >> DP83867_MICR_WOL_INT_EN_SHIFT)
1603 
1604 /*
1605  * XGMII_ERR_INT_EN (RW)
1606  *
1607  * Enable xGMII Error Interrupt:
1608  * 1 = Enable xGMII Error Interrupt.
1609  * 0 = Disable xGMII Error Interrupt.
1610  */
1611 #define DP83867_MICR_XGMII_ERR_INT_EN_MASK (0x4U)
1612 #define DP83867_MICR_XGMII_ERR_INT_EN_SHIFT (2U)
1613 #define DP83867_MICR_XGMII_ERR_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_XGMII_ERR_INT_EN_SHIFT) & DP83867_MICR_XGMII_ERR_INT_EN_MASK)
1614 #define DP83867_MICR_XGMII_ERR_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_XGMII_ERR_INT_EN_MASK) >> DP83867_MICR_XGMII_ERR_INT_EN_SHIFT)
1615 
1616 /*
1617  * POLARITY_CHNG_INT_EN (RW)
1618  *
1619  * Enable Polarity Change Interrupt:
1620  * 1 = Enable Polarity Change interrupt.
1621  * 0 = Disable Polarity Change interrupt.
1622  */
1623 #define DP83867_MICR_POLARITY_CHNG_INT_EN_MASK (0x2U)
1624 #define DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT (1U)
1625 #define DP83867_MICR_POLARITY_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK)
1626 #define DP83867_MICR_POLARITY_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK) >> DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT)
1627 
1628 /*
1629  * JABBER_INT_EN (RW)
1630  *
1631  * Enable Jabber Interrupt:
1632  * 1 = Enable Jabber interrupt.
1633  * 0 = Disable Jabber interrupt.
1634  */
1635 #define DP83867_MICR_JABBER_INT_EN_MASK (0x1U)
1636 #define DP83867_MICR_JABBER_INT_EN_SHIFT (0U)
1637 #define DP83867_MICR_JABBER_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_JABBER_INT_EN_SHIFT) & DP83867_MICR_JABBER_INT_EN_MASK)
1638 #define DP83867_MICR_JABBER_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_JABBER_INT_EN_MASK) >> DP83867_MICR_JABBER_INT_EN_SHIFT)
1639 
1640 /* Bitfield definition for register: ISR */
1641 /*
1642  * AUTONEG_ERR_INT (RO, LH, COR)
1643  *
1644  * Auto-Negotiation Error Interrupt:
1645  * 1 = Auto-Negotiation Error interrupt is pending and is cleared by the
1646  * current read.
1647  * 0 = No Auto-Negotiation Error interrupt.
1648  */
1649 #define DP83867_ISR_AUTONEG_ERR_INT_MASK (0x8000U)
1650 #define DP83867_ISR_AUTONEG_ERR_INT_SHIFT (15U)
1651 #define DP83867_ISR_AUTONEG_ERR_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_AUTONEG_ERR_INT_MASK) >> DP83867_ISR_AUTONEG_ERR_INT_SHIFT)
1652 
1653 /*
1654  * SPEED_CHNG_INT (RO, LH, COR)
1655  *
1656  * Speed Change Interrupt:
1657  * 1 = Speed Change interrupt is pending and is cleared by the current
1658  * read.
1659  * 0 = No Speed Change interrupt.
1660  */
1661 #define DP83867_ISR_SPEED_CHNG_INT_MASK (0x4000U)
1662 #define DP83867_ISR_SPEED_CHNG_INT_SHIFT (14U)
1663 #define DP83867_ISR_SPEED_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SPEED_CHNG_INT_MASK) >> DP83867_ISR_SPEED_CHNG_INT_SHIFT)
1664 
1665 /*
1666  * DUPLEX_MODE_CHNG_INT (RO, LH, COR)
1667  *
1668  * Duplex Mode Change Interrupt:
1669  * 1 = Duplex Mode Change interrupt is pending and is cleared by the
1670  * current read.
1671  * 0 = No Duplex Mode Change interrupt.
1672  */
1673 #define DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK (0x2000U)
1674 #define DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT (13U)
1675 #define DP83867_ISR_DUPLEX_MODE_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK) >> DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT)
1676 
1677 /*
1678  * PAGE_RECEIVED_INT (RO, LH, COR)
1679  *
1680  * Page Received Interrupt:
1681  * 1 = Page Received Interrupt is pending and is cleared by the
1682  * current read.
1683  * 0 = No Page Received Interrupt is pending.
1684  */
1685 #define DP83867_ISR_PAGE_RECEIVED_INT_MASK (0x1000U)
1686 #define DP83867_ISR_PAGE_RECEIVED_INT_SHIFT (12U)
1687 #define DP83867_ISR_PAGE_RECEIVED_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_PAGE_RECEIVED_INT_MASK) >> DP83867_ISR_PAGE_RECEIVED_INT_SHIFT)
1688 
1689 /*
1690  * AUTONEG_COMP_INT (RO, LH, COR)
1691  *
1692  * Auto-Negotiation Complete Interrupt:
1693  * 1 = Auto-Negotiation Complete Interrupt is pending and is cleared
1694  * by the current read.
1695  * 0 = No Auto-Negotiation Complete Interrupt is pending.
1696  */
1697 #define DP83867_ISR_AUTONEG_COMP_INT_MASK (0x800U)
1698 #define DP83867_ISR_AUTONEG_COMP_INT_SHIFT (11U)
1699 #define DP83867_ISR_AUTONEG_COMP_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_AUTONEG_COMP_INT_MASK) >> DP83867_ISR_AUTONEG_COMP_INT_SHIFT)
1700 
1701 /*
1702  * LINK_STATUS_CHNG_INT (RO, LH, COR)
1703  *
1704  * Link Status Change Interrupt:
1705  * 1 = Link Status Change interrupt is pending and is cleared by the
1706  * current read.
1707  * 0 = No Link Status Change interrupt is pending.
1708  */
1709 #define DP83867_ISR_LINK_STATUS_CHNG_INT_MASK (0x400U)
1710 #define DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT (10U)
1711 #define DP83867_ISR_LINK_STATUS_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_LINK_STATUS_CHNG_INT_MASK) >> DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT)
1712 
1713 /*
1714  * FALSE_CARRIER_INT ( RO, LH, COR)
1715  *
1716  * False Carrier Interrupt:
1717  * 1 = False Carrier interrupt is pending and is cleared by the current
1718  * read.
1719  * 0 = No False Carrier interrupt is pending.
1720  */
1721 #define DP83867_ISR_FALSE_CARRIER_INT_MASK (0x100U)
1722 #define DP83867_ISR_FALSE_CARRIER_INT_SHIFT (8U)
1723 #define DP83867_ISR_FALSE_CARRIER_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_FALSE_CARRIER_INT_MASK) >> DP83867_ISR_FALSE_CARRIER_INT_SHIFT)
1724 
1725 /*
1726  * MDI_CROSSOVER_CHNG_INT (RO, LH, COR)
1727  *
1728  * MDI Crossover Change Interrupt:
1729  * 1 = MDI Crossover Change interrupt is pending and is cleared by
1730  * the current read.
1731  * 0 = No MDI Crossover Change interrupt is pending.
1732  */
1733 #define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK (0x40U)
1734 #define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT (6U)
1735 #define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK) >> DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT)
1736 
1737 /*
1738  * SPEED_OPT_EVENT_INT (RO, LH, COR)
1739  *
1740  * Speed Optimization Event Interrupt:
1741  * 1 = Speed Optimization Event Interrupt is pending and is cleared by
1742  * the current read.
1743  * 0 = No Speed Optimization Event Interrupt is pending.
1744  */
1745 #define DP83867_ISR_SPEED_OPT_EVENT_INT_MASK (0x20U)
1746 #define DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT (5U)
1747 #define DP83867_ISR_SPEED_OPT_EVENT_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SPEED_OPT_EVENT_INT_MASK) >> DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT)
1748 
1749 /*
1750  * SLEEP_MODE_CHNG_INT (RO, LH, COR)
1751  *
1752  * Sleep Mode Change Interrupt:
1753  * 1 = Sleep Mode Change Interrupt is pending and is cleared by the
1754  * current read.
1755  * 0 = No Sleep Mode Change Interrupt is pending.
1756  */
1757 #define DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK (0x10U)
1758 #define DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT (4U)
1759 #define DP83867_ISR_SLEEP_MODE_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK) >> DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT)
1760 
1761 /*
1762  * WOL_INT (RO, LH, COR)
1763  *
1764  * Wake-on-LAN Interrupt:
1765  * 1 = Wake-on-LAN Interrupt is pending.
1766  * 0 = No Wake-on-LAN Interrupt is pending.
1767  */
1768 #define DP83867_ISR_WOL_INT_MASK (0x8U)
1769 #define DP83867_ISR_WOL_INT_SHIFT (3U)
1770 #define DP83867_ISR_WOL_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_WOL_INT_MASK) >> DP83867_ISR_WOL_INT_SHIFT)
1771 
1772 /*
1773  * XGMII_ERR_INT (RO, LH, COR)
1774  *
1775  * xGMII Error Interrupt:
1776  * 1 = xGMII Error Interrupt is pending and is cleared by the current
1777  * read.
1778  * 0 = No xGMII Error Interrupt is pending.
1779  */
1780 #define DP83867_ISR_XGMII_ERR_INT_MASK (0x4U)
1781 #define DP83867_ISR_XGMII_ERR_INT_SHIFT (2U)
1782 #define DP83867_ISR_XGMII_ERR_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_XGMII_ERR_INT_MASK) >> DP83867_ISR_XGMII_ERR_INT_SHIFT)
1783 
1784 /*
1785  * POLARITY_CHNG_INT (RO, LH, COR)
1786  *
1787  * Polarity Change Interrupt:
1788  * 1 = Polarity Change interrupt is pending and is cleared by the
1789  * current read.
1790  * 0 = No Polarity Change interrupt is pending.
1791  */
1792 #define DP83867_ISR_POLARITY_CHNG_INT_MASK (0x2U)
1793 #define DP83867_ISR_POLARITY_CHNG_INT_SHIFT (1U)
1794 #define DP83867_ISR_POLARITY_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_POLARITY_CHNG_INT_MASK) >> DP83867_ISR_POLARITY_CHNG_INT_SHIFT)
1795 
1796 /*
1797  * JABBER_INT (RO, LH, COR)
1798  *
1799  * Jabber Interrupt:
1800  * 1 = Jabber interrupt is pending and is cleared by the current read.
1801  * 0 = No Jabber interrupt is pending.
1802  */
1803 #define DP83867_ISR_JABBER_INT_MASK (0x1U)
1804 #define DP83867_ISR_JABBER_INT_SHIFT (0U)
1805 #define DP83867_ISR_JABBER_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_JABBER_INT_MASK) >> DP83867_ISR_JABBER_INT_SHIFT)
1806 
1807 /* Bitfield definition for register: CRG2 */
1808 /*
1809  * INTERRUPT_POLARITY (RW)
1810  *
1811  * Configure Interrupt Polarity:
1812  * 1 = Interrupt pin is active low.
1813  * 0 = Interrupt pin is active high.
1814  */
1815 #define DP83867_CRG2_INTERRUPT_POLARITY_MASK (0x2000U)
1816 #define DP83867_CRG2_INTERRUPT_POLARITY_SHIFT (13U)
1817 #define DP83867_CRG2_INTERRUPT_POLARITY_SET(x) (((uint16_t)(x) << DP83867_CRG2_INTERRUPT_POLARITY_SHIFT) & DP83867_CRG2_INTERRUPT_POLARITY_MASK)
1818 #define DP83867_CRG2_INTERRUPT_POLARITY_GET(x) (((uint16_t)(x) & DP83867_CRG2_INTERRUPT_POLARITY_MASK) >> DP83867_CRG2_INTERRUPT_POLARITY_SHIFT)
1819 
1820 /*
1821  * SPEED_OPT_ATTEMPT_CNT (RO)
1822  *
1823  * Speed Optimization Attempt Count:
1824  * Selects the number of 1000BASE-T link establishment attempt
1825  * failures prior to performing Speed Optimization.
1826  * 11 = 8
1827  * 10 = 4
1828  * 01 = 2
1829  * 00 = 1
1830  */
1831 #define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK (0xC00U)
1832 #define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT (10U)
1833 #define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK) >> DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT)
1834 
1835 /*
1836  * SPEED_OPT_EN (RW)
1837  *
1838  * Speed Optimization Enable:
1839  * 1 = Enable Speed Optimization.
1840  * 0 = Disable Speed Optimization.
1841  */
1842 #define DP83867_CRG2_SPEED_OPT_EN_MASK (0x200U)
1843 #define DP83867_CRG2_SPEED_OPT_EN_SHIFT (9U)
1844 #define DP83867_CRG2_SPEED_OPT_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_EN_MASK)
1845 #define DP83867_CRG2_SPEED_OPT_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_EN_MASK) >> DP83867_CRG2_SPEED_OPT_EN_SHIFT)
1846 
1847 /*
1848  * SPEED_OPT_ENHANCED_EN (RW)
1849  *
1850  * Speed Optimization Enhanced Mode Enable:
1851  * In enhanced mode, speed is optimized if energy is not detected in
1852  * channels C and D.
1853  * 1 = Enable Speed Optimization enhanced mode.
1854  * 0 = Disable Speed Optimization enhanced mode.
1855  */
1856 #define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK (0x100U)
1857 #define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT (8U)
1858 #define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK)
1859 #define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK) >> DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT)
1860 
1861 /*
1862  * SGMII_AUTONEG_EN (RW)
1863  *
1864  * SGMII Auto-Negotiation Enable:
1865  * 1 = Enable SGMII Auto-Negotaition.
1866  * 0 = Disable SGMII Auto-Negotaition.
1867  */
1868 #define DP83867_CRG2_SGMII_AUTONEG_EN_MASK (0x80U)
1869 #define DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT (7U)
1870 #define DP83867_CRG2_SGMII_AUTONEG_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK)
1871 #define DP83867_CRG2_SGMII_AUTONEG_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK) >> DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT)
1872 
1873 /*
1874  * SPEED_OPT_10M_EN (RW)
1875  *
1876  * Enable Speed Optimization to 10BASE-Te:
1877  * 1 = Enable speed optimization to 10BASE-Te if link establishment
1878  * fails in 1000BASE-T and 100BASE-TX .
1879  * 0 = Disable speed optimization to 10BASE-Te.
1880  */
1881 #define DP83867_CRG2_SPEED_OPT_10M_EN_MASK (0x40U)
1882 #define DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT (6U)
1883 #define DP83867_CRG2_SPEED_OPT_10M_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK)
1884 #define DP83867_CRG2_SPEED_OPT_10M_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK) >> DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT)
1885 
1886 /* Bitfield definition for register: RECR */
1887 /*
1888  * RXERCNT_15_0 (RO, WSC)
1889  *
1890  * RX_ER Counter:
1891  * Receive error counter. This register saturates at the maximum value
1892  * of 0xFFFF. It is cleared by dummy write to this register.
1893  */
1894 #define DP83867_RECR_RXERCNT_15_0_MASK (0xFFFFU)
1895 #define DP83867_RECR_RXERCNT_15_0_SHIFT (0U)
1896 #define DP83867_RECR_RXERCNT_15_0_SET(x) (((uint16_t)(x) << DP83867_RECR_RXERCNT_15_0_SHIFT) & DP83867_RECR_RXERCNT_15_0_MASK)
1897 #define DP83867_RECR_RXERCNT_15_0_GET(x) (((uint16_t)(x) & DP83867_RECR_RXERCNT_15_0_MASK) >> DP83867_RECR_RXERCNT_15_0_SHIFT)
1898 
1899 /* Bitfield definition for register: STS2 */
1900 /*
1901  * PRBS_LOCK (RO)
1902  *
1903  * PRBS Lock Status:
1904  * 1 = PRBS checker is locked to the received byte stream.
1905  * 0 = PRBS checker is not locked.
1906  */
1907 #define DP83867_STS2_PRBS_LOCK_MASK (0x800U)
1908 #define DP83867_STS2_PRBS_LOCK_SHIFT (11U)
1909 #define DP83867_STS2_PRBS_LOCK_GET(x) (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_MASK) >> DP83867_STS2_PRBS_LOCK_SHIFT)
1910 
1911 /*
1912  * PRBS_LOCK_LOST (RO, LH, COR)
1913  *
1914  * PRBS Lock Lost:
1915  * 1 = PRBS checker has lost lock.
1916  * 0 = PRBS checker has not lost lock.
1917  */
1918 #define DP83867_STS2_PRBS_LOCK_LOST_MASK (0x400U)
1919 #define DP83867_STS2_PRBS_LOCK_LOST_SHIFT (10U)
1920 #define DP83867_STS2_PRBS_LOCK_LOST_GET(x) (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_LOST_MASK) >> DP83867_STS2_PRBS_LOCK_LOST_SHIFT)
1921 
1922 /*
1923  * PKT_GEN_BUSY (RO)
1924  *
1925  * Packet Generator Busy:
1926  * 1 = Packet generation is in process.
1927  * 0 = Packet generation is not in process.
1928  */
1929 #define DP83867_STS2_PKT_GEN_BUSY_MASK (0x200U)
1930 #define DP83867_STS2_PKT_GEN_BUSY_SHIFT (9U)
1931 #define DP83867_STS2_PKT_GEN_BUSY_GET(x) (((uint16_t)(x) & DP83867_STS2_PKT_GEN_BUSY_MASK) >> DP83867_STS2_PKT_GEN_BUSY_SHIFT)
1932 
1933 /*
1934  * SCR_MODE_MASTER_1G (RO)
1935  *
1936  * Gigabit Master Scramble Mode:
1937  * 1 = 1G PCS (master) is in legacy encoding mode.
1938  * 0 = 1G PCS (master) is in normal encoding mode..
1939  */
1940 #define DP83867_STS2_SCR_MODE_MASTER_1G_MASK (0x100U)
1941 #define DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT (8U)
1942 #define DP83867_STS2_SCR_MODE_MASTER_1G_GET(x) (((uint16_t)(x) & DP83867_STS2_SCR_MODE_MASTER_1G_MASK) >> DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT)
1943 
1944 /*
1945  * SCR_MODE_SLAVE_1G (RO)
1946  *
1947  * Gigabit Slave Scramble Mode:
1948  * 1 = 1G PCS (slave) is in legacy encoding mode.
1949  * 0 = 1G PCS (slave) is in normal encoding mode..
1950  */
1951 #define DP83867_STS2_SCR_MODE_SLAVE_1G_MASK (0x80U)
1952 #define DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT (7U)
1953 #define DP83867_STS2_SCR_MODE_SLAVE_1G_GET(x) (((uint16_t)(x) & DP83867_STS2_SCR_MODE_SLAVE_1G_MASK) >> DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT)
1954 
1955 /*
1956  * CORE_PWR_MODE (RO)
1957  *
1958  * Core Power Mode:
1959  * 1 = Core is in normal power mode.
1960  * 0 = Core is power-down mode or in sleep mode.
1961  */
1962 #define DP83867_STS2_CORE_PWR_MODE_MASK (0x40U)
1963 #define DP83867_STS2_CORE_PWR_MODE_SHIFT (6U)
1964 #define DP83867_STS2_CORE_PWR_MODE_GET(x) (((uint16_t)(x) & DP83867_STS2_CORE_PWR_MODE_MASK) >> DP83867_STS2_CORE_PWR_MODE_SHIFT)
1965 
1966 /* Bitfield definition for register: LEDCR1 */
1967 /*
1968  * LED_GPIO_SEL (RW)
1969  *
1970  * Source of the GPIO LED_3:
1971  * 1111: Reserved
1972  * 1110: Receive Error
1973  * 1101: Receive Error or Transmit Error
1974  * 1100: RESERVED
1975  * 1011: Link established, blink for transmit or receive activity
1976  * 1010: Full duplex
1977  * 1001: 100/1000BT link established
1978  * 1000: 10/100BT link established
1979  * 0111: 10BT link established
1980  * 0110: 100 BTX link established
1981  * 0101: 1000BT link established
1982  * 0100: Collision detected
1983  * 0011: Receive activity
1984  * 0010: Transmit activity
1985  * 0001: Receive or Transmit activity
1986  * 0000: Link established
1987  */
1988 #define DP83867_LEDCR1_LED_GPIO_SEL_MASK (0xF000U)
1989 #define DP83867_LEDCR1_LED_GPIO_SEL_SHIFT (12U)
1990 #define DP83867_LEDCR1_LED_GPIO_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_GPIO_SEL_SHIFT) & DP83867_LEDCR1_LED_GPIO_SEL_MASK)
1991 #define DP83867_LEDCR1_LED_GPIO_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_GPIO_SEL_MASK) >> DP83867_LEDCR1_LED_GPIO_SEL_SHIFT)
1992 
1993 /*
1994  * LED_2_SEL (RW)
1995  *
1996  * Source of LED_2:
1997  * 1111: Reserved
1998  * 1110: Receive Error
1999  * 1101: Receive Error or Transmit Error
2000  * 1100: RESERVED
2001  * 1011: Link established, blink for transmit or receive activity
2002  * 1010: Full duplex
2003  * 1001: 100/1000BT link established
2004  * 1000: 10/100BT link established
2005  * 0111: 10BT link established
2006  * 0110: 100 BTX link established
2007  * 0101: 1000BT link established
2008  * 0100: Collision detected
2009  * 0011: Receive activity
2010  * 0010: Transmit activity
2011  * 0001: Receive or Transmit activity
2012  * 0000: Link established
2013  */
2014 #define DP83867_LEDCR1_LED_2_SEL_MASK (0xF00U)
2015 #define DP83867_LEDCR1_LED_2_SEL_SHIFT (8U)
2016 #define DP83867_LEDCR1_LED_2_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_2_SEL_SHIFT) & DP83867_LEDCR1_LED_2_SEL_MASK)
2017 #define DP83867_LEDCR1_LED_2_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_2_SEL_MASK) >> DP83867_LEDCR1_LED_2_SEL_SHIFT)
2018 
2019 /*
2020  * LED_1_SEL (RW)
2021  *
2022  * Source of LED_1:
2023  * 1111: Reserved
2024  * 1110: Receive Error
2025  * 1101: Receive Error or Transmit Error
2026  * 1100: RESERVED
2027  * 1011: Link established, blink for transmit or receive activity
2028  * 1010: Full duplex
2029  * 1001: 100/1000BT link established
2030  * 1000: 10/100BT link established
2031  * 0111: 10BT link established
2032  * 0110: 100 BTX link established
2033  * 0101: 1000BT link established
2034  * 0100: Collision detected
2035  * 0011: Receive activity
2036  * 0010: Transmit activity
2037  * 0001: Receive or Transmit activity
2038  * 0000: Link established
2039  */
2040 #define DP83867_LEDCR1_LED_1_SEL_MASK (0xF0U)
2041 #define DP83867_LEDCR1_LED_1_SEL_SHIFT (4U)
2042 #define DP83867_LEDCR1_LED_1_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_1_SEL_SHIFT) & DP83867_LEDCR1_LED_1_SEL_MASK)
2043 #define DP83867_LEDCR1_LED_1_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_1_SEL_MASK) >> DP83867_LEDCR1_LED_1_SEL_SHIFT)
2044 
2045 /*
2046  * LED_0_SEL (RW)
2047  *
2048  * Source of LED_0:
2049  * 1111: Reserved
2050  * 1110: Receive Error
2051  * 1101: Receive Error or Transmit Error
2052  * 1100: RESERVED
2053  * 1011: Link established, blink for transmit or receive activity
2054  * 1010: Full duplex
2055  * 1001: 100/1000BT link established
2056  * 1000: 10/100BT link established
2057  * 0111: 10BT link established
2058  * 0110: 100 BTX link established
2059  * 0101: 1000BT link established
2060  * 0100: Collision detected
2061  * 0011: Receive activity
2062  * 0010: Transmit activity
2063  * 0001: Receive or Transmit activity
2064  * 0000: Link established
2065  */
2066 #define DP83867_LEDCR1_LED_0_SEL_MASK (0xFU)
2067 #define DP83867_LEDCR1_LED_0_SEL_SHIFT (0U)
2068 #define DP83867_LEDCR1_LED_0_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_0_SEL_SHIFT) & DP83867_LEDCR1_LED_0_SEL_MASK)
2069 #define DP83867_LEDCR1_LED_0_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_0_SEL_MASK) >> DP83867_LEDCR1_LED_0_SEL_SHIFT)
2070 
2071 /* Bitfield definition for register: LEDCR2 */
2072 /*
2073  * LED_GPIO_POLARITY (RW)
2074  *
2075  * GPIO LED Polarity:
2076  * 1 = Active high
2077  * 0 = Active low
2078  */
2079 #define DP83867_LEDCR2_LED_GPIO_POLARITY_MASK (0x4000U)
2080 #define DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT (14U)
2081 #define DP83867_LEDCR2_LED_GPIO_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK)
2082 #define DP83867_LEDCR2_LED_GPIO_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK) >> DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT)
2083 
2084 /*
2085  * LED_GPIO_DRV_VAL (RW)
2086  *
2087  * GPIO LED Drive Value:
2088  * Value to force on GPIO LED
2089  * This bit is only valid if enabled through LED_GPIO_DRV_EN.
2090  */
2091 #define DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK (0x2000U)
2092 #define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT (13U)
2093 #define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK)
2094 #define DP83867_LEDCR2_LED_GPIO_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT)
2095 
2096 /*
2097  * LED_GPIO_DRV_EN (RW)
2098  *
2099  * GPIO LED Drive Enable:
2100  * 1 = Force the value of the LED_GPIO_DRV_VAL bit onto the GPIO
2101  * LED.
2102  * 0 = Normal operation
2103  */
2104 #define DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK (0x1000U)
2105 #define DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT (12U)
2106 #define DP83867_LEDCR2_LED_GPIO_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK)
2107 #define DP83867_LEDCR2_LED_GPIO_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT)
2108 
2109 /*
2110  * LED_2_POLARITY (RW)
2111  *
2112  * LED_2 Polarity:
2113  * 1 = Active high
2114  * 0 = Active low
2115  */
2116 #define DP83867_LEDCR2_LED_2_POLARITY_MASK (0x400U)
2117 #define DP83867_LEDCR2_LED_2_POLARITY_SHIFT (10U)
2118 #define DP83867_LEDCR2_LED_2_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_POLARITY_SHIFT) & DP83867_LEDCR2_LED_2_POLARITY_MASK)
2119 #define DP83867_LEDCR2_LED_2_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_POLARITY_MASK) >> DP83867_LEDCR2_LED_2_POLARITY_SHIFT)
2120 
2121 /*
2122  * LED_2_DRV_VAL (RW)
2123  *
2124  * LED_2 Drive Value:
2125  * Value to force on LED_2
2126  * This bit is only valid if enabled through LED_2_DRV_EN.
2127  */
2128 #define DP83867_LEDCR2_LED_2_DRV_VAL_MASK (0x200U)
2129 #define DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT (9U)
2130 #define DP83867_LEDCR2_LED_2_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK)
2131 #define DP83867_LEDCR2_LED_2_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT)
2132 
2133 /*
2134  * LED_2_DRV_EN (RW)
2135  *
2136  * LED_2 Drive Enable:
2137  * 1 = Force the value of the LED_2_DRV_VAL bit onto LED_2.
2138  * 0 = Normal operation
2139  */
2140 #define DP83867_LEDCR2_LED_2_DRV_EN_MASK (0x100U)
2141 #define DP83867_LEDCR2_LED_2_DRV_EN_SHIFT (8U)
2142 #define DP83867_LEDCR2_LED_2_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_2_DRV_EN_MASK)
2143 #define DP83867_LEDCR2_LED_2_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_EN_MASK) >> DP83867_LEDCR2_LED_2_DRV_EN_SHIFT)
2144 
2145 /*
2146  * LED_1_POLARITY (RW)
2147  *
2148  * LED_1 Polarity:
2149  * 1 = Active high
2150  * 0 = Active low
2151  */
2152 #define DP83867_LEDCR2_LED_1_POLARITY_MASK (0x40U)
2153 #define DP83867_LEDCR2_LED_1_POLARITY_SHIFT (6U)
2154 #define DP83867_LEDCR2_LED_1_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_POLARITY_SHIFT) & DP83867_LEDCR2_LED_1_POLARITY_MASK)
2155 #define DP83867_LEDCR2_LED_1_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_POLARITY_MASK) >> DP83867_LEDCR2_LED_1_POLARITY_SHIFT)
2156 
2157 /*
2158  * LED_1_DRV_VAL (RW)
2159  *
2160  * LED_1 Drive Value:
2161  * Value to force on LED_1
2162  * This bit is only valid if enabled through LED_1_DRV_EN.
2163  */
2164 #define DP83867_LEDCR2_LED_1_DRV_VAL_MASK (0x20U)
2165 #define DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT (5U)
2166 #define DP83867_LEDCR2_LED_1_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK)
2167 #define DP83867_LEDCR2_LED_1_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT)
2168 
2169 /*
2170  * LED_1_DRV_EN (RW)
2171  *
2172  * LED_1 Drive Enable:
2173  * 1 = Force the value of the LED_1_DRV_VAL bit onto LED_1.
2174  * 0 = Normal operation
2175  */
2176 #define DP83867_LEDCR2_LED_1_DRV_EN_MASK (0x10U)
2177 #define DP83867_LEDCR2_LED_1_DRV_EN_SHIFT (4U)
2178 #define DP83867_LEDCR2_LED_1_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_1_DRV_EN_MASK)
2179 #define DP83867_LEDCR2_LED_1_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_EN_MASK) >> DP83867_LEDCR2_LED_1_DRV_EN_SHIFT)
2180 
2181 /*
2182  * LED_0_POLARITY (RW)
2183  *
2184  * LED_0 Polarity:
2185  * 1 = Active high
2186  * 0 = Active low
2187  */
2188 #define DP83867_LEDCR2_LED_0_POLARITY_MASK (0x4U)
2189 #define DP83867_LEDCR2_LED_0_POLARITY_SHIFT (2U)
2190 #define DP83867_LEDCR2_LED_0_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_POLARITY_SHIFT) & DP83867_LEDCR2_LED_0_POLARITY_MASK)
2191 #define DP83867_LEDCR2_LED_0_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_POLARITY_MASK) >> DP83867_LEDCR2_LED_0_POLARITY_SHIFT)
2192 
2193 /*
2194  * LED_0_DRV_VAL (RW)
2195  *
2196  * LED_0 Drive Value:
2197  * Value to force on LED_0
2198  * This bit is only valid if enabled through LED_0_DRV_EN.
2199  */
2200 #define DP83867_LEDCR2_LED_0_DRV_VAL_MASK (0x2U)
2201 #define DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT (1U)
2202 #define DP83867_LEDCR2_LED_0_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK)
2203 #define DP83867_LEDCR2_LED_0_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT)
2204 
2205 /*
2206  * LED_0_DRV_EN (RW)
2207  *
2208  * LED_0 Drive Enable:
2209  * 1 = Force the value of the LED_0_DRV_VAL bit onto LED_0.
2210  * 0 = Normal operation
2211  */
2212 #define DP83867_LEDCR2_LED_0_DRV_EN_MASK (0x1U)
2213 #define DP83867_LEDCR2_LED_0_DRV_EN_SHIFT (0U)
2214 #define DP83867_LEDCR2_LED_0_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_0_DRV_EN_MASK)
2215 #define DP83867_LEDCR2_LED_0_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_EN_MASK) >> DP83867_LEDCR2_LED_0_DRV_EN_SHIFT)
2216 
2217 /* Bitfield definition for register: LEDCR3 */
2218 /*
2219  * LEDS_BYPASS_STRETCHING (RW)
2220  *
2221  * Bypass LED Stretching:
2222  * 1 = Bypass LED Stretching
2223  * 0 = Normal operation
2224  */
2225 #define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK (0x4U)
2226 #define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT (2U)
2227 #define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SET(x) (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK)
2228 #define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_GET(x) (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK) >> DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT)
2229 
2230 /*
2231  * LEDS_BLINK_RATE (RW)
2232  *
2233  * LED Blink Rate:
2234  * 11: 2 Hz (500 ms)
2235  * 10: 5 Hz (200 ms)
2236  * 01: 10 Hz (100 ms)
2237  * 00 = 20 Hz (50 ms)
2238  */
2239 #define DP83867_LEDCR3_LEDS_BLINK_RATE_MASK (0x3U)
2240 #define DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT (0U)
2241 #define DP83867_LEDCR3_LEDS_BLINK_RATE_SET(x) (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK)
2242 #define DP83867_LEDCR3_LEDS_BLINK_RATE_GET(x) (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK) >> DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT)
2243 
2244 /* Bitfield definition for register: CFG3 */
2245 /*
2246  * FAST_LINK_UP_IN_PARALLEL_DETECT (RW)
2247  *
2248  * Fast Link-Up in Parallel Detect Mode:
2249  * 1 = Enable Fast Link-Up time During Parallel Detection
2250  * 0 = Normal Parallel Detection link establishment
2251  * In Fast Auto MDI-X this bit is automatically set.
2252  */
2253 #define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK (0x8000U)
2254 #define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT (15U)
2255 #define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK)
2256 #define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK) >> DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT)
2257 
2258 /*
2259  * FAST_AN_ENABLE (RW)
2260  *
2261  * Fast Auto-Negotiation Enable:
2262  * 1 = Enable Fast Auto-Negotiation mode – The PHY auto-
2263  * negotiates using Timer setting according to Fast AN Sel bits
2264  * 0 = Disable Fast Auto-Negotiation mode – The PHY auto-
2265  * negotiates using normal Timer setting
2266  * Adjusting these bits reduces the time it takes to Auto-negotiate
2267  * between two PHYs. Note: When using this option care must be
2268  * taken to maintain proper operation of the system. While shortening
2269  * these timer intervals may not cause problems in normal operation,
2270  * there are certain situations where this may lead to problems.
2271  */
2272 #define DP83867_CFG3_FAST_AN_ENABLE_MASK (0x4000U)
2273 #define DP83867_CFG3_FAST_AN_ENABLE_SHIFT (14U)
2274 #define DP83867_CFG3_FAST_AN_ENABLE_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AN_ENABLE_SHIFT) & DP83867_CFG3_FAST_AN_ENABLE_MASK)
2275 #define DP83867_CFG3_FAST_AN_ENABLE_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AN_ENABLE_MASK) >> DP83867_CFG3_FAST_AN_ENABLE_SHIFT)
2276 
2277 /*
2278  * FAST_AN_SEL (RW)
2279  *
2280  * Fast Auto-Negotiation Select bits:
2281  * Fast AN Select  Break Link Timer(ms)    Link Fail Inhibit TImer(ms)   Auto-Neg Wait Timer(ms)
2282  * <00>            80                      50                            35
2283  * <01>            120                     75                            50
2284  * <10>            240                     150                           100
2285  * <11>            NA                      NA                            NA
2286  * Adjusting these bits reduces the time it takes to auto-negotiate
2287  * between two PHYs. In Fast AN mode, both PHYs should be
2288  * configured to the same configuration. These 2 bits define the
2289  * duration for each state of the Auto-Negotiation process according
2290  * to the table above. The new duration time must be enabled by
2291  * setting Fast AN En - bit 4 of this register. Note: Using this mode in
2292  * cases where both link partners are not configured to the same
2293  * Fast Auto-Negotiation configuration might produce scenarios with
2294  * unexpected behavior.
2295  */
2296 #define DP83867_CFG3_FAST_AN_SEL_MASK (0x3000U)
2297 #define DP83867_CFG3_FAST_AN_SEL_SHIFT (12U)
2298 #define DP83867_CFG3_FAST_AN_SEL_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AN_SEL_SHIFT) & DP83867_CFG3_FAST_AN_SEL_MASK)
2299 #define DP83867_CFG3_FAST_AN_SEL_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AN_SEL_MASK) >> DP83867_CFG3_FAST_AN_SEL_SHIFT)
2300 
2301 /*
2302  * EXTENDED_FD_ABILITY (RW)
2303  *
2304  * Extended Full-Duplex Ability:
2305  * 1 = Force Full-Duplex while working with link partner in forced
2306  * 100B-TX. When the PHY is set to Auto-Negotiation or Force 100B-
2307  * TX and the link partner is operated in Force 100B-TX, the link is
2308  * always Full Duplex
2309  * 0 = Disable Extended Full Duplex Ability. Decision to work in Full
2310  * Duplex or Half Duplex mode follows IEEE specification.
2311  */
2312 #define DP83867_CFG3_EXTENDED_FD_ABILITY_MASK (0x800U)
2313 #define DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT (11U)
2314 #define DP83867_CFG3_EXTENDED_FD_ABILITY_SET(x) (((uint16_t)(x) << DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK)
2315 #define DP83867_CFG3_EXTENDED_FD_ABILITY_GET(x) (((uint16_t)(x) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK) >> DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT)
2316 
2317 /*
2318  * ROBUST_AUTO_MDIX (RW)
2319  *
2320  * Robust Auto-MDIX:
2321  * 1 =Enable Robust Auto MDI/MDIX resolution
2322  * 0 = Normal Auto MDI/MDIX mode
2323  * If link partners are configured to operational modes that are not
2324  * supported by normal Auto MDI/MDIX mode (like Auto-Neg versus
2325  * Force 100Base-TX or Force 100Base-TX versus Force 100Base-
2326  * TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX
2327  * resolution and prevents deadlock.
2328  */
2329 #define DP83867_CFG3_ROBUST_AUTO_MDIX_MASK (0x200U)
2330 #define DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT (9U)
2331 #define DP83867_CFG3_ROBUST_AUTO_MDIX_SET(x) (((uint16_t)(x) << DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK)
2332 #define DP83867_CFG3_ROBUST_AUTO_MDIX_GET(x) (((uint16_t)(x) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK) >> DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT)
2333 
2334 /*
2335  * FAST_AUTO_MDIX (RW)
2336  *
2337  * Fast Auto MDI/MDIX:
2338  * 1 = Enable Fast Auto MDI/MDIX mode
2339  * 0 = Normal Auto MDI/MDIX mode
2340  * If both link partners are configured to work in Force 100Base-TX
2341  * mode (Auto-Negotiation is disabled), this mode enables Automatic
2342  * MDI/MDIX resolution in a short time.
2343  */
2344 #define DP83867_CFG3_FAST_AUTO_MDIX_MASK (0x100U)
2345 #define DP83867_CFG3_FAST_AUTO_MDIX_SHIFT (8U)
2346 #define DP83867_CFG3_FAST_AUTO_MDIX_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AUTO_MDIX_SHIFT) & DP83867_CFG3_FAST_AUTO_MDIX_MASK)
2347 #define DP83867_CFG3_FAST_AUTO_MDIX_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AUTO_MDIX_MASK) >> DP83867_CFG3_FAST_AUTO_MDIX_SHIFT)
2348 
2349 /*
2350  * INT_OE (RW)
2351  *
2352  * Interrupt Output Enable:
2353  * 1 = INTN/PWDNN Pad is an Interrupt Output.
2354  * 0 = INTN/PWDNN Pad in a Power-Down Input.
2355  */
2356 #define DP83867_CFG3_INT_OE_MASK (0x80U)
2357 #define DP83867_CFG3_INT_OE_SHIFT (7U)
2358 #define DP83867_CFG3_INT_OE_SET(x) (((uint16_t)(x) << DP83867_CFG3_INT_OE_SHIFT) & DP83867_CFG3_INT_OE_MASK)
2359 #define DP83867_CFG3_INT_OE_GET(x) (((uint16_t)(x) & DP83867_CFG3_INT_OE_MASK) >> DP83867_CFG3_INT_OE_SHIFT)
2360 
2361 /*
2362  * FORCE_INTERRUPT (RW)
2363  *
2364  * Force Interrupt:
2365  * 1 = Assert interrupt pin.
2366  * 0 = Normal interrupt mode.
2367  */
2368 #define DP83867_CFG3_FORCE_INTERRUPT_MASK (0x40U)
2369 #define DP83867_CFG3_FORCE_INTERRUPT_SHIFT (6U)
2370 #define DP83867_CFG3_FORCE_INTERRUPT_SET(x) (((uint16_t)(x) << DP83867_CFG3_FORCE_INTERRUPT_SHIFT) & DP83867_CFG3_FORCE_INTERRUPT_MASK)
2371 #define DP83867_CFG3_FORCE_INTERRUPT_GET(x) (((uint16_t)(x) & DP83867_CFG3_FORCE_INTERRUPT_MASK) >> DP83867_CFG3_FORCE_INTERRUPT_SHIFT)
2372 
2373 /*
2374  * TDR_FAIL (RO)
2375  *
2376  * TDR Failure:
2377  * 1 = TDR failed.
2378  * 0 = Normal TDR operation.
2379  */
2380 #define DP83867_CFG3_TDR_FAIL_MASK (0x4U)
2381 #define DP83867_CFG3_TDR_FAIL_SHIFT (2U)
2382 #define DP83867_CFG3_TDR_FAIL_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_FAIL_MASK) >> DP83867_CFG3_TDR_FAIL_SHIFT)
2383 
2384 /*
2385  * TDR_DONE (RO)
2386  *
2387  * TDR Done:
2388  * 1 = TDR has completed.
2389  * 0 = TDR has not completed.
2390  */
2391 #define DP83867_CFG3_TDR_DONE_MASK (0x2U)
2392 #define DP83867_CFG3_TDR_DONE_SHIFT (1U)
2393 #define DP83867_CFG3_TDR_DONE_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_DONE_MASK) >> DP83867_CFG3_TDR_DONE_SHIFT)
2394 
2395 /*
2396  * TDR_START (RW)
2397  *
2398  * TDR Start:
2399  * 1 = Start TDR.
2400  * 0 = Normal operation
2401  */
2402 #define DP83867_CFG3_TDR_START_MASK (0x1U)
2403 #define DP83867_CFG3_TDR_START_SHIFT (0U)
2404 #define DP83867_CFG3_TDR_START_SET(x) (((uint16_t)(x) << DP83867_CFG3_TDR_START_SHIFT) & DP83867_CFG3_TDR_START_MASK)
2405 #define DP83867_CFG3_TDR_START_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_START_MASK) >> DP83867_CFG3_TDR_START_SHIFT)
2406 
2407 /* Bitfield definition for register: CTRL */
2408 /*
2409  * SW_RESET (RW,SC)
2410  *
2411  * Software Reset:
2412  * 1 = Perform a full reset, including registers.
2413  * 0 = Normal operation.
2414  */
2415 #define DP83867_CTRL_SW_RESET_MASK (0x8000U)
2416 #define DP83867_CTRL_SW_RESET_SHIFT (15U)
2417 #define DP83867_CTRL_SW_RESET_SET(x) (((uint16_t)(x) << DP83867_CTRL_SW_RESET_SHIFT) & DP83867_CTRL_SW_RESET_MASK)
2418 #define DP83867_CTRL_SW_RESET_GET(x) (((uint16_t)(x) & DP83867_CTRL_SW_RESET_MASK) >> DP83867_CTRL_SW_RESET_SHIFT)
2419 
2420 /*
2421  * SW_RESTART (RW,SC)
2422  *
2423  * Software Restart:
2424  * 1 = Perform a full reset, not including registers. .
2425  * 0 = Normal operation.
2426  */
2427 #define DP83867_CTRL_SW_RESTART_MASK (0x4000U)
2428 #define DP83867_CTRL_SW_RESTART_SHIFT (14U)
2429 #define DP83867_CTRL_SW_RESTART_SET(x) (((uint16_t)(x) << DP83867_CTRL_SW_RESTART_SHIFT) & DP83867_CTRL_SW_RESTART_MASK)
2430 #define DP83867_CTRL_SW_RESTART_GET(x) (((uint16_t)(x) & DP83867_CTRL_SW_RESTART_MASK) >> DP83867_CTRL_SW_RESTART_SHIFT)
2431 
2432 /* Bitfield definition for register: RGMIIDCTL */
2433 /*
2434  * RGMII_TX_DELAY_CTRL (RW)
2435  *
2436  * RGMII Transmit Clock Delay:
2437  * 1111: 4.00 ns
2438  * 1110: 3.75 ns
2439  * 1101: 3.50 ns
2440  * 1100: 3.25 ns
2441  * 1011: 3.00 ns
2442  * 1010: 2.75 ns
2443  * 1001: 2.50 ns
2444  * 1000: 2.25 ns
2445  * 0111: 2.00 ns
2446  * 0110: 1.75 ns
2447  * 0101: 1.50 ns
2448  * 0100: 1.25 ns
2449  * 0011: 1.00 ns
2450  * 0010: 0.75 ns
2451  * 0001: 0.50 ns
2452  * 0000: 0.25 ns
2453  */
2454 #define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK (0xF0U)
2455 #define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT (4U)
2456 #define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SET(x) (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK)
2457 #define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_GET(x) (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT)
2458 
2459 /*
2460  * RGMII_RX_DELAY_CTRL (RW)
2461  *
2462  * RGMII Receive Clock Delay:
2463  * 1111: 4.00 ns
2464  * 1110: 3.75 ns
2465  * 1101: 3.50 ns
2466  * 1100: 3.25 ns
2467  * 1011: 3.00 ns
2468  * 1010: 2.75 ns
2469  * 1001: 2.50 ns
2470  * 1000: 2.25 ns
2471  * 0111: 2.00 ns
2472  * 0110: 1.75 ns
2473  * 0101: 1.50 ns
2474  * 0100: 1.25 ns
2475  * 0011: 1.00 ns
2476  * 0010: 0.75 ns
2477  * 0001: 0.50 ns
2478  * 0000: 0.25 ns
2479  */
2480 #define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK (0xFU)
2481 #define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT (0U)
2482 #define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SET(x) (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK)
2483 #define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_GET(x) (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT)
2484 
2485 
2486 
2487 
2488 #endif /* HPM_DP83867_REGS_H */
2489