1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author         Notes
8  * 2020-12-02    bigmagic       first version
9  */
10 #ifndef __DRV_DMA_H__
11 #define __DRV_DMA_H__
12 
13 #include <rthw.h>
14 
15 #define DMA_PER_BASE                    (0xFE000000)
16 
17 //DMA
18 #define DMA_BASE        (DMA_PER_BASE+0x7000)
19 #define DMA_INT_STATUS  (DMA_BASE + 0xFE0)          //Interrupt Status of each DMA Channel
20 #define DMA_ENABLE      (DMA_BASE + 0xFF0)          //Global Enable bits for each DMA Channel */
21 #define DMA15_BASE      (DMA_PER_BASE+0xE05000)     //DMA Channel 15 Register Set */
22 
23 
24 #define DMA_INT_STATUS_REG          __REG32(DMA_INT_STATUS)
25 #define DMA_ENABLE_REG              __REG32(DMA_ENABLE)
26 //DMA dch 1~14
27 #define DMA_CS(dch)                 __REG32(DMA_BASE + dch*0x100 + 0x000)    /* Control and Status */
28 #define DMA_CONBLK_AD(dch)          __REG32(DMA_BASE + dch*0x100 + 0x004)    /* Control Block Address */
29 #define DMA_TI(dch)                 __REG32(DMA_BASE + dch*0x100 + 0x008)    /* CB Word 0(Transfer Information) */
30 #define DMA_SOURCE_AD(dch)          __REG32(DMA_BASE + dch*0x100 + 0x00c)    /* CB Word 1(Source Address) */
31 #define DMA_DEST_AD(dch)            __REG32(DMA_BASE + dch*0x100 + 0x010)    /* CB Word 2(Destination Address) */
32 #define DMA_TXFR_LEN(dch)           __REG32(DMA_BASE + dch*0x100 + 0x014)    /* CB Word 3(Transfer Length) */
33 #define DMA_STRIDE(dch)             __REG32(DMA_BASE + dch*0x100 + 0x018)    /* CB Word 4(2D Stride) */
34 #define DMA_NEXTCONBK(dch)          __REG32(DMA_BASE + dch*0x100 + 0x01c)    /* CB Word 5(Next CB Address) */
35 #define DMA_DEBUG(dch)              __REG32(DMA_BASE + dch*0x100 + 0x01c)    /* Debug */
36 
37 //DMA dch 15
38 #define DMA15_CS                    __REG32(DMA15_BASE + 0x000)    /* Control and Status */
39 #define DMA15_CONBLK_AD             __REG32(DMA15_BASE + 0x004)    /* Control Block Address */
40 #define DMA15_TI                    __REG32(DMA15_BASE + 0x008)    /* CB Word 0(Transfer Information) */
41 #define DMA15_SOURCE_AD             __REG32(DMA15_BASE + 0x00c)    /* CB Word 1(Source Address) */
42 #define DMA15_DEST_AD               __REG32(DMA15_BASE + 0x010)    /* CB Word 2(Destination Address) */
43 #define DMA15_TXFR_LEN              __REG32(DMA15_BASE + 0x014)    /* CB Word 3(Transfer Length) */
44 #define DMA15_STRIDE                __REG32(DMA15_BASE + 0x018)    /* CB Word 4(2D Stride) */
45 #define DMA15_NEXTCONBK             __REG32(DMA15_BASE + 0x01c)    /* CB Word 5(Next CB Address) */
46 #define DMA15_DEBUG                 __REG32(DMA15_BASE + 0x01c)    /* Debug */
47 
48 #define DMA15_ENABLE             (1 << 15)
49 #define DMA14_ENABLE             (1 << 14)
50 #define DMA13_ENABLE             (1 << 13)
51 #define DMA12_ENABLE             (1 << 12)
52 #define DMA11_ENABLE             (1 << 11)
53 #define DMA10_ENABLE             (1 << 10)
54 #define DMA9_ENABLE              (1 << 9)
55 #define DMA8_ENABLE              (1 << 8)
56 #define DMA7_ENABLE              (1 << 7)
57 #define DMA6_ENABLE              (1 << 6)
58 #define DMA5_ENABLE              (1 << 5)
59 #define DMA4_ENABLE              (1 << 4)
60 #define DMA3_ENABLE              (1 << 3)
61 #define DMA2_ENABLE              (1 << 2)
62 #define DMA1_ENABLE              (1 << 1)
63 #define DMA0_ENABLE              (1 << 0)
64 
65 //Peripheral DREQ Signals
66 #define DREQ_DSI0_PWM1        (1)
67 #define DREQ_PCM_TX           (2)
68 #define DREQ_PCM_RX           (3)
69 #define DREQ_SMI              (4)
70 #define DREQ_PWM0             (5)
71 #define DREQ_SPI0_TX          (6)
72 #define DREQ_SPI0_RX          (7)
73 #define DREQ_BSC_SPI_SLAVE_TX (8)
74 #define DREQ_BSC_SPI_SLAVE_RX (9)
75 #define DREQ_HSMI0            (10)
76 #define DREQ_EMMC             (11)
77 #define DREQ_UART0_TX         (12)
78 #define DREQ_SD_HOST          (13)
79 #define DREQ_UART0_RX         (14)
80 #define DREQ_DSI1             (15)
81 #define DREQ_SPI1_TX          (16)
82 #define DREQ_HDMI1            (17)
83 #define DREQ_SPI1_RX          (18)
84 #define DREQ_UART3_TX_SPI4_TX (19)
85 #define DREQ_UART3_RX_SPI4_RX (20)
86 #define DREQ_UART5_TX_SPI5_TX (21)
87 #define DREQ_UART5_RX_SPI5_RX (22)
88 #define DREQ_SPI6_TX          (23)
89 #define DREQ_SCALER_FIFO0_SMI (24)
90 #define DREQ_SCALER_FIFO1_SMI (25)
91 #define DREQ_SCALER_FIFO2_SMI (26)
92 #define DREQ_SPI6_RX          (27)
93 #define DREQ_UART2_TX         (28)
94 #define DREQ_UART2_RX         (29)
95 #define DREQ_UART4_TX         (30)
96 #define DREQ_UART4_RX         (31)
97 
98 //IRQ
99 #define DMA_INT15           (1 << 15)
100 #define DMA_INT14           (1 << 14)
101 #define DMA_INT13           (1 << 13)
102 #define DMA_INT12           (1 << 12)
103 #define DMA_INT11           (1 << 11)
104 #define DMA_INT10           (1 << 10)
105 #define DMA_INT9            (1 << 9)
106 #define DMA_INT8            (1 << 8)
107 #define DMA_INT7            (1 << 7)
108 #define DMA_INT6            (1 << 6)
109 #define DMA_INT5            (1 << 5)
110 #define DMA_INT4            (1 << 4)
111 #define DMA_INT3            (1 << 3)
112 #define DMA_INT2            (1 << 2)
113 #define DMA_INT1            (1 << 1)
114 #define DMA_INT0            (1 << 0)
115 
116 //IRQ_NUMBER
117 #define IRQ_DMA0            (96 + 16)
118 #define IRQ_DMA1            (96 + 17)
119 #define IRQ_DMA2            (96 + 18)
120 #define IRQ_DMA3            (96 + 19)
121 #define IRQ_DMA4            (96 + 20)
122 #define IRQ_DMA5            (96 + 21)
123 #define IRQ_DMA6            (96 + 22)
124 #define IRQ_DMA7_DMA8       (96 + 23)
125 #define IRQ_DMA9_DMA10      (96 + 24)
126 #define IRQ_DMA11           (96 + 25)
127 #define IRQ_DMA12           (96 + 26)
128 #define IRQ_DMA13           (96 + 27)
129 #define IRQ_DMA14           (96 + 28)
130 #define IRQ_DMA15           (96 + 31)
131 
132 //CS
133 #define DMA_CS_RESET            (1 << 31)
134 #define DMA_CS_ABORT            (1 << 30)
135 #define DMA_CS_DISDEBUG         (1 << 29)
136 #define DMA_CS_DREQ_STOPS_DMA   (1 << 5)
137 #define DMA_CS_PAUSED           (1 << 4)
138 #define DMA_CS_DREQ             (1 << 3)
139 #define DMA_CS_INT              (1 << 2)
140 #define DMA_CS_END              (1 << 1)
141 #define DMA_CS_ACTIVE           (1 << 0)
142 
143 //CONBLK_AD
144 //The address must be256-bit aligned, so the bottom 5 bits of the address mustbe zero.
145 
146 //TI
147 //DMA Transfer Information.
148 #define DMA_TI_SRC_IGNORE       (1 << 11)
149 #define DMA_TI_SRC_DREQ         (1 << 10)
150 #define DMA_TI_SRC_WIDTH        (1 << 9)
151 #define DMA_TI_SRC_INC          (1 << 8)
152 #define DMA_TI_DEST_IGNORE      (1 << 7)
153 #define DMA_TI_DEST_DREQ        (1 << 6)
154 #define DMA_TI_DEST_WIDTH       (1 << 5)
155 #define DMA_TI_DEST_INC         (1 << 4)
156 #define DMA_TI_WAIT_RESP        (1 << 3)
157 #define DMA_TI_TDMODE           (1 << 1)
158 #define DMA_TI_INTEN            (1 << 0)
159 
160 //SOURCE_AD
161 //DMA Source Address
162 
163 //DEST_AD
164 //DMA Destination Address
165 
166 //TXFR_LEN
167 //DMA Transfer Length
168 
169 void dma_init(unsigned char dch);
170 rt_err_t dma_memcpy(void *src, void *dst, unsigned int size, unsigned int dch, unsigned int timeout);
171 
172 #endif
173