1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2020-07-20 thread-liu the first version 9 */ 10 11 #ifndef __DRV_ETH_H__ 12 #define __DRV_ETH_H__ 13 14 #include <rtthread.h> 15 #include <rthw.h> 16 #include <rtdevice.h> 17 #include <board.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef struct 24 { 25 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100/1000 Mbps. 26 This parameter can be a value of @ref ETH_Speed */ 27 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 28 This parameter can be a value of @ref ETH_Duplex_Mode */ 29 } ETH_MACConfigTypeDef; 30 31 /** 32 * @brief Transmit descriptor 33 **/ 34 typedef struct 35 { 36 uint32_t tdes0; 37 uint32_t tdes1; 38 uint32_t tdes2; 39 uint32_t tdes3; 40 } TxDmaDesc; 41 42 /** 43 * @brief Receive descriptor 44 **/ 45 typedef struct 46 { 47 uint32_t rdes0; 48 uint32_t rdes1; 49 uint32_t rdes2; 50 uint32_t rdes3; 51 } RxDmaDesc; 52 53 #define RTL8211F_PHY_ADDR 1 /* PHY address */ 54 55 #define ETH_TXBUFNB 4 /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ 56 #define ETH_TX_BUF_SIZE 1536 /* buffer size for transmit */ 57 #define ETH_RXBUFNB 4 /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ 58 #define ETH_RX_BUF_SIZE 1536 /* buffer size for receive */ 59 60 #define ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk /* ETH_MMCTXIMR register */ 61 62 /* Register access macros */ 63 #define ETH_MACRXQC0R_RXQ0EN_Val(n) (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk) 64 #define ETH_MACMDIOAR_CR_Val(n) (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk) 65 #define ETH_MACMDIOAR_GOC_Val(n) (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk) 66 #define ETH_MTLTXQ0OMR_TQS_Val(n) (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk) 67 #define ETH_MTLTXQ0OMR_TXQEN_Val(n) (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk) 68 #define ETH_MTLRXQ0OMR_RQS_Val(n) (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk) 69 #define ETH_DMAMR_INTM_Val(n) (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk) 70 #define ETH_DMAMR_PR_Val(n) (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk) 71 #define ETH_DMAC0CR_DSL_Val(n) (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk) 72 #define ETH_DMAC0TXCR_TXPBL_Val(n) (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk) 73 #define ETH_DMAC0RXCR_RXPBL_Val(n) (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk) 74 #define ETH_DMAC0RXCR_RBSZ_Val(n) (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk) 75 76 /* Transmit normal descriptor (read format) */ 77 #define ETH_TDES0_BUF1AP 0xFFFFFFFF 78 #define ETH_TDES1_BUF2AP 0xFFFFFFFF 79 #define ETH_TDES2_IOC 0x80000000 80 #define ETH_TDES2_TTSE 0x40000000 81 #define ETH_TDES2_B2L 0x3FFF0000 82 #define ETH_TDES2_VTIR 0x0000C000 83 #define ETH_TDES2_B1L 0x00003FFF 84 #define ETH_TDES3_OWN 0x80000000 85 #define ETH_TDES3_CTXT 0x40000000 86 #define ETH_TDES3_FD 0x20000000 87 #define ETH_TDES3_LD 0x10000000 88 #define ETH_TDES3_CPC 0x0C000000 89 #define ETH_TDES3_SAIC 0x03800000 90 #define ETH_TDES3_THL 0x00780000 91 #define ETH_TDES3_TSE 0x00040000 92 #define ETH_TDES3_CIC 0x00030000 93 #define ETH_TDES3_FL 0x00007FFF 94 95 /* Transmit normal descriptor (write-back format) */ 96 #define ETH_TDES0_TTSL 0xFFFFFFFF 97 #define ETH_TDES1_TTSH 0xFFFFFFFF 98 #define ETH_TDES3_OWN 0x80000000 99 #define ETH_TDES3_CTXT 0x40000000 100 #define ETH_TDES3_FD 0x20000000 101 #define ETH_TDES3_LD 0x10000000 102 #define ETH_TDES3_TTSS 0x00020000 103 #define ETH_TDES3_ES 0x00008000 104 #define ETH_TDES3_JT 0x00004000 105 #define ETH_TDES3_FF 0x00002000 106 #define ETH_TDES3_PCE 0x00001000 107 #define ETH_TDES3_LOC 0x00000800 108 #define ETH_TDES3_NC 0x00000400 109 #define ETH_TDES3_LC 0x00000200 110 #define ETH_TDES3_EC 0x00000100 111 #define ETH_TDES3_CC 0x000000F0 112 #define ETH_TDES3_ED 0x00000008 113 #define ETH_TDES3_UF 0x00000004 114 #define ETH_TDES3_DB 0x00000002 115 #define ETH_TDES3_IHE 0x00000001 116 117 /* Transmit context descriptor */ 118 #define ETH_TDES0_TTSL 0xFFFFFFFF 119 #define ETH_TDES1_TTSH 0xFFFFFFFF 120 #define ETH_TDES2_IVT 0xFFFF0000 121 #define ETH_TDES2_MSS 0x00003FFF 122 #define ETH_TDES3_OWN 0x80000000 123 #define ETH_TDES3_CTXT 0x40000000 124 #define ETH_TDES3_OSTC 0x08000000 125 #define ETH_TDES3_TCMSSV 0x04000000 126 #define ETH_TDES3_CDE 0x00800000 127 #define ETH_TDES3_IVLTV 0x00020000 128 #define ETH_TDES3_VLTV 0x00010000 129 #define ETH_TDES3_VT 0x0000FFFF 130 131 /* Receive normal descriptor (read format) */ 132 #define ETH_RDES0_BUF1AP 0xFFFFFFFF 133 #define ETH_RDES2_BUF2AP 0xFFFFFFFF 134 #define ETH_RDES3_OWN 0x80000000 135 #define ETH_RDES3_IOC 0x40000000 136 #define ETH_RDES3_BUF2V 0x02000000 137 #define ETH_RDES3_BUF1V 0x01000000 138 139 /* Receive normal descriptor (write-back format) */ 140 #define ETH_RDES0_IVT 0xFFFF0000 141 #define ETH_RDES0_OVT 0x0000FFFF 142 #define ETH_RDES1_OPC 0xFFFF0000 143 #define ETH_RDES1_TD 0x00008000 144 #define ETH_RDES1_TSA 0x00004000 145 #define ETH_RDES1_PV 0x00002000 146 #define ETH_RDES1_PFT 0x00001000 147 #define ETH_RDES1_PMT 0x00000F00 148 #define ETH_RDES1_IPCE 0x00000080 149 #define ETH_RDES1_IPCB 0x00000040 150 #define ETH_RDES1_IPV6 0x00000020 151 #define ETH_RDES1_IPV4 0x00000010 152 #define ETH_RDES1_IPHE 0x00000008 153 #define ETH_RDES1_PT 0x00000007 154 #define ETH_RDES2_L3L4FM 0xE0000000 155 #define ETH_RDES2_L4FM 0x10000000 156 #define ETH_RDES2_L3FM 0x08000000 157 #define ETH_RDES2_MADRM 0x07F80000 158 #define ETH_RDES2_HF 0x00040000 159 #define ETH_RDES2_DAF 0x00020000 160 #define ETH_RDES2_SAF 0x00010000 161 #define ETH_RDES2_VF 0x00008000 162 #define ETH_RDES2_ARPRN 0x00000400 163 #define ETH_RDES3_OWN 0x80000000 164 #define ETH_RDES3_CTXT 0x40000000 165 #define ETH_RDES3_FD 0x20000000 166 #define ETH_RDES3_LD 0x10000000 167 #define ETH_RDES3_RS2V 0x08000000 168 #define ETH_RDES3_RS1V 0x04000000 169 #define ETH_RDES3_RS0V 0x02000000 170 #define ETH_RDES3_CE 0x01000000 171 #define ETH_RDES3_GP 0x00800000 172 #define ETH_RDES3_RWT 0x00400000 173 #define ETH_RDES3_OE 0x00200000 174 #define ETH_RDES3_RE 0x00100000 175 #define ETH_RDES3_DE 0x00080000 176 #define ETH_RDES3_LT 0x00070000 177 #define ETH_RDES3_ES 0x00008000 178 #define ETH_RDES3_PL 0x00007FFF 179 180 /* Receive context descriptor */ 181 #define ETH_RDES0_RTSL 0xFFFFFFFF 182 #define ETH_RDES1_RTSH 0xFFFFFFFF 183 #define ETH_RDES3_OWN 0x80000000 184 #define ETH_RDES3_CTXT 0x40000000 185 186 #define RTL8211F_BMCR ((uint16_t)0x0000U) /* Basic Mode Control Register. */ 187 #define RTL8211F_BMSR ((uint16_t)0x0001U) /* Basic Mode Status Register. */ 188 #define RTL8211F_PHYID1 ((uint16_t)0x0002U) /* PHY Identifier Register 1. */ 189 #define RTL8211F_PHYID2 ((uint16_t)0x0003U) /* PHY Identifier Register 2. */ 190 #define RTL8211F_ANAR ((uint16_t)0x0004U) /* Auto-Negotiation Advertising Register. */ 191 #define RTL8211F_ANLPAR ((uint16_t)0x0005U) /* Auto-Negotiation Link Partner Ability Register. */ 192 #define RTL8211F_ANER ((uint16_t)0x0006U) /* Auto-Negotiation Expansion Register.*/ 193 #define RTL8211F_ANNPTR ((uint16_t)0x0007U) /* Auto-Negotiation Next Page Transmit Register.*/ 194 #define RTL8211F_ANNPRR ((uint16_t)0x0008U) /* Auto-Negotiation Next Page Receive Register. */ 195 #define RTL8211F_GBCR ((uint16_t)0x0009U) /* 1000Base-T Control Register. */ 196 #define RTL8211F_GBSR ((uint16_t)0x000AU) /* 1000Base-T Status Register. */ 197 #define RTL8211F_MMDACR ((uint16_t)0x000DU) /* MMD Access Control Register. */ 198 #define RTL8211F_MMDAADR ((uint16_t)0x000EU) /* MMD Access Address Data Register. */ 199 #define RTL8211F_GBESR ((uint16_t)0x000FU) /* 1000Base-T Extended Status Register. */ 200 #define RTL8211F_LCR ((uint16_t)0x0010U) /* LED Control Register. */ 201 #define RTL8211F_INER ((uint16_t)0x0012U) /* Interrupt Enable Register. */ 202 #define RTL8211F_PHYSCR ((uint16_t)0x0014U) /* PHY Special Cofig Register */ 203 #define RTL8211F_PHYCR1 ((uint16_t)0x0018U) /* PHY Specific Control Register 1. */ 204 #define RTL8211F_PHYCR2 ((uint16_t)0x0019U) /* PHY Specific Control Register 2. */ 205 #define RTL8211F_PHYSR ((uint16_t)0x001AU) /* PHY Specific Status Register. */ 206 #define RTL8211F_INSR ((uint16_t)0x001DU) /* Interrupt Status Register. */ 207 #define RTL8211F_PAGSR ((uint16_t)0x001FU) /* Page Select Register. */ 208 209 /* Basic Mode Control register */ 210 #define RTL8211F_BMCR_RESET 0x8000 211 #define RTL8211F_BMCR_LOOPBACK 0x4000 212 #define RTL8211F_BMCR_SPEED_SEL_LSB 0x2000 213 #define RTL8211F_BMCR_AN_EN 0x1000 214 #define RTL8211F_BMCR_POWER_DOWN 0x0800 215 #define RTL8211F_BMCR_ISOLATE 0x0400 216 #define RTL8211F_BMCR_RESTART_AN 0x0200 217 #define RTL8211F_BMCR_DUPLEX_MODE 0x0100 218 #define RTL8211F_BMCR_COL_TEST 0x0080 219 #define RTL8211F_BMCR_SPEED_SEL_MSB 0x0040 220 #define RTL8211F_BMCR_UNI_DIR_EN 0x0020 221 222 /* Basic Mode Status register */ 223 #define RTL8211F_BMSR_100BT4 0x8000 224 #define RTL8211F_BMSR_100BTX_FD 0x4000 225 #define RTL8211F_BMSR_100BTX_HD 0x2000 226 #define RTL8211F_BMSR_10BT_FD 0x1000 227 #define RTL8211F_BMSR_10BT_HD 0x0800 228 #define RTL8211F_BMSR_100BT2_FD 0x0400 229 #define RTL8211F_BMSR_100BT2_HD 0x0200 230 #define RTL8211F_BMSR_EXTENDED_STATUS 0x0100 231 #define RTL8211F_BMSR_UNI_DIR_CAPABLE 0x0080 232 #define RTL8211F_BMSR_PREAMBLE_SUPPR 0x0040 233 #define RTL8211F_BMSR_AN_COMPLETE 0x0020 234 #define RTL8211F_BMSR_REMOTE_FAULT 0x0010 235 #define RTL8211F_BMSR_AN_CAPABLE 0x0008 236 #define RTL8211F_BMSR_LINK_STATUS 0x0004 237 #define RTL8211F_BMSR_JABBER_DETECT 0x0002 238 #define RTL8211F_BMSR_EXTENDED_CAPABLE 0x0001 239 240 /* PHY Identifier 1 register */ 241 #define RTL8211F_PHYID1_OUI_MSB 0xFFFF 242 #define RTL8211F_PHYID1_OUI_MSB_DEFAULT 0x001C 243 244 /* PHY Identifier 2 register */ 245 #define RTL8211F_PHYID2_OUI_LSB 0xFC00 246 #define RTL8211F_PHYID2_OUI_LSB_DEFAULT 0xC800 247 #define RTL8211F_PHYID2_MODEL_NUM 0x03F0 248 #define RTL8211F_PHYID2_MODEL_NUM_DEFAULT 0x0110 249 #define RTL8211F_PHYID2_REVISION_NUM 0x000F 250 #define RTL8211F_PHYID2_REVISION_NUM_DEFAULT 0x0006 251 252 /* Auto-Negotiation Advertisement register */ 253 #define RTL8211F_ANAR_NEXT_PAGE 0x8000 254 #define RTL8211F_ANAR_REMOTE_FAULT 0x2000 255 #define RTL8211F_ANAR_ASYM_PAUSE 0x0800 256 #define RTL8211F_ANAR_PAUSE 0x0400 257 #define RTL8211F_ANAR_100BT4 0x0200 258 #define RTL8211F_ANAR_100BTX_FD 0x0100 259 #define RTL8211F_ANAR_100BTX_HD 0x0080 260 #define RTL8211F_ANAR_10BT_FD 0x0040 261 #define RTL8211F_ANAR_10BT_HD 0x0020 262 #define RTL8211F_ANAR_SELECTOR 0x001F 263 #define RTL8211F_ANAR_SELECTOR_DEFAULT 0x0001 264 265 /* Auto-Negotiation Link Partner Ability register */ 266 #define RTL8211F_ANLPAR_NEXT_PAGE 0x8000 267 #define RTL8211F_ANLPAR_ACK 0x4000 268 #define RTL8211F_ANLPAR_REMOTE_FAULT 0x2000 269 #define RTL8211F_ANLPAR_ASYM_PAUSE 0x0800 270 #define RTL8211F_ANLPAR_PAUSE 0x0400 271 #define RTL8211F_ANLPAR_100BT4 0x0200 272 #define RTL8211F_ANLPAR_100BTX_FD 0x0100 273 #define RTL8211F_ANLPAR_100BTX_HD 0x0080 274 #define RTL8211F_ANLPAR_10BT_FD 0x0040 275 #define RTL8211F_ANLPAR_10BT_HD 0x0020 276 #define RTL8211F_ANLPAR_SELECTOR 0x001F 277 #define RTL8211F_ANLPAR_SELECTOR_DEFAULT 0x0001 278 279 /* Auto-Negotiation Expansion register */ 280 #define RTL8211F_ANER_RX_NP_LOCATION_ABLE 0x0040 281 #define RTL8211F_ANER_RX_NP_LOCATION 0x0020 282 #define RTL8211F_ANER_PAR_DETECT_FAULT 0x0010 283 #define RTL8211F_ANER_LP_NEXT_PAGE_ABLE 0x0008 284 #define RTL8211F_ANER_NEXT_PAGE_ABLE 0x0004 285 #define RTL8211F_ANER_PAGE_RECEIVED 0x0002 286 #define RTL8211F_ANER_LP_AN_ABLE 0x0001 287 288 /* Auto-Negotiation Next Page Transmit register */ 289 #define RTL8211F_ANNPTR_NEXT_PAGE 0x8000 290 #define RTL8211F_ANNPTR_MSG_PAGE 0x2000 291 #define RTL8211F_ANNPTR_ACK2 0x1000 292 #define RTL8211F_ANNPTR_TOGGLE 0x0800 293 #define RTL8211F_ANNPTR_MESSAGE 0x07FF 294 295 /* Auto-Negotiation Next Page Receive register */ 296 #define RTL8211F_ANNPRR_NEXT_PAGE 0x8000 297 #define RTL8211F_ANNPRR_ACK 0x4000 298 #define RTL8211F_ANNPRR_MSG_PAGE 0x2000 299 #define RTL8211F_ANNPRR_ACK2 0x1000 300 #define RTL8211F_ANNPRR_TOGGLE 0x0800 301 #define RTL8211F_ANNPRR_MESSAGE 0x07FF 302 303 /* 1000Base-T Control register */ 304 #define RTL8211F_GBCR_TEST_MODE 0xE000 305 #define RTL8211F_GBCR_MS_MAN_CONF_EN 0x1000 306 #define RTL8211F_GBCR_MS_MAN_CONF_VAL 0x0800 307 #define RTL8211F_GBCR_PORT_TYPE 0x0400 308 #define RTL8211F_GBCR_1000BT_FD 0x0200 309 310 /* 1000Base-T Status register */ 311 #define RTL8211F_GBSR_MS_CONF_FAULT 0x8000 312 #define RTL8211F_GBSR_MS_CONF_RES 0x4000 313 #define RTL8211F_GBSR_LOCAL_RECEIVER_STATUS 0x2000 314 #define RTL8211F_GBSR_REMOTE_RECEIVER_STATUS 0x1000 315 #define RTL8211F_GBSR_LP_1000BT_FD 0x0800 316 #define RTL8211F_GBSR_LP_1000BT_HD 0x0400 317 #define RTL8211F_GBSR_IDLE_ERR_COUNT 0x00FF 318 319 /* MMD Access Control register */ 320 #define RTL8211F_MMDACR_FUNC 0xC000 321 #define RTL8211F_MMDACR_FUNC_ADDR 0x0000 322 #define RTL8211F_MMDACR_FUNC_DATA_NO_POST_INC 0x4000 323 #define RTL8211F_MMDACR_FUNC_DATA_POST_INC_RW 0x8000 324 #define RTL8211F_MMDACR_FUNC_DATA_POST_INC_W 0xC000 325 #define RTL8211F_MMDACR_DEVAD 0x001F 326 327 /* 1000Base-T Extended Status register */ 328 #define RTL8211F_GBESR_1000BX_FD 0x8000 329 #define RTL8211F_GBESR_1000BX_HD 0x4000 330 #define RTL8211F_GBESR_1000BT_FD 0x2000 331 #define RTL8211F_GBESR_1000BT_HD 0x1000 332 333 /* Interrupt Enable register */ 334 #define RTL8211F_INER_JABBER 0x0400 335 #define RTL8211F_INER_ALDPS_STATE 0x0200 336 #define RTL8211F_INER_PME 0x0080 337 #define RTL8211F_INER_PHY_REG_ACCESS 0x0020 338 #define RTL8211F_INER_LINK_STATUS 0x0010 339 #define RTL8211F_INER_AN_COMPLETE 0x0008 340 #define RTL8211F_INER_PAGE_RECEIVED 0x0004 341 #define RTL8211F_INER_AN_ERROR 0x0001 342 343 /* PHY Specific Control 1 register */ 344 #define RTL8211F_PHYCR1_PHYAD_0_EN 0x2000 345 #define RTL8211F_PHYCR1_MDI_MODE_MANUAL_CONFIG 0x0200 346 #define RTL8211F_PHYCR1_MDI_MODE 0x0100 347 #define RTL8211F_PHYCR1_TX_CRS_EN 0x0080 348 #define RTL8211F_PHYCR1_PHYAD_NON_ZERO_DETECT 0x0040 349 #define RTL8211F_PHYCR1_PREAMBLE_CHECK_EN 0x0010 350 #define RTL8211F_PHYCR1_JABBER_DETECT_EN 0x0008 351 #define RTL8211F_PHYCR1_ALDPS_EN 0x0004 352 353 /* PHY Specific Control 2 register */ 354 #define RTL8211F_PHYCR2_CLKOUT_FREQ_SEL 0x0800 355 #define RTL8211F_PHYCR2_CLKOUT_SSC_EN 0x0080 356 #define RTL8211F_PHYCR2_RXC_SSC_EN 0x0008 357 #define RTL8211F_PHYCR2_RXC_EN 0x0002 358 #define RTL8211F_PHYCR2_CLKOUT_EN 0x0001 359 360 /* PHY Specific Status register */ 361 #define RTL8211F_PHYSR_ALDPS_STATE 0x4000 362 #define RTL8211F_PHYSR_MDI_PLUG 0x2000 363 #define RTL8211F_PHYSR_NWAY_EN 0x1000 364 #define RTL8211F_PHYSR_MASTER_MODE 0x0800 365 #define RTL8211F_PHYSR_EEE_CAPABLE 0x0100 366 #define RTL8211F_PHYSR_RX_FLOW_EN 0x0080 367 #define RTL8211F_PHYSR_TX_FLOW_EN 0x0040 368 #define RTL8211F_PHYSR_SPEED 0x0030 369 #define RTL8211F_PHYSR_SPEED_10MBPS 0x0000 370 #define RTL8211F_PHYSR_SPEED_100MBPS 0x0010 371 #define RTL8211F_PHYSR_SPEED_1000MBPS 0x0020 372 #define RTL8211F_PHYSR_DUPLEX 0x0008 373 #define RTL8211F_PHYSR_LINK 0x0004 374 #define RTL8211F_PHYSR_MDI_CROSSOVER_STATUS 0x0002 375 #define RTL8211F_PHYSR_JABBER 0x0001 376 377 /* Interrupt Status register */ 378 #define RTL8211F_INSR_JABBER 0x0400 379 #define RTL8211F_INSR_ALDPS_STATE 0x0200 380 #define RTL8211F_INSR_PME 0x0080 381 #define RTL8211F_INSR_PHY_REG_ACCESS 0x0020 382 #define RTL8211F_INSR_LINK_STATUS 0x0010 383 #define RTL8211F_INSR_AN_COMPLETE 0x0008 384 #define RTL8211F_INSR_PAGE_RECEIVED 0x0004 385 #define RTL8211F_INSR_AN_ERROR 0x0001 386 387 /* Page Select register */ 388 #define RTL8211F_PAGSR_PAGE_SEL 0x0007 389 390 #ifdef __cplusplus 391 } 392 #endif 393 394 #endif 395