1 /*
2 * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0.
5 *
6 * @Date: 2021-04-16 14:00:59
7 * @LastEditTime: 2021-04-16 16:07:27
8 * @Description: This files is for
9 *
10 * @Modify History:
11 * Ver Who Date Changes
12 * ----- ------ -------- --------------------------------------
13 */
14
15 #include "ft_cache.h"
16
FCache_cacheLineSize(void)17 __STATIC_INLINE u32 FCache_cacheLineSize(void)
18 {
19 u32 ctr;
20 asm volatile("mrc p15, 0, %0, c0, c0, 1"
21 : "=r"(ctr));
22 return 4 << ((ctr >> 16) & 0xF);
23 }
24
FCache_cpuDcacheInvalidate(void * addr,ft_base_t size)25 void FCache_cpuDcacheInvalidate(void *addr, ft_base_t size)
26 {
27 u32 lineSize = FCache_cacheLineSize();
28 u32 startAddr = (u32)addr;
29 u32 endAddr = (u32)addr + size + lineSize - 1;
30
31 asm volatile("dmb" ::
32 : "memory");
33
34 startAddr &= ~(lineSize - 1);
35 endAddr &= ~(lineSize - 1);
36
37 while (startAddr < endAddr)
38 {
39 asm volatile("mcr p15, 0, %0, c7, c6, 1" ::"r"(startAddr)); /* dcimvac */
40 startAddr += lineSize;
41 }
42
43 asm volatile("dsb" ::
44 : "memory");
45 }
46
FCache_cpuDcacheClean(void * addr,ft_base_t size)47 void FCache_cpuDcacheClean(void *addr, ft_base_t size)
48 {
49 u32 lineSize = FCache_cacheLineSize();
50 u32 startAddr = (u32)addr;
51 u32 endAddr = (u32)addr + size + lineSize - 1;
52
53 asm volatile("dmb" ::
54 : "memory");
55
56 startAddr &= ~(lineSize - 1);
57 endAddr &= ~(lineSize - 1);
58
59 while (startAddr < endAddr)
60 {
61 asm volatile("mcr p15, 0, %0, c7, c10, 1" ::"r"(startAddr)); /* dccmvac */
62 startAddr += lineSize;
63 }
64
65 asm volatile("dsb" ::
66 : "memory");
67 }
68
FCache_cpuIcacheInvalidate(void * addr,ft_base_t size)69 void FCache_cpuIcacheInvalidate(void *addr, ft_base_t size)
70 {
71 u32 lineSize = FCache_cacheLineSize();
72 u32 startAddr = (u32)addr;
73 u32 endAddr = (u32)addr + size + lineSize - 1;
74
75 asm volatile("dmb" ::
76 : "memory");
77 startAddr &= ~(lineSize - 1);
78 endAddr &= ~(lineSize - 1);
79 while (startAddr < endAddr)
80 {
81 asm volatile("mcr p15, 0, %0, c7, c5, 1" ::"r"(startAddr)); /* icimvau */
82 startAddr += lineSize;
83 }
84 asm volatile("dsb\n\tisb" ::
85 : "memory");
86 }
87