1 /* 2 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0. 5 * 6 * @Date: 2021-04-27 13:52:47 7 * @LastEditTime: 2021-04-27 13:52:47 8 * @Description: Description of file 9 * @Modify History: 10 * * * Ver Who Date Changes 11 * * ----- ------ -------- -------------------------------------- 12 */ 13 14 #ifndef FT_CAN_HW_H 15 #define FT_CAN_HW_H 16 17 #include "ft_types.h" 18 #include "ft_io.h" 19 #include "ft_can.h" 20 21 /***ft CAN REGISTER offset*/ 22 #define FCAN_CTRL_OFFSET 0x00 /* Global control register */ 23 #define FCAN_INTR_OFFSET 0x04 /* Interrupt register */ 24 #define FCAN_ARB_RATE_CTRL_OFFSET 0x08 /* Arbitration rate control register */ 25 #define FCAN_DAT_RATE_CTRL_OFFSET 0x0C /* Data rate control register */ 26 #define FCAN_ACC_ID0_OFFSET 0x10 /* Acceptance identifier0 register */ 27 #define FCAN_ACC_ID1_OFFSET 0x14 /* Acceptance identifier1 register */ 28 #define FCAN_ACC_ID2_OFFSET 0x18 /* Acceptance identifier2 register */ 29 #define FCAN_ACC_ID3_OFFSET 0x1C /* Acceptance identifier3 register */ 30 #define FCAN_ACC_ID0_MASK_OFFSET 0x20 /* Acceptance identifier0 mask register */ 31 #define FCAN_ACC_ID1_MASK_OFFSET 0x24 /* Acceptance identifier1 mask register */ 32 #define FCAN_ACC_ID2_MASK_OFFSET 0x28 /* Acceptance identifier2 mask register */ 33 #define FCAN_ACC_ID3_MASK_OFFSET 0x2C /* Acceptance identifier3 mask register */ 34 #define FCAN_XFER_STS_OFFSET 0x30 /* Transfer status register */ 35 #define FCAN_ERR_CNT_OFFSET 0x34 /* Error counter register */ 36 #define FCAN_FIFO_CNT_OFFSET 0x38 /* FIFO counter register */ 37 #define FCAN_DMA_CTRL_OFFSET 0x3C /* DMA request control register */ 38 #define FCAN_TX_FIFO_OFFSET 0x100 /* TX FIFO shadow register */ 39 #define FCAN_RX_FIFO_OFFSET 0x200 /* RX FIFO shadow register */ 40 41 /*----------------------------------------------------------------------------*/ 42 /* CAN register bit masks - FCAN_<REG>_<BIT>_MASK */ 43 /*----------------------------------------------------------------------------*/ 44 45 /* FCAN_CTRL mask */ 46 #define FCAN_CTRL_XFER_MASK (0x1 << 0) /* RW */ /*Transfer enable*/ 47 #define FCAN_CTRL_TXREQ_MASK (0x1 << 1) /* RW */ /*Transmit request*/ 48 #define FCAN_CTRL_AIME_MASK (0x1 << 2) /* RW */ /*Acceptance identifier mask enable*/ 49 #define FCAN_CTRL_RESET_MASK (0x1 << 6) 50 51 /* FCAN_INTR mask */ 52 #define FCAN_INTR_STATUS_MASK (0xFF << 0) /* RO */ /*the interrupt status*/ 53 #define FCAN_INTR_BOIS_MASK (0x1 << 0) /* RO */ /*Bus off interrupt status*/ 54 #define FCAN_INTR_PWIS_MASK (0x1 << 1) /* RO */ /*Passive warning interrupt status*/ 55 #define FCAN_INTR_PEIS_MASK (0x1 << 2) /* RO */ /*Passive error interrupt status*/ 56 #define FCAN_INTR_RFIS_MASK (0x1 << 3) /* RO */ /*RX FIFO full interrupt status*/ 57 #define FCAN_INTR_TFIS_MASK (0x1 << 4) /* RO */ /*TX FIFO empty interrupt status*/ 58 #define FCAN_INTR_REIS_MASK (0x1 << 5) /* RO */ /*RX frame end interrupt status*/ 59 #define FCAN_INTR_TEIS_MASK (0x1 << 6) /* RO */ /*TX frame end interrupt status*/ 60 #define FCAN_INTR_EIS_MASK (0x1 << 7) /* RO */ /*Error interrupt status*/ 61 62 #define FCAN_INTR_EN_MASK (0xFF << 8) /* RO */ /*the interrupt enable*/ 63 #define FCAN_INTR_BOIE_MASK (0x1 << 8) /* RW */ /*Bus off interrupt enable*/ 64 #define FCAN_INTR_PWIE_MASK (0x1 << 9) /* RW */ /*Passive warning interrupt enable*/ 65 #define FCAN_INTR_PEIE_MASK (0x1 << 10) /* RW */ /*Passive error interrupt enable*/ 66 #define FCAN_INTR_RFIE_MASK (0x1 << 11) /* RW */ /*RX FIFO full interrupt enable*/ 67 #define FCAN_INTR_TFIE_MASK (0x1 << 12) /* RW */ /*TX FIFO empty interrupt enable*/ 68 #define FCAN_INTR_REIE_MASK (0x1 << 13) /* RW */ /*RX frame end interrupt enable*/ 69 #define FCAN_INTR_TEIE_MASK (0x1 << 14) /* RW */ /*TX frame end interrupt enable*/ 70 #define FCAN_INTR_EIE_MASK (0x1 << 15) /* RW */ /*Error interrupt enable*/ 71 72 #define FCAN_INTR_BOIC_MASK (0x1 << 16) /* WO */ /*Bus off interrupt clear*/ 73 #define FCAN_INTR_PWIC_MASK (0x1 << 17) /* WO */ /*Passive warning interrupt clear*/ 74 #define FCAN_INTR_PEIC_MASK (0x1 << 18) /* WO */ /*Passive error interrupt clear*/ 75 #define FCAN_INTR_RFIC_MASK (0x1 << 19) /* WO */ /*RX FIFO full interrupt clear*/ 76 #define FCAN_INTR_TFIC_MASK (0x1 << 20) /* WO */ /*TX FIFO empty interrupt clear*/ 77 #define FCAN_INTR_REIC_MASK (0x1 << 21) /* WO */ /*RX frame end interrupt clear*/ 78 #define FCAN_INTR_TEIC_MASK (0x1 << 22) /* WO */ /*TX frame end interrupt clear*/ 79 #define FCAN_INTR_EIC_MASK (0x1 << 23) /* WO */ /*Error interrupt clear*/ 80 81 /* FCAN_ACC_ID(0-3)_MASK mask */ 82 #define FCAN_ACC_IDN_MASK 0x1FFFFFFF /* WO */ /*don’t care the matching */ 83 /* FCAN_DAT_RATE_CTRL mask */ 84 85 /* FCAN_ERR_CNT_OFFSET mask */ 86 #define FCAN_ERR_CNT_RFN_MASK (0xFF << 0) /* RO */ /*Receive error counter*/ 87 #define FCAN_ERR_CNT_TFN_MASK (0xFF << 16) /* RO */ /*Transmit error counter*/ 88 89 /* FCAN_FIFO_CNT_OFFSET mask */ 90 #define FCAN_FIFO_CNT_RFN_MASK (0xFF << 0) /* RO */ /*Receive FIFO valid data number*/ 91 #define FCAN_FIFO_CNT_TFN_MASK (0xFF << 16) /* RO */ /*Transmit FIFO valid data number*/ 92 93 #define FCAN_ERR_CNT_TFN_SHIFT 16 /* Tx Error Count shift */ 94 #define FCAN_FIFO_CNT_TFN_SHIFT 16 /* Tx FIFO Count shift*/ 95 #define FCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */ 96 #define FCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */ 97 #define FCAN_IDR_SDLC_SHIFT 14 98 #define FCAN_IDR_EDLC_SHIFT 26 99 #define FCAN_ACC_IDN_SHIFT 18 /*Standard ACC ID shift*/ 100 101 #define FCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */ 102 #define FCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ 103 #define FCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ 104 #define FCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ 105 #define FCAN_IDR_RTR_MASK 0x00000001 /* Extended frames remote TX request */ 106 #define FCAN_IDR_DLC_MASK 0x0003C000 /* Standard msg dlc */ 107 #define FCAN_IDR_PAD_MASK 0x00003FFF /* Standard msg padding 1 */ 108 #define FCAN_IDR_EDLC_MASK 0x3C000000 /* Extended msg dlc */ 109 110 /* Can timming */ 111 #define FCAN_TSEG1_MIN 1 112 #define FCAN_TSEG1_MAX 8 113 #define FCAN_TSEG2_MIN 1 114 #define FCAN_TSEG2_MAX 8 115 #define FCAN_SJW_MAX 4 116 #define FCAN_BRP_MIN 1 117 #define FCAN_BRP_MAX 512 118 #define FCAN_BRP_INC 1 119 #define FCAN_CALC_SYNC_SEG 1 120 121 /** 122 * 123 * This macro reads the given register. 124 * 125 * @param BaseAddr is the base address of the device. 126 * @param RegOffset is the register offset to be read. 127 * 128 * @return The 32-bit value of the register 129 * 130 * @note None. 131 * 132 *****************************************************************************/ 133 #define FCan_ReadReg(BaseAddr, RegOffset) \ 134 Ft_in32((BaseAddr) + (u32)(RegOffset)) 135 136 /****************************************************************************/ 137 /** 138 * 139 * This macro writes the given register. 140 * 141 * @param BaseAddr is the base address of the device. 142 * @param RegOffset is the register offset to be written. 143 * @param Data is the 32-bit value to write to the register. 144 * 145 * @return None. 146 * 147 * @note None. 148 * 149 *****************************************************************************/ 150 #define FCan_WriteReg(BaseAddr, RegOffset, Data) \ 151 Ft_out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) 152 153 #define FCan_SetBit(BaseAddr, RegOffset, Data) \ 154 Ft_setBit32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) 155 156 #define FCan_ClearBit(BaseAddr, RegOffset, Data) \ 157 Ft_clearBit32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) 158 159 void FCan_Reset(FCan_t *Can_p); 160 161 #endif // ! 162