1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_FFA_H 10 #define HPM_FFA_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: */ 14 __RW uint32_t STATUS; /* 0x4: */ 15 __RW uint32_t INT_EN; /* 0x8: */ 16 __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ 17 __RW uint32_t FP_CTRL; /* 0x10: */ 18 __RW uint32_t FP_ST; /* 0x14: */ 19 __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ 20 __RW uint32_t OP_CTRL; /* 0x20: */ 21 __RW uint32_t OP_CMD; /* 0x24: */ 22 union { 23 __RW uint32_t OP_REG0; /* 0x28: */ 24 __RW uint32_t OP_FIR_MISC; /* 0x28: */ 25 __RW uint32_t OP_FFT_MISC; /* 0x28: */ 26 }; 27 union { 28 __RW uint32_t OP_REG1; /* 0x2C: */ 29 __RW uint32_t OP_FIR_MISC1; /* 0x2C: */ 30 }; 31 union { 32 __RW uint32_t OP_REG2; /* 0x30: */ 33 __RW uint32_t OP_FFT_INRBUF; /* 0x30: */ 34 }; 35 union { 36 __RW uint32_t OP_REG3; /* 0x34: */ 37 __RW uint32_t OP_FIR_INBUF; /* 0x34: */ 38 }; 39 union { 40 __RW uint32_t OP_REG4; /* 0x38: */ 41 __RW uint32_t OP_FIR_COEFBUF; /* 0x38: */ 42 __RW uint32_t OP_FFT_OUTRBUF; /* 0x38: */ 43 }; 44 union { 45 __RW uint32_t OP_REG5; /* 0x3C: */ 46 __RW uint32_t OP_FIR_OUTBUF; /* 0x3C: */ 47 }; 48 __RW uint32_t OP_REG6; /* 0x40: */ 49 __RW uint32_t OP_REG7; /* 0x44: */ 50 } FFA_Type; 51 52 53 /* Bitfield definition for register: CTRL */ 54 /* 55 * SFTRST (RW) 56 * 57 * software reset the module if asserted to be 1. 58 * EN is only active after this bit is zero. 59 */ 60 #define FFA_CTRL_SFTRST_MASK (0x80000000UL) 61 #define FFA_CTRL_SFTRST_SHIFT (31U) 62 #define FFA_CTRL_SFTRST_SET(x) (((uint32_t)(x) << FFA_CTRL_SFTRST_SHIFT) & FFA_CTRL_SFTRST_MASK) 63 #define FFA_CTRL_SFTRST_GET(x) (((uint32_t)(x) & FFA_CTRL_SFTRST_MASK) >> FFA_CTRL_SFTRST_SHIFT) 64 65 /* 66 * EN (RW) 67 * 68 * Asserted to enable the module 69 */ 70 #define FFA_CTRL_EN_MASK (0x1U) 71 #define FFA_CTRL_EN_SHIFT (0U) 72 #define FFA_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_CTRL_EN_SHIFT) & FFA_CTRL_EN_MASK) 73 #define FFA_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_CTRL_EN_MASK) >> FFA_CTRL_EN_SHIFT) 74 75 /* Bitfield definition for register: STATUS */ 76 /* 77 * FP_NAN (RO) 78 * 79 * Ored together by ( FP_ST[IN_NAN] & FP_CTRL[IN_NAN_IE] ) | ( FP_ST[COEF_NAN] & FP_CTRL[COEF_NAN_IE] ) 80 */ 81 #define FFA_STATUS_FP_NAN_MASK (0x200U) 82 #define FFA_STATUS_FP_NAN_SHIFT (9U) 83 #define FFA_STATUS_FP_NAN_GET(x) (((uint32_t)(x) & FFA_STATUS_FP_NAN_MASK) >> FFA_STATUS_FP_NAN_SHIFT) 84 85 /* 86 * FP_SAT (RO) 87 * 88 * Ored together by ( FP_ST[IN_SAT] & FP_CTRL[IN_SAT_IE] ) | ( FP_ST[COEF_SAT] & FP_CTRL[COEF_SAT_IE] ) 89 */ 90 #define FFA_STATUS_FP_SAT_MASK (0x100U) 91 #define FFA_STATUS_FP_SAT_SHIFT (8U) 92 #define FFA_STATUS_FP_SAT_GET(x) (((uint32_t)(x) & FFA_STATUS_FP_SAT_MASK) >> FFA_STATUS_FP_SAT_SHIFT) 93 94 /* 95 * FIR_OV (W1C) 96 * 97 * FIR Overflow err 98 */ 99 #define FFA_STATUS_FIR_OV_MASK (0x80U) 100 #define FFA_STATUS_FIR_OV_SHIFT (7U) 101 #define FFA_STATUS_FIR_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FIR_OV_SHIFT) & FFA_STATUS_FIR_OV_MASK) 102 #define FFA_STATUS_FIR_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FIR_OV_MASK) >> FFA_STATUS_FIR_OV_SHIFT) 103 104 /* 105 * FFT_OV (W1C) 106 * 107 * FFT Overflow Err 108 */ 109 #define FFA_STATUS_FFT_OV_MASK (0x40U) 110 #define FFA_STATUS_FFT_OV_SHIFT (6U) 111 #define FFA_STATUS_FFT_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FFT_OV_SHIFT) & FFA_STATUS_FFT_OV_MASK) 112 #define FFA_STATUS_FFT_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FFT_OV_MASK) >> FFA_STATUS_FFT_OV_SHIFT) 113 114 /* 115 * WR_ERR (W1C) 116 * 117 * AXI Data Write Error 118 */ 119 #define FFA_STATUS_WR_ERR_MASK (0x20U) 120 #define FFA_STATUS_WR_ERR_SHIFT (5U) 121 #define FFA_STATUS_WR_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_WR_ERR_SHIFT) & FFA_STATUS_WR_ERR_MASK) 122 #define FFA_STATUS_WR_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_WR_ERR_MASK) >> FFA_STATUS_WR_ERR_SHIFT) 123 124 /* 125 * RD_NXT_ERR (W1C) 126 * 127 * AXI Read Bus Error for NXT DATA 128 */ 129 #define FFA_STATUS_RD_NXT_ERR_MASK (0x10U) 130 #define FFA_STATUS_RD_NXT_ERR_SHIFT (4U) 131 #define FFA_STATUS_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_NXT_ERR_SHIFT) & FFA_STATUS_RD_NXT_ERR_MASK) 132 #define FFA_STATUS_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_NXT_ERR_MASK) >> FFA_STATUS_RD_NXT_ERR_SHIFT) 133 134 /* 135 * RD_ERR (W1C) 136 * 137 * AXI Data Read Error 138 */ 139 #define FFA_STATUS_RD_ERR_MASK (0x8U) 140 #define FFA_STATUS_RD_ERR_SHIFT (3U) 141 #define FFA_STATUS_RD_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_ERR_SHIFT) & FFA_STATUS_RD_ERR_MASK) 142 #define FFA_STATUS_RD_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_ERR_MASK) >> FFA_STATUS_RD_ERR_SHIFT) 143 144 /* 145 * NXT_CMD_RD_DONE (W1C) 146 * 147 * Indicate that next command sequence is already read into the module. 148 */ 149 #define FFA_STATUS_NXT_CMD_RD_DONE_MASK (0x2U) 150 #define FFA_STATUS_NXT_CMD_RD_DONE_SHIFT (1U) 151 #define FFA_STATUS_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) 152 #define FFA_STATUS_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) >> FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) 153 154 /* 155 * OP_CMD_DONE (W1C) 156 * 157 * Indicate that operation cmd is done, and data are available in system memory. 158 */ 159 #define FFA_STATUS_OP_CMD_DONE_MASK (0x1U) 160 #define FFA_STATUS_OP_CMD_DONE_SHIFT (0U) 161 #define FFA_STATUS_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_OP_CMD_DONE_SHIFT) & FFA_STATUS_OP_CMD_DONE_MASK) 162 #define FFA_STATUS_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_OP_CMD_DONE_MASK) >> FFA_STATUS_OP_CMD_DONE_SHIFT) 163 164 /* Bitfield definition for register: INT_EN */ 165 /* 166 * WRSV1 (RW) 167 * 168 * Reserved 169 */ 170 #define FFA_INT_EN_WRSV1_MASK (0xFFFFFF00UL) 171 #define FFA_INT_EN_WRSV1_SHIFT (8U) 172 #define FFA_INT_EN_WRSV1_SET(x) (((uint32_t)(x) << FFA_INT_EN_WRSV1_SHIFT) & FFA_INT_EN_WRSV1_MASK) 173 #define FFA_INT_EN_WRSV1_GET(x) (((uint32_t)(x) & FFA_INT_EN_WRSV1_MASK) >> FFA_INT_EN_WRSV1_SHIFT) 174 175 /* 176 * FIR_OV (RW) 177 * 178 * FIR Overflow err 179 */ 180 #define FFA_INT_EN_FIR_OV_MASK (0x80U) 181 #define FFA_INT_EN_FIR_OV_SHIFT (7U) 182 #define FFA_INT_EN_FIR_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FIR_OV_SHIFT) & FFA_INT_EN_FIR_OV_MASK) 183 #define FFA_INT_EN_FIR_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FIR_OV_MASK) >> FFA_INT_EN_FIR_OV_SHIFT) 184 185 /* 186 * FFT_OV (RW) 187 * 188 * FFT Overflow Err 189 */ 190 #define FFA_INT_EN_FFT_OV_MASK (0x40U) 191 #define FFA_INT_EN_FFT_OV_SHIFT (6U) 192 #define FFA_INT_EN_FFT_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FFT_OV_SHIFT) & FFA_INT_EN_FFT_OV_MASK) 193 #define FFA_INT_EN_FFT_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FFT_OV_MASK) >> FFA_INT_EN_FFT_OV_SHIFT) 194 195 /* 196 * WR_ERR (RW) 197 * 198 * Enable Data Write Error interrupt 199 */ 200 #define FFA_INT_EN_WR_ERR_MASK (0x20U) 201 #define FFA_INT_EN_WR_ERR_SHIFT (5U) 202 #define FFA_INT_EN_WR_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_WR_ERR_SHIFT) & FFA_INT_EN_WR_ERR_MASK) 203 #define FFA_INT_EN_WR_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_WR_ERR_MASK) >> FFA_INT_EN_WR_ERR_SHIFT) 204 205 /* 206 * RD_NXT_ERR (RW) 207 * 208 * Enable Read Bus Error for NXT DATA interrupt 209 */ 210 #define FFA_INT_EN_RD_NXT_ERR_MASK (0x10U) 211 #define FFA_INT_EN_RD_NXT_ERR_SHIFT (4U) 212 #define FFA_INT_EN_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_NXT_ERR_SHIFT) & FFA_INT_EN_RD_NXT_ERR_MASK) 213 #define FFA_INT_EN_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_NXT_ERR_MASK) >> FFA_INT_EN_RD_NXT_ERR_SHIFT) 214 215 /* 216 * RD_ERR (RW) 217 * 218 * Enable Data Read Error interrupt 219 */ 220 #define FFA_INT_EN_RD_ERR_MASK (0x8U) 221 #define FFA_INT_EN_RD_ERR_SHIFT (3U) 222 #define FFA_INT_EN_RD_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_ERR_SHIFT) & FFA_INT_EN_RD_ERR_MASK) 223 #define FFA_INT_EN_RD_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_ERR_MASK) >> FFA_INT_EN_RD_ERR_SHIFT) 224 225 /* 226 * NXT_CMD_RD_DONE (RW) 227 * 228 * Indicate that next command sequence is already read into the module. 229 */ 230 #define FFA_INT_EN_NXT_CMD_RD_DONE_MASK (0x2U) 231 #define FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT (1U) 232 #define FFA_INT_EN_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) 233 #define FFA_INT_EN_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) >> FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) 234 235 /* 236 * OP_CMD_DONE (RW) 237 * 238 * Indicate that operation cmd is done, and data are available in system memory. 239 */ 240 #define FFA_INT_EN_OP_CMD_DONE_MASK (0x1U) 241 #define FFA_INT_EN_OP_CMD_DONE_SHIFT (0U) 242 #define FFA_INT_EN_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_OP_CMD_DONE_SHIFT) & FFA_INT_EN_OP_CMD_DONE_MASK) 243 #define FFA_INT_EN_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_OP_CMD_DONE_MASK) >> FFA_INT_EN_OP_CMD_DONE_SHIFT) 244 245 /* Bitfield definition for register: FP_CTRL */ 246 /* 247 * IN_SAT_IE (RW) 248 * 249 * IN_SAT interrupt enable 250 */ 251 #define FFA_FP_CTRL_IN_SAT_IE_MASK (0x80000000UL) 252 #define FFA_FP_CTRL_IN_SAT_IE_SHIFT (31U) 253 #define FFA_FP_CTRL_IN_SAT_IE_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_IN_SAT_IE_SHIFT) & FFA_FP_CTRL_IN_SAT_IE_MASK) 254 #define FFA_FP_CTRL_IN_SAT_IE_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_IN_SAT_IE_MASK) >> FFA_FP_CTRL_IN_SAT_IE_SHIFT) 255 256 /* 257 * COEF_SAT_IE (RW) 258 * 259 * COEF_SAT interrupt enable 260 */ 261 #define FFA_FP_CTRL_COEF_SAT_IE_MASK (0x20000000UL) 262 #define FFA_FP_CTRL_COEF_SAT_IE_SHIFT (29U) 263 #define FFA_FP_CTRL_COEF_SAT_IE_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_COEF_SAT_IE_SHIFT) & FFA_FP_CTRL_COEF_SAT_IE_MASK) 264 #define FFA_FP_CTRL_COEF_SAT_IE_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_COEF_SAT_IE_MASK) >> FFA_FP_CTRL_COEF_SAT_IE_SHIFT) 265 266 /* 267 * IN_NAN_IE (RW) 268 * 269 * IN_NAN interrupt enable 270 */ 271 #define FFA_FP_CTRL_IN_NAN_IE_MASK (0x10000000UL) 272 #define FFA_FP_CTRL_IN_NAN_IE_SHIFT (28U) 273 #define FFA_FP_CTRL_IN_NAN_IE_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_IN_NAN_IE_SHIFT) & FFA_FP_CTRL_IN_NAN_IE_MASK) 274 #define FFA_FP_CTRL_IN_NAN_IE_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_IN_NAN_IE_MASK) >> FFA_FP_CTRL_IN_NAN_IE_SHIFT) 275 276 /* 277 * COEF_NAN_IE (RW) 278 * 279 * COEF_NAN interrupt enable 280 */ 281 #define FFA_FP_CTRL_COEF_NAN_IE_MASK (0x8000000UL) 282 #define FFA_FP_CTRL_COEF_NAN_IE_SHIFT (27U) 283 #define FFA_FP_CTRL_COEF_NAN_IE_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_COEF_NAN_IE_SHIFT) & FFA_FP_CTRL_COEF_NAN_IE_MASK) 284 #define FFA_FP_CTRL_COEF_NAN_IE_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_COEF_NAN_IE_MASK) >> FFA_FP_CTRL_COEF_NAN_IE_SHIFT) 285 286 /* 287 * EXP_ST_SEL (RW) 288 * 289 * 2'b00: exp for input data 290 * 2'b01: exp for output data 291 * 2'b10: exp for coef data 292 */ 293 #define FFA_FP_CTRL_EXP_ST_SEL_MASK (0x6000000UL) 294 #define FFA_FP_CTRL_EXP_ST_SEL_SHIFT (25U) 295 #define FFA_FP_CTRL_EXP_ST_SEL_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_EXP_ST_SEL_SHIFT) & FFA_FP_CTRL_EXP_ST_SEL_MASK) 296 #define FFA_FP_CTRL_EXP_ST_SEL_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_EXP_ST_SEL_MASK) >> FFA_FP_CTRL_EXP_ST_SEL_SHIFT) 297 298 /* 299 * OPT_BIAS_EXP (RW) 300 * 301 * Asserted to use biased exp as exp input and exp output 302 */ 303 #define FFA_FP_CTRL_OPT_BIAS_EXP_MASK (0x1000000UL) 304 #define FFA_FP_CTRL_OPT_BIAS_EXP_SHIFT (24U) 305 #define FFA_FP_CTRL_OPT_BIAS_EXP_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_OPT_BIAS_EXP_SHIFT) & FFA_FP_CTRL_OPT_BIAS_EXP_MASK) 306 #define FFA_FP_CTRL_OPT_BIAS_EXP_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_OPT_BIAS_EXP_MASK) >> FFA_FP_CTRL_OPT_BIAS_EXP_SHIFT) 307 308 /* 309 * COEF_MAX (RW) 310 * 311 * The coef max exp for float. When used as float input, this field must be configured. The absolute value of coefficients should be smalller than pow(2, (COEF_MAX+1)). So this suggested value is (ceil(log2(fabs(coef[])))-1). 312 */ 313 #define FFA_FP_CTRL_COEF_MAX_MASK (0xFF0000UL) 314 #define FFA_FP_CTRL_COEF_MAX_SHIFT (16U) 315 #define FFA_FP_CTRL_COEF_MAX_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_COEF_MAX_SHIFT) & FFA_FP_CTRL_COEF_MAX_MASK) 316 #define FFA_FP_CTRL_COEF_MAX_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_COEF_MAX_MASK) >> FFA_FP_CTRL_COEF_MAX_SHIFT) 317 318 /* 319 * OUT_MAX (RW) 320 * 321 * The output max exp for float. When used as float output, this field must be configured. The absolute value of output data should be smalller than pow(2, (OUT_MAX+1)). So this suggested value is (ceil(log2(fabs(out[])))-1). 322 */ 323 #define FFA_FP_CTRL_OUT_MAX_MASK (0xFF00U) 324 #define FFA_FP_CTRL_OUT_MAX_SHIFT (8U) 325 #define FFA_FP_CTRL_OUT_MAX_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_OUT_MAX_SHIFT) & FFA_FP_CTRL_OUT_MAX_MASK) 326 #define FFA_FP_CTRL_OUT_MAX_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_OUT_MAX_MASK) >> FFA_FP_CTRL_OUT_MAX_SHIFT) 327 328 /* 329 * IN_MAX (RW) 330 * 331 * The input max exp for float. When used as float input, this field must be configured. The absolute value of input data should be smalller than pow(2, (IN_MAX+1)). So this suggested value is (ceil(log2(fabs(in[])))-1). 332 */ 333 #define FFA_FP_CTRL_IN_MAX_MASK (0xFFU) 334 #define FFA_FP_CTRL_IN_MAX_SHIFT (0U) 335 #define FFA_FP_CTRL_IN_MAX_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_IN_MAX_SHIFT) & FFA_FP_CTRL_IN_MAX_MASK) 336 #define FFA_FP_CTRL_IN_MAX_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_IN_MAX_MASK) >> FFA_FP_CTRL_IN_MAX_SHIFT) 337 338 /* Bitfield definition for register: FP_ST */ 339 /* 340 * IN_SAT (W1C) 341 * 342 * the float input is saturated when converted from float to fix due to small FLT_CTRL[IN_MAX]. 343 */ 344 #define FFA_FP_ST_IN_SAT_MASK (0x80000000UL) 345 #define FFA_FP_ST_IN_SAT_SHIFT (31U) 346 #define FFA_FP_ST_IN_SAT_SET(x) (((uint32_t)(x) << FFA_FP_ST_IN_SAT_SHIFT) & FFA_FP_ST_IN_SAT_MASK) 347 #define FFA_FP_ST_IN_SAT_GET(x) (((uint32_t)(x) & FFA_FP_ST_IN_SAT_MASK) >> FFA_FP_ST_IN_SAT_SHIFT) 348 349 /* 350 * COEF_SAT (W1C) 351 * 352 * the float coef is saturated when converted from float to fix due to small FLT_CTRL[COEF_MAX]. 353 */ 354 #define FFA_FP_ST_COEF_SAT_MASK (0x20000000UL) 355 #define FFA_FP_ST_COEF_SAT_SHIFT (29U) 356 #define FFA_FP_ST_COEF_SAT_SET(x) (((uint32_t)(x) << FFA_FP_ST_COEF_SAT_SHIFT) & FFA_FP_ST_COEF_SAT_MASK) 357 #define FFA_FP_ST_COEF_SAT_GET(x) (((uint32_t)(x) & FFA_FP_ST_COEF_SAT_MASK) >> FFA_FP_ST_COEF_SAT_SHIFT) 358 359 /* 360 * IN_NAN (W1C) 361 * 362 * IN_NAN found 363 */ 364 #define FFA_FP_ST_IN_NAN_MASK (0x10000000UL) 365 #define FFA_FP_ST_IN_NAN_SHIFT (28U) 366 #define FFA_FP_ST_IN_NAN_SET(x) (((uint32_t)(x) << FFA_FP_ST_IN_NAN_SHIFT) & FFA_FP_ST_IN_NAN_MASK) 367 #define FFA_FP_ST_IN_NAN_GET(x) (((uint32_t)(x) & FFA_FP_ST_IN_NAN_MASK) >> FFA_FP_ST_IN_NAN_SHIFT) 368 369 /* 370 * COEF_NAN (W1C) 371 * 372 * COEF_NAN found 373 */ 374 #define FFA_FP_ST_COEF_NAN_MASK (0x8000000UL) 375 #define FFA_FP_ST_COEF_NAN_SHIFT (27U) 376 #define FFA_FP_ST_COEF_NAN_SET(x) (((uint32_t)(x) << FFA_FP_ST_COEF_NAN_SHIFT) & FFA_FP_ST_COEF_NAN_MASK) 377 #define FFA_FP_ST_COEF_NAN_GET(x) (((uint32_t)(x) & FFA_FP_ST_COEF_NAN_MASK) >> FFA_FP_ST_COEF_NAN_SHIFT) 378 379 /* 380 * EXP_MAX (RO) 381 * 382 * The max exp for float 383 */ 384 #define FFA_FP_ST_EXP_MAX_MASK (0xFF00U) 385 #define FFA_FP_ST_EXP_MAX_SHIFT (8U) 386 #define FFA_FP_ST_EXP_MAX_GET(x) (((uint32_t)(x) & FFA_FP_ST_EXP_MAX_MASK) >> FFA_FP_ST_EXP_MAX_SHIFT) 387 388 /* 389 * EXP_MIN (RO) 390 * 391 * The min exp for float 392 */ 393 #define FFA_FP_ST_EXP_MIN_MASK (0xFFU) 394 #define FFA_FP_ST_EXP_MIN_SHIFT (0U) 395 #define FFA_FP_ST_EXP_MIN_GET(x) (((uint32_t)(x) & FFA_FP_ST_EXP_MIN_MASK) >> FFA_FP_ST_EXP_MIN_SHIFT) 396 397 /* Bitfield definition for register: OP_CTRL */ 398 /* 399 * NXT_ADDR (RW) 400 * 401 * The address for the next command. 402 * It will be processed after CUR_CMD is executed and done.. 403 */ 404 #define FFA_OP_CTRL_NXT_ADDR_MASK (0xFFFFFFFCUL) 405 #define FFA_OP_CTRL_NXT_ADDR_SHIFT (2U) 406 #define FFA_OP_CTRL_NXT_ADDR_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_ADDR_SHIFT) & FFA_OP_CTRL_NXT_ADDR_MASK) 407 #define FFA_OP_CTRL_NXT_ADDR_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_ADDR_MASK) >> FFA_OP_CTRL_NXT_ADDR_SHIFT) 408 409 /* 410 * NXT_EN (RW) 411 * 412 * Whether NXT_CMD is enabled. 413 * Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. 414 */ 415 #define FFA_OP_CTRL_NXT_EN_MASK (0x2U) 416 #define FFA_OP_CTRL_NXT_EN_SHIFT (1U) 417 #define FFA_OP_CTRL_NXT_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_EN_SHIFT) & FFA_OP_CTRL_NXT_EN_MASK) 418 #define FFA_OP_CTRL_NXT_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_EN_MASK) >> FFA_OP_CTRL_NXT_EN_SHIFT) 419 420 /* 421 * EN (RW) 422 * 423 * Whether CUR_CMD is enabled. 424 * Asserted to enable the CUR_CMD 425 */ 426 #define FFA_OP_CTRL_EN_MASK (0x1U) 427 #define FFA_OP_CTRL_EN_SHIFT (0U) 428 #define FFA_OP_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_EN_SHIFT) & FFA_OP_CTRL_EN_MASK) 429 #define FFA_OP_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_EN_MASK) >> FFA_OP_CTRL_EN_SHIFT) 430 431 /* Bitfield definition for register: OP_CMD */ 432 /* 433 * CONJ_C (RW) 434 * 435 * asserted to have conjuate value for coefs in computation 436 */ 437 #define FFA_OP_CMD_CONJ_C_MASK (0x1000000UL) 438 #define FFA_OP_CMD_CONJ_C_SHIFT (24U) 439 #define FFA_OP_CMD_CONJ_C_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CONJ_C_SHIFT) & FFA_OP_CMD_CONJ_C_MASK) 440 #define FFA_OP_CMD_CONJ_C_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CONJ_C_MASK) >> FFA_OP_CMD_CONJ_C_SHIFT) 441 442 /* 443 * CMD (RW) 444 * 445 * The Command Used: 446 * 0: FIR 447 * 2: FFT 448 * Others: Reserved 449 */ 450 #define FFA_OP_CMD_CMD_MASK (0xFC0000UL) 451 #define FFA_OP_CMD_CMD_SHIFT (18U) 452 #define FFA_OP_CMD_CMD_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CMD_SHIFT) & FFA_OP_CMD_CMD_MASK) 453 #define FFA_OP_CMD_CMD_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CMD_MASK) >> FFA_OP_CMD_CMD_SHIFT) 454 455 /* 456 * OUTD_TYPE (RW) 457 * 458 * Output data type: 459 * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 460 * 4:complex sp float 5: real sp float 461 */ 462 #define FFA_OP_CMD_OUTD_TYPE_MASK (0x38000UL) 463 #define FFA_OP_CMD_OUTD_TYPE_SHIFT (15U) 464 #define FFA_OP_CMD_OUTD_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_OUTD_TYPE_SHIFT) & FFA_OP_CMD_OUTD_TYPE_MASK) 465 #define FFA_OP_CMD_OUTD_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_OUTD_TYPE_MASK) >> FFA_OP_CMD_OUTD_TYPE_SHIFT) 466 467 /* 468 * COEF_TYPE (RW) 469 * 470 * Coef data type (used for FIR): 471 * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 472 * 4:complex sp float 5: real sp float 473 */ 474 #define FFA_OP_CMD_COEF_TYPE_MASK (0x7000U) 475 #define FFA_OP_CMD_COEF_TYPE_SHIFT (12U) 476 #define FFA_OP_CMD_COEF_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_COEF_TYPE_SHIFT) & FFA_OP_CMD_COEF_TYPE_MASK) 477 #define FFA_OP_CMD_COEF_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_COEF_TYPE_MASK) >> FFA_OP_CMD_COEF_TYPE_SHIFT) 478 479 /* 480 * IND_TYPE (RW) 481 * 482 * Input data type: 483 * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 484 * 4:complex sp float 5: real sp float 485 */ 486 #define FFA_OP_CMD_IND_TYPE_MASK (0xE00U) 487 #define FFA_OP_CMD_IND_TYPE_SHIFT (9U) 488 #define FFA_OP_CMD_IND_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_IND_TYPE_SHIFT) & FFA_OP_CMD_IND_TYPE_MASK) 489 #define FFA_OP_CMD_IND_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_IND_TYPE_MASK) >> FFA_OP_CMD_IND_TYPE_SHIFT) 490 491 /* 492 * NXT_CMD_LEN (RW) 493 * 494 * The length of nxt commands in 32-bit words 495 */ 496 #define FFA_OP_CMD_NXT_CMD_LEN_MASK (0xFFU) 497 #define FFA_OP_CMD_NXT_CMD_LEN_SHIFT (0U) 498 #define FFA_OP_CMD_NXT_CMD_LEN_SET(x) (((uint32_t)(x) << FFA_OP_CMD_NXT_CMD_LEN_SHIFT) & FFA_OP_CMD_NXT_CMD_LEN_MASK) 499 #define FFA_OP_CMD_NXT_CMD_LEN_GET(x) (((uint32_t)(x) & FFA_OP_CMD_NXT_CMD_LEN_MASK) >> FFA_OP_CMD_NXT_CMD_LEN_SHIFT) 500 501 /* Bitfield definition for register: OP_REG0 */ 502 /* 503 * CT (RW) 504 * 505 * Contents 506 */ 507 #define FFA_OP_REG0_CT_MASK (0xFFFFFFFFUL) 508 #define FFA_OP_REG0_CT_SHIFT (0U) 509 #define FFA_OP_REG0_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG0_CT_SHIFT) & FFA_OP_REG0_CT_MASK) 510 #define FFA_OP_REG0_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG0_CT_MASK) >> FFA_OP_REG0_CT_SHIFT) 511 512 /* Bitfield definition for register: OP_FIR_MISC */ 513 /* 514 * FIR_COEF_TAPS (RW) 515 * 516 * Length of FIR coefs （max 256） 517 */ 518 #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK (0x3FFFU) 519 #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT (0U) 520 #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) 521 #define FFA_OP_FIR_MISC_FIR_COEF_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) >> FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) 522 523 /* Bitfield definition for register: OP_FFT_MISC */ 524 /* 525 * FFT_LEN (RW) 526 * 527 * FFT length 528 * 0:8, 529 * ..., 530 * n:2^(3+n) 531 */ 532 #define FFA_OP_FFT_MISC_FFT_LEN_MASK (0x780U) 533 #define FFA_OP_FFT_MISC_FFT_LEN_SHIFT (7U) 534 #define FFA_OP_FFT_MISC_FFT_LEN_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_FFT_LEN_SHIFT) & FFA_OP_FFT_MISC_FFT_LEN_MASK) 535 #define FFA_OP_FFT_MISC_FFT_LEN_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_FFT_LEN_MASK) >> FFA_OP_FFT_MISC_FFT_LEN_SHIFT) 536 537 /* 538 * IFFT (RW) 539 * 540 * Asserted to indicate IFFT 541 */ 542 #define FFA_OP_FFT_MISC_IFFT_MASK (0x40U) 543 #define FFA_OP_FFT_MISC_IFFT_SHIFT (6U) 544 #define FFA_OP_FFT_MISC_IFFT_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IFFT_SHIFT) & FFA_OP_FFT_MISC_IFFT_MASK) 545 #define FFA_OP_FFT_MISC_IFFT_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IFFT_MASK) >> FFA_OP_FFT_MISC_IFFT_SHIFT) 546 547 /* 548 * TMP_BLK (RW) 549 * 550 * Memory block for indata. Should be assigned as 1 551 */ 552 #define FFA_OP_FFT_MISC_TMP_BLK_MASK (0xCU) 553 #define FFA_OP_FFT_MISC_TMP_BLK_SHIFT (2U) 554 #define FFA_OP_FFT_MISC_TMP_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_TMP_BLK_SHIFT) & FFA_OP_FFT_MISC_TMP_BLK_MASK) 555 #define FFA_OP_FFT_MISC_TMP_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_TMP_BLK_MASK) >> FFA_OP_FFT_MISC_TMP_BLK_SHIFT) 556 557 /* 558 * IND_BLK (RW) 559 * 560 * Memory block for indata. Should be assigned as 0 561 */ 562 #define FFA_OP_FFT_MISC_IND_BLK_MASK (0x3U) 563 #define FFA_OP_FFT_MISC_IND_BLK_SHIFT (0U) 564 #define FFA_OP_FFT_MISC_IND_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IND_BLK_SHIFT) & FFA_OP_FFT_MISC_IND_BLK_MASK) 565 #define FFA_OP_FFT_MISC_IND_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IND_BLK_MASK) >> FFA_OP_FFT_MISC_IND_BLK_SHIFT) 566 567 /* Bitfield definition for register: OP_REG1 */ 568 /* 569 * CT (RW) 570 * 571 * Contents 572 */ 573 #define FFA_OP_REG1_CT_MASK (0xFFFFFFFFUL) 574 #define FFA_OP_REG1_CT_SHIFT (0U) 575 #define FFA_OP_REG1_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG1_CT_SHIFT) & FFA_OP_REG1_CT_MASK) 576 #define FFA_OP_REG1_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG1_CT_MASK) >> FFA_OP_REG1_CT_SHIFT) 577 578 /* Bitfield definition for register: OP_FIR_MISC1 */ 579 /* 580 * OUTD_MEM_BLK (RW) 581 * 582 * Should be assigned as 0 583 */ 584 #define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK (0x300000UL) 585 #define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT (20U) 586 #define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) 587 #define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) 588 589 /* 590 * COEF_MEM_BLK (RW) 591 * 592 * Should be assigned as 1 593 */ 594 #define FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK (0xC0000UL) 595 #define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT (18U) 596 #define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) 597 #define FFA_OP_FIR_MISC1_COEF_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) 598 599 /* 600 * IND_MEM_BLK (RW) 601 * 602 * Should be assigned as 2 603 */ 604 #define FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK (0x30000UL) 605 #define FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT (16U) 606 #define FFA_OP_FIR_MISC1_IND_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) 607 #define FFA_OP_FIR_MISC1_IND_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) 608 609 /* 610 * FIR_DATA_TAPS (RW) 611 * 612 * The input data data length 613 */ 614 #define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK (0xFFFFU) 615 #define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT (0U) 616 #define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) 617 #define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) >> FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) 618 619 /* Bitfield definition for register: OP_REG2 */ 620 /* 621 * CT (RW) 622 * 623 * Contents 624 */ 625 #define FFA_OP_REG2_CT_MASK (0xFFFFFFFFUL) 626 #define FFA_OP_REG2_CT_SHIFT (0U) 627 #define FFA_OP_REG2_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG2_CT_SHIFT) & FFA_OP_REG2_CT_MASK) 628 #define FFA_OP_REG2_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG2_CT_MASK) >> FFA_OP_REG2_CT_SHIFT) 629 630 /* Bitfield definition for register: OP_FFT_INRBUF */ 631 /* 632 * LOC (RW) 633 * 634 * The input (real) data buffer pointer 635 */ 636 #define FFA_OP_FFT_INRBUF_LOC_MASK (0xFFFFFFFFUL) 637 #define FFA_OP_FFT_INRBUF_LOC_SHIFT (0U) 638 #define FFA_OP_FFT_INRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_INRBUF_LOC_SHIFT) & FFA_OP_FFT_INRBUF_LOC_MASK) 639 #define FFA_OP_FFT_INRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_INRBUF_LOC_MASK) >> FFA_OP_FFT_INRBUF_LOC_SHIFT) 640 641 /* Bitfield definition for register: OP_REG3 */ 642 /* 643 * CT (RW) 644 * 645 * Contents 646 */ 647 #define FFA_OP_REG3_CT_MASK (0xFFFFFFFFUL) 648 #define FFA_OP_REG3_CT_SHIFT (0U) 649 #define FFA_OP_REG3_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG3_CT_SHIFT) & FFA_OP_REG3_CT_MASK) 650 #define FFA_OP_REG3_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG3_CT_MASK) >> FFA_OP_REG3_CT_SHIFT) 651 652 /* Bitfield definition for register: OP_FIR_INBUF */ 653 /* 654 * LOC (RW) 655 * 656 * The input data buffer pointer 657 */ 658 #define FFA_OP_FIR_INBUF_LOC_MASK (0xFFFFFFFFUL) 659 #define FFA_OP_FIR_INBUF_LOC_SHIFT (0U) 660 #define FFA_OP_FIR_INBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_INBUF_LOC_SHIFT) & FFA_OP_FIR_INBUF_LOC_MASK) 661 #define FFA_OP_FIR_INBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_INBUF_LOC_MASK) >> FFA_OP_FIR_INBUF_LOC_SHIFT) 662 663 /* Bitfield definition for register: OP_REG4 */ 664 /* 665 * CT (RW) 666 * 667 * Contents 668 */ 669 #define FFA_OP_REG4_CT_MASK (0xFFFFFFFFUL) 670 #define FFA_OP_REG4_CT_SHIFT (0U) 671 #define FFA_OP_REG4_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG4_CT_SHIFT) & FFA_OP_REG4_CT_MASK) 672 #define FFA_OP_REG4_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG4_CT_MASK) >> FFA_OP_REG4_CT_SHIFT) 673 674 /* Bitfield definition for register: OP_FIR_COEFBUF */ 675 /* 676 * LOC (RW) 677 * 678 * The coef buf pointer 679 */ 680 #define FFA_OP_FIR_COEFBUF_LOC_MASK (0xFFFFFFFFUL) 681 #define FFA_OP_FIR_COEFBUF_LOC_SHIFT (0U) 682 #define FFA_OP_FIR_COEFBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_COEFBUF_LOC_SHIFT) & FFA_OP_FIR_COEFBUF_LOC_MASK) 683 #define FFA_OP_FIR_COEFBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_COEFBUF_LOC_MASK) >> FFA_OP_FIR_COEFBUF_LOC_SHIFT) 684 685 /* Bitfield definition for register: OP_FFT_OUTRBUF */ 686 /* 687 * LOC (RW) 688 * 689 * The output (real) data buffer pointer 690 */ 691 #define FFA_OP_FFT_OUTRBUF_LOC_MASK (0xFFFFFFFFUL) 692 #define FFA_OP_FFT_OUTRBUF_LOC_SHIFT (0U) 693 #define FFA_OP_FFT_OUTRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_OUTRBUF_LOC_SHIFT) & FFA_OP_FFT_OUTRBUF_LOC_MASK) 694 #define FFA_OP_FFT_OUTRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_OUTRBUF_LOC_MASK) >> FFA_OP_FFT_OUTRBUF_LOC_SHIFT) 695 696 /* Bitfield definition for register: OP_REG5 */ 697 /* 698 * CT (RW) 699 * 700 * Contents 701 */ 702 #define FFA_OP_REG5_CT_MASK (0xFFFFFFFFUL) 703 #define FFA_OP_REG5_CT_SHIFT (0U) 704 #define FFA_OP_REG5_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG5_CT_SHIFT) & FFA_OP_REG5_CT_MASK) 705 #define FFA_OP_REG5_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG5_CT_MASK) >> FFA_OP_REG5_CT_SHIFT) 706 707 /* Bitfield definition for register: OP_FIR_OUTBUF */ 708 /* 709 * LOC (RW) 710 * 711 * The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） 712 */ 713 #define FFA_OP_FIR_OUTBUF_LOC_MASK (0xFFFFFFFFUL) 714 #define FFA_OP_FIR_OUTBUF_LOC_SHIFT (0U) 715 #define FFA_OP_FIR_OUTBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_OUTBUF_LOC_SHIFT) & FFA_OP_FIR_OUTBUF_LOC_MASK) 716 #define FFA_OP_FIR_OUTBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_OUTBUF_LOC_MASK) >> FFA_OP_FIR_OUTBUF_LOC_SHIFT) 717 718 /* Bitfield definition for register: OP_REG6 */ 719 /* 720 * CT (RW) 721 * 722 * Contents 723 */ 724 #define FFA_OP_REG6_CT_MASK (0xFFFFFFFFUL) 725 #define FFA_OP_REG6_CT_SHIFT (0U) 726 #define FFA_OP_REG6_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG6_CT_SHIFT) & FFA_OP_REG6_CT_MASK) 727 #define FFA_OP_REG6_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG6_CT_MASK) >> FFA_OP_REG6_CT_SHIFT) 728 729 /* Bitfield definition for register: OP_REG7 */ 730 /* 731 * CT (RW) 732 * 733 * Contents 734 */ 735 #define FFA_OP_REG7_CT_MASK (0xFFFFFFFFUL) 736 #define FFA_OP_REG7_CT_SHIFT (0U) 737 #define FFA_OP_REG7_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG7_CT_SHIFT) & FFA_OP_REG7_CT_MASK) 738 #define FFA_OP_REG7_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG7_CT_MASK) >> FFA_OP_REG7_CT_SHIFT) 739 740 741 742 743 #endif /* HPM_FFA_H */ 744