1 /* 2 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0. 5 * 6 * @Date: 2021-04-05 21:31:10 7 * @LastEditTime: 2021-04-05 21:31:10 8 * @Description: Description of file 9 * @Modify History: 10 * * * Ver Who Date Changes 11 * * ----- ------ -------- -------------------------------------- 12 * * v1.0 hh 2021-04-05 init 13 */ 14 15 #ifndef FT_QSPI_H 16 #define FT_QSPI_H 17 18 #ifdef __cplusplus 19 extern "C" 20 { 21 #endif 22 23 #include "ft_types.h" 24 #include "ft_error_code.h" 25 26 #define FQSPI_SUCCESS FST_SUCCESS /* SUCCESS */ 27 #define FQSPI_FAILURE FT_MAKE_ERRCODE(errQspi, errBspGeneral, FST_FAILURE) /* Normal */ 28 #define FQSPI_TIMEOUT FT_MAKE_ERRCODE(errQspi, errBspGeneral, FST_TIMEOUT) /* Timeout */ 29 #define FQSPI_EILSEQ FT_MAKE_ERRCODE(errQspi, errBspGeneral, FST_EILSEQ) /* Illegal byte sequence. */ 30 #define FQSPI_INVALID_PARAM FT_MAKE_ERRCODE(errQspi, errBspGeneral, FST_INVALID_PARAM) /* Invalid param. */ 31 32 /* qspi bsp command instruction operation */ 33 #define FQSPI_CMD_NEED_ADDR_MASK 0x1U 34 #define FQSPI_CMD_NEED_DUMMY_MASK 0x2U 35 #define FQSPI_CMD_NEED_GET_MASK 0x4U 36 #define FQSPI_CMD_NEED_SET_MASK 0x08U 37 #define FQSPI_CMD_ADDRESS_3BYTE_MASK 0x10U 38 #define FQSPI_CMD_ADDRESS_4BYTE_MASK 0x20U 39 40 /* qspi cmd of transfer operation */ 41 #define FQSPI_DATA_NEED_DUMMY_MASK 0x1U 42 #define FQSPI_DATA_ADDRESS_3BYTE_MASK 0x2U 43 #define FQSPI_DATA_ADDRESS_4BYTE_MASK 0x4U 44 45 #define FQSPI_FLASH_CMD_WRR 0x01 /* Write status register */ 46 #define FQSPI_FLASH_CMD_PP 0x02 /* Page program */ 47 #define FQSPI_FLASH_CMD_READ 0x03 /* Normal read data bytes */ 48 #define FQSPI_FLASH_CMD_WRDI 0x04 /* Write disable */ 49 #define FQSPI_FLASH_CMD_RDSR1 0x05 /* Read status register */ 50 #define FQSPI_FLASH_CMD_WREN 0x06 /* Write enable */ 51 #define FQSPI_FLASH_CMD_RDSR2 0x07 /* Read status register */ 52 #define FQSPI_FLASH_CMD_FAST_READ 0x0B /* Fast read data bytes */ 53 #define FQSPI_FLASH_CMD_4FAST_READ 0x0C /* Fast read data bytes */ 54 #define FQSPI_FLASH_CMD_4PP 0x12 /* Page program */ 55 #define FQSPI_FLASH_CMD_4READ 0x13 /* Normal read data bytes */ 56 #define FQSPI_FLASH_CMD_P4E 0x20 /* Erase 4kb sector */ 57 #define FQSPI_FLASH_CMD_4P4E 0x21 /* Erase 4kb sector */ 58 #define FQSPI_FLASH_CMD_QPP 0x32 /* Quad Page program */ 59 #define FQSPI_FLASH_CMD_4QPP 0x34 /* Quad Page program */ 60 #define FQSPI_FLASH_CMD_RDCR 0x35 /* Read config register */ 61 #define FQSPI_FLASH_CMD_BE 0x60 /* Bulk erase */ 62 #define FQSPI_FLASH_CMD_RDAR 0x65 /* Read Any Register */ 63 #define FQSPI_FLASH_CMD_QOR 0x6B /* Quad read data bytes */ 64 #define FQSPI_FLASH_CMD_4QOR 0x6C /* Quad read data bytes */ 65 #define FQSPI_FLASH_CMD_WRAR 0x71 /* Write Any Register */ 66 #define FQSPI_FLASH_CMD_RDID 0x9F /* Read JEDEC ID */ 67 #define FQSPI_FLASH_CMD_4BAM 0xB7 /* Enter 4 Bytes Mode */ 68 #define FQSPI_FLASH_CMD_4BE 0xC7 /* Bulk erase */ 69 #define FQSPI_FLASH_CMD_SE 0xD8 /* Sector erase */ 70 #define FQSPI_FLASH_CMD_4SE 0xDC /* Sector erase */ 71 #define FQSPI_FLASH_CMD_4BEX 0xE9 /* Exit 4 Bytes Mode */ 72 #define FQSPI_FLASH_CMD_QIOR 0xEB /* Quad read data bytes */ 73 #define FQSPI_FLASH_CMD_4QIOR 0xEC /* Quad read data bytes */ 74 #define FQSPI_FLASH_DISCOVERABLE_PARAMETER 0x5a 75 #define FQSPI_CMD_ENABLE_RESET 0x66 76 #define FQSPI_CMD_RESET 0x99 77 78 struct FQSpi_DataPack 79 { 80 u32 flags; /* Follow qspi cmd of transfer operation */ 81 u32 cmd; /* Command instruction */ 82 u32 addr; /* Flash address */ 83 u32 dummyCycle; /* dummy Cycle */ 84 const u8 *txBuf; 85 u8 *rxBuf; /* Need send or read buffer */ 86 u32 length; /* Buffer length */ 87 }; 88 89 struct FQSpi_CmdPack 90 { 91 u32 flags; /* Follow qspi bsp command instruction operation */ 92 u32 cmd; /* Command instruction */ 93 u32 addr; /* Command address */ 94 u32 dummyCycle; /* dummy Cycle */ 95 const u8 *txBuf; 96 u8 *rxBuf; /* Need send or read buffer */ 97 u32 length; /* Buffer length */ 98 }; 99 100 typedef struct 101 { 102 u32 instanceId; /* Id of device */ 103 uintptr_t baseAddress; /* Base address of qspi */ 104 u32 transMode; /* Transfer mode */ 105 u32 capacity; /* Flash capacity */ 106 u32 addrMode; /**/ 107 u32 clkDiv; 108 u32 qspiDevNum; /*Qspi device number */ 109 u32 channel; /* Cs number */ 110 u32 bitWidth; /* Transfer unit width */ 111 } FQSpi_Config_t; 112 113 typedef struct 114 { 115 FQSpi_Config_t config; 116 u32 isReady; /**< Device is initialized and ready */ 117 118 } FQSpi_t; 119 120 /** 121 * @name: FQSpi_LookupConfig 122 * @msg: FQSpi_LookupConfig returns a reference FQSpi_Config_t structure based on the 123 * unique device id. 124 * @in param {u32} instanceId : unique device 125 * @return {FQSpi_Config_t} FQSpi_Config_t is a reference to a config record in the configuration 126 * table (in qspi_g.c) corresponding to <i>instanceId</i>, or NULL if no match is found. 127 */ 128 FQSpi_Config_t *FQSpi_LookupConfig(u32 instanceId); 129 130 /** 131 * @name: FQSpi_CfgInitialize 132 * @msg: This function intializes the configuration for the qspi instance 133 * @in param {FQSpi_t *} pQspi: A pointer to the qspi instance 134 * @in param {FQSpi_Config_t *} pConfig: A pointer to the qspi instance config record 135 * @return {ft_error_t} 136 */ 137 ft_error_t FQSpi_CfgInitialize(FQSpi_t *pQspi, FQSpi_Config_t *pConfig); 138 139 /** 140 * @name: FQSpi_CmdOperation 141 * @msg: This function send command instruction by the struct FQSpi_CmdPack 142 * @in param {FQSpi_t *} pQspi: A pointer to the qspi instance 143 * @in param {struct FQSpi_CmdPack *} pCmdPack: Need to send command instruction package 144 * @return {ft_error_t} 145 */ 146 ft_error_t FQSpi_CmdOperation(FQSpi_t *pQspi, struct FQSpi_CmdPack *pCmdPack); 147 148 /** 149 * @name: FQSpi_Read 150 * @msg: This function reads flash data from a specific address by {struct FQSpi_DataPack} 151 * @in param {FQSpi_t *} pQspi: A pointer to the qspi instance 152 * @in param {struct FQSpi_DataPack *} pDataPack: Need to read data package 153 * @return {ft_error_t} 154 */ 155 ft_error_t FQSpi_Read(FQSpi_t *pQspi, struct FQSpi_DataPack *pDataPack); 156 157 /** 158 * @name: FQSpi_Write 159 * @msg: This function writes data from a specific address by {struct FQSpi_DataPack} 160 * @in param {FQSpi_t *} pQspi: A pointer to the qspi instance 161 * @in param {struct FQSpi_DataPack *} pDataPack: Need to read data package 162 * @return {ft_error_t} 163 */ 164 ft_error_t FQSpi_Write(FQSpi_t *pQspi, struct FQSpi_DataPack *pDataPack); 165 166 /** 167 * @name: FQSpi_FlashRegSet 168 * @msg: This function sends command instruction with specific parameters 169 * @in param {FQSpi_t *} pQspi: A pointer to the qspi instance 170 * @in param {FT_IN u8} cmd: Command instruction 171 * @in param {FT_IN u8 *} writebuf: Data that needs to be sent through command instruction registers 172 * @in param {u32} length: Data length 173 * @return {ft_error_t} 174 */ 175 ft_error_t FQSpi_FlashRegSet(FQSpi_t *pQspi, 176 FT_IN u8 cmd, 177 FT_IN u8 *writebuf, 178 u32 length); 179 180 #ifdef __cplusplus 181 } 182 #endif 183 184 #endif 185