1 /* 2 ** ################################################################### 3 ** Version: rev. 2.15, 2016-03-21 4 ** Build: b170228 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2017 NXP 11 ** Redistribution and use in source and binary forms, with or without modification, 12 ** are permitted provided that the following conditions are met: 13 ** 14 ** o Redistributions of source code must retain the above copyright notice, this list 15 ** of conditions and the following disclaimer. 16 ** 17 ** o Redistributions in binary form must reproduce the above copyright notice, this 18 ** list of conditions and the following disclaimer in the documentation and/or 19 ** other materials provided with the distribution. 20 ** 21 ** o Neither the name of the copyright holder nor the names of its 22 ** contributors may be used to endorse or promote products derived from this 23 ** software without specific prior written permission. 24 ** 25 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 26 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 29 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 32 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 ** 36 ** http: www.nxp.com 37 ** mail: support@nxp.com 38 ** 39 ** Revisions: 40 ** - rev. 1.0 (2013-08-12) 41 ** Initial version. 42 ** - rev. 2.0 (2013-10-29) 43 ** Register accessor macros added to the memory map. 44 ** Symbols for Processor Expert memory map compatibility added to the memory map. 45 ** Startup file for gcc has been updated according to CMSIS 3.2. 46 ** System initialization updated. 47 ** MCG - registers updated. 48 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 49 ** - rev. 2.1 (2013-10-30) 50 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 51 ** - rev. 2.2 (2013-12-09) 52 ** DMA - EARS register removed. 53 ** AIPS0, AIPS1 - MPRA register updated. 54 ** - rev. 2.3 (2014-01-24) 55 ** Update according to reference manual rev. 2 56 ** ENET, MCG, MCM, SIM, USB - registers updated 57 ** - rev. 2.4 (2014-01-30) 58 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. 59 ** - rev. 2.5 (2014-02-10) 60 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 61 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 62 ** - rev. 2.6 (2014-02-10) 63 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 64 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 65 ** Module access macro module_BASES replaced by module_BASE_PTRS. 66 ** - rev. 2.7 (2014-08-28) 67 ** Update of system files - default clock configuration changed. 68 ** Update of startup files - possibility to override DefaultISR added. 69 ** - rev. 2.8 (2014-10-14) 70 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. 71 ** - rev. 2.9 (2015-01-21) 72 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 73 ** - rev. 2.10 (2015-02-19) 74 ** Renamed interrupt vector LLW to LLWU. 75 ** - rev. 2.11 (2015-05-19) 76 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 77 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 78 ** Added features for PDB and PORT. 79 ** - rev. 2.12 (2015-05-25) 80 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 81 ** - rev. 2.13 (2015-05-27) 82 ** Several USB features added. 83 ** - rev. 2.14 (2015-06-08) 84 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 85 ** - rev. 2.15 (2016-03-21) 86 ** Added MK64FN1M0CAJ12 part. 87 ** 88 ** ################################################################### 89 */ 90 91 #ifndef _MK64F12_FEATURES_H_ 92 #define _MK64F12_FEATURES_H_ 93 94 /* SOC module features */ 95 96 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ 97 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) 98 /* @brief ACMP availability on the SoC. */ 99 #define FSL_FEATURE_SOC_ACMP_COUNT (0) 100 /* @brief ADC16 availability on the SoC. */ 101 #define FSL_FEATURE_SOC_ADC16_COUNT (2) 102 /* @brief ADC12 availability on the SoC. */ 103 #define FSL_FEATURE_SOC_ADC12_COUNT (0) 104 /* @brief AFE availability on the SoC. */ 105 #define FSL_FEATURE_SOC_AFE_COUNT (0) 106 /* @brief AIPS availability on the SoC. */ 107 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 108 /* @brief AOI availability on the SoC. */ 109 #define FSL_FEATURE_SOC_AOI_COUNT (0) 110 /* @brief AXBS availability on the SoC. */ 111 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 112 /* @brief ASMC availability on the SoC. */ 113 #define FSL_FEATURE_SOC_ASMC_COUNT (0) 114 /* @brief CADC availability on the SoC. */ 115 #define FSL_FEATURE_SOC_CADC_COUNT (0) 116 /* @brief FLEXCAN availability on the SoC. */ 117 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) 118 /* @brief MMCAU availability on the SoC. */ 119 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 120 /* @brief CMP availability on the SoC. */ 121 #define FSL_FEATURE_SOC_CMP_COUNT (3) 122 /* @brief CMT availability on the SoC. */ 123 #define FSL_FEATURE_SOC_CMT_COUNT (1) 124 /* @brief CNC availability on the SoC. */ 125 #define FSL_FEATURE_SOC_CNC_COUNT (0) 126 /* @brief CRC availability on the SoC. */ 127 #define FSL_FEATURE_SOC_CRC_COUNT (1) 128 /* @brief DAC availability on the SoC. */ 129 #define FSL_FEATURE_SOC_DAC_COUNT (2) 130 /* @brief DAC32 availability on the SoC. */ 131 #define FSL_FEATURE_SOC_DAC32_COUNT (0) 132 /* @brief DCDC availability on the SoC. */ 133 #define FSL_FEATURE_SOC_DCDC_COUNT (0) 134 /* @brief DDR availability on the SoC. */ 135 #define FSL_FEATURE_SOC_DDR_COUNT (0) 136 /* @brief DMA availability on the SoC. */ 137 #define FSL_FEATURE_SOC_DMA_COUNT (0) 138 /* @brief EDMA availability on the SoC. */ 139 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 140 /* @brief DMAMUX availability on the SoC. */ 141 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 142 /* @brief DRY availability on the SoC. */ 143 #define FSL_FEATURE_SOC_DRY_COUNT (0) 144 /* @brief DSPI availability on the SoC. */ 145 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 146 /* @brief EMVSIM availability on the SoC. */ 147 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) 148 /* @brief ENC availability on the SoC. */ 149 #define FSL_FEATURE_SOC_ENC_COUNT (0) 150 /* @brief ENET availability on the SoC. */ 151 #define FSL_FEATURE_SOC_ENET_COUNT (1) 152 /* @brief EWM availability on the SoC. */ 153 #define FSL_FEATURE_SOC_EWM_COUNT (1) 154 /* @brief FB availability on the SoC. */ 155 #define FSL_FEATURE_SOC_FB_COUNT (1) 156 /* @brief FGPIO availability on the SoC. */ 157 #define FSL_FEATURE_SOC_FGPIO_COUNT (0) 158 /* @brief FLEXIO availability on the SoC. */ 159 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) 160 /* @brief FMC availability on the SoC. */ 161 #define FSL_FEATURE_SOC_FMC_COUNT (1) 162 /* @brief FSKDT availability on the SoC. */ 163 #define FSL_FEATURE_SOC_FSKDT_COUNT (0) 164 /* @brief FTFA availability on the SoC. */ 165 #define FSL_FEATURE_SOC_FTFA_COUNT (0) 166 /* @brief FTFE availability on the SoC. */ 167 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 168 /* @brief FTFL availability on the SoC. */ 169 #define FSL_FEATURE_SOC_FTFL_COUNT (0) 170 /* @brief FTM availability on the SoC. */ 171 #define FSL_FEATURE_SOC_FTM_COUNT (4) 172 /* @brief FTMRA availability on the SoC. */ 173 #define FSL_FEATURE_SOC_FTMRA_COUNT (0) 174 /* @brief FTMRE availability on the SoC. */ 175 #define FSL_FEATURE_SOC_FTMRE_COUNT (0) 176 /* @brief FTMRH availability on the SoC. */ 177 #define FSL_FEATURE_SOC_FTMRH_COUNT (0) 178 /* @brief GPIO availability on the SoC. */ 179 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 180 /* @brief HSADC availability on the SoC. */ 181 #define FSL_FEATURE_SOC_HSADC_COUNT (0) 182 /* @brief I2C availability on the SoC. */ 183 #define FSL_FEATURE_SOC_I2C_COUNT (3) 184 /* @brief I2S availability on the SoC. */ 185 #define FSL_FEATURE_SOC_I2S_COUNT (1) 186 /* @brief ICS availability on the SoC. */ 187 #define FSL_FEATURE_SOC_ICS_COUNT (0) 188 /* @brief INTMUX availability on the SoC. */ 189 #define FSL_FEATURE_SOC_INTMUX_COUNT (0) 190 /* @brief IRQ availability on the SoC. */ 191 #define FSL_FEATURE_SOC_IRQ_COUNT (0) 192 /* @brief KBI availability on the SoC. */ 193 #define FSL_FEATURE_SOC_KBI_COUNT (0) 194 /* @brief SLCD availability on the SoC. */ 195 #define FSL_FEATURE_SOC_SLCD_COUNT (0) 196 /* @brief LCDC availability on the SoC. */ 197 #define FSL_FEATURE_SOC_LCDC_COUNT (0) 198 /* @brief LDO availability on the SoC. */ 199 #define FSL_FEATURE_SOC_LDO_COUNT (0) 200 /* @brief LLWU availability on the SoC. */ 201 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 202 /* @brief LMEM availability on the SoC. */ 203 #define FSL_FEATURE_SOC_LMEM_COUNT (0) 204 /* @brief LPI2C availability on the SoC. */ 205 #define FSL_FEATURE_SOC_LPI2C_COUNT (0) 206 /* @brief LPIT availability on the SoC. */ 207 #define FSL_FEATURE_SOC_LPIT_COUNT (0) 208 /* @brief LPSCI availability on the SoC. */ 209 #define FSL_FEATURE_SOC_LPSCI_COUNT (0) 210 /* @brief LPSPI availability on the SoC. */ 211 #define FSL_FEATURE_SOC_LPSPI_COUNT (0) 212 /* @brief LPTMR availability on the SoC. */ 213 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 214 /* @brief LPTPM availability on the SoC. */ 215 #define FSL_FEATURE_SOC_LPTPM_COUNT (0) 216 /* @brief LPUART availability on the SoC. */ 217 #define FSL_FEATURE_SOC_LPUART_COUNT (0) 218 /* @brief LTC availability on the SoC. */ 219 #define FSL_FEATURE_SOC_LTC_COUNT (0) 220 /* @brief MC availability on the SoC. */ 221 #define FSL_FEATURE_SOC_MC_COUNT (0) 222 /* @brief MCG availability on the SoC. */ 223 #define FSL_FEATURE_SOC_MCG_COUNT (1) 224 /* @brief MCGLITE availability on the SoC. */ 225 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) 226 /* @brief MCM availability on the SoC. */ 227 #define FSL_FEATURE_SOC_MCM_COUNT (1) 228 /* @brief MMAU availability on the SoC. */ 229 #define FSL_FEATURE_SOC_MMAU_COUNT (0) 230 /* @brief MMDVSQ availability on the SoC. */ 231 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) 232 /* @brief SYSMPU availability on the SoC. */ 233 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 234 /* @brief MSCAN availability on the SoC. */ 235 #define FSL_FEATURE_SOC_MSCAN_COUNT (0) 236 /* @brief MSCM availability on the SoC. */ 237 #define FSL_FEATURE_SOC_MSCM_COUNT (0) 238 /* @brief MTB availability on the SoC. */ 239 #define FSL_FEATURE_SOC_MTB_COUNT (0) 240 /* @brief MTBDWT availability on the SoC. */ 241 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) 242 /* @brief MU availability on the SoC. */ 243 #define FSL_FEATURE_SOC_MU_COUNT (0) 244 /* @brief NFC availability on the SoC. */ 245 #define FSL_FEATURE_SOC_NFC_COUNT (0) 246 /* @brief OPAMP availability on the SoC. */ 247 #define FSL_FEATURE_SOC_OPAMP_COUNT (0) 248 /* @brief OSC availability on the SoC. */ 249 #define FSL_FEATURE_SOC_OSC_COUNT (1) 250 /* @brief OSC32 availability on the SoC. */ 251 #define FSL_FEATURE_SOC_OSC32_COUNT (0) 252 /* @brief OTFAD availability on the SoC. */ 253 #define FSL_FEATURE_SOC_OTFAD_COUNT (0) 254 /* @brief PDB availability on the SoC. */ 255 #define FSL_FEATURE_SOC_PDB_COUNT (1) 256 /* @brief PCC availability on the SoC. */ 257 #define FSL_FEATURE_SOC_PCC_COUNT (0) 258 /* @brief PGA availability on the SoC. */ 259 #define FSL_FEATURE_SOC_PGA_COUNT (0) 260 /* @brief PIT availability on the SoC. */ 261 #define FSL_FEATURE_SOC_PIT_COUNT (1) 262 /* @brief PMC availability on the SoC. */ 263 #define FSL_FEATURE_SOC_PMC_COUNT (1) 264 /* @brief PORT availability on the SoC. */ 265 #define FSL_FEATURE_SOC_PORT_COUNT (5) 266 /* @brief PWM availability on the SoC. */ 267 #define FSL_FEATURE_SOC_PWM_COUNT (0) 268 /* @brief PWT availability on the SoC. */ 269 #define FSL_FEATURE_SOC_PWT_COUNT (0) 270 /* @brief QuadSPI availability on the SoC. */ 271 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) 272 /* @brief RCM availability on the SoC. */ 273 #define FSL_FEATURE_SOC_RCM_COUNT (1) 274 /* @brief RFSYS availability on the SoC. */ 275 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 276 /* @brief RFVBAT availability on the SoC. */ 277 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 278 /* @brief RNG availability on the SoC. */ 279 #define FSL_FEATURE_SOC_RNG_COUNT (1) 280 /* @brief RNGB availability on the SoC. */ 281 #define FSL_FEATURE_SOC_RNGB_COUNT (0) 282 /* @brief ROM availability on the SoC. */ 283 #define FSL_FEATURE_SOC_ROM_COUNT (0) 284 /* @brief RSIM availability on the SoC. */ 285 #define FSL_FEATURE_SOC_RSIM_COUNT (0) 286 /* @brief RTC availability on the SoC. */ 287 #define FSL_FEATURE_SOC_RTC_COUNT (1) 288 /* @brief SCG availability on the SoC. */ 289 #define FSL_FEATURE_SOC_SCG_COUNT (0) 290 /* @brief SCI availability on the SoC. */ 291 #define FSL_FEATURE_SOC_SCI_COUNT (0) 292 /* @brief SDHC availability on the SoC. */ 293 #define FSL_FEATURE_SOC_SDHC_COUNT (1) 294 /* @brief SDRAM availability on the SoC. */ 295 #define FSL_FEATURE_SOC_SDRAM_COUNT (0) 296 /* @brief SEMA42 availability on the SoC. */ 297 #define FSL_FEATURE_SOC_SEMA42_COUNT (0) 298 /* @brief SIM availability on the SoC. */ 299 #define FSL_FEATURE_SOC_SIM_COUNT (1) 300 /* @brief SMC availability on the SoC. */ 301 #define FSL_FEATURE_SOC_SMC_COUNT (1) 302 /* @brief SPI availability on the SoC. */ 303 #define FSL_FEATURE_SOC_SPI_COUNT (0) 304 /* @brief TMR availability on the SoC. */ 305 #define FSL_FEATURE_SOC_TMR_COUNT (0) 306 /* @brief TPM availability on the SoC. */ 307 #define FSL_FEATURE_SOC_TPM_COUNT (0) 308 /* @brief TRGMUX availability on the SoC. */ 309 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) 310 /* @brief TRIAMP availability on the SoC. */ 311 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) 312 /* @brief TRNG availability on the SoC. */ 313 #define FSL_FEATURE_SOC_TRNG_COUNT (0) 314 /* @brief TSI availability on the SoC. */ 315 #define FSL_FEATURE_SOC_TSI_COUNT (0) 316 /* @brief TSTMR availability on the SoC. */ 317 #define FSL_FEATURE_SOC_TSTMR_COUNT (0) 318 /* @brief UART availability on the SoC. */ 319 #define FSL_FEATURE_SOC_UART_COUNT (6) 320 /* @brief USB availability on the SoC. */ 321 #define FSL_FEATURE_SOC_USB_COUNT (1) 322 /* @brief USBDCD availability on the SoC. */ 323 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 324 /* @brief USBHS availability on the SoC. */ 325 #define FSL_FEATURE_SOC_USBHS_COUNT (0) 326 /* @brief USBHSDCD availability on the SoC. */ 327 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) 328 /* @brief USBPHY availability on the SoC. */ 329 #define FSL_FEATURE_SOC_USBPHY_COUNT (0) 330 /* @brief VREF availability on the SoC. */ 331 #define FSL_FEATURE_SOC_VREF_COUNT (1) 332 /* @brief WDOG availability on the SoC. */ 333 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 334 /* @brief XBAR availability on the SoC. */ 335 #define FSL_FEATURE_SOC_XBAR_COUNT (0) 336 /* @brief XBARA availability on the SoC. */ 337 #define FSL_FEATURE_SOC_XBARA_COUNT (0) 338 /* @brief XBARB availability on the SoC. */ 339 #define FSL_FEATURE_SOC_XBARB_COUNT (0) 340 /* @brief XCVR availability on the SoC. */ 341 #define FSL_FEATURE_SOC_XCVR_COUNT (0) 342 /* @brief XRDC availability on the SoC. */ 343 #define FSL_FEATURE_SOC_XRDC_COUNT (0) 344 /* @brief ZLL availability on the SoC. */ 345 #define FSL_FEATURE_SOC_ZLL_COUNT (0) 346 #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12) 347 /* @brief ACMP availability on the SoC. */ 348 #define FSL_FEATURE_SOC_ACMP_COUNT (0) 349 /* @brief ADC16 availability on the SoC. */ 350 #define FSL_FEATURE_SOC_ADC16_COUNT (2) 351 /* @brief ADC12 availability on the SoC. */ 352 #define FSL_FEATURE_SOC_ADC12_COUNT (0) 353 /* @brief AFE availability on the SoC. */ 354 #define FSL_FEATURE_SOC_AFE_COUNT (0) 355 /* @brief AIPS availability on the SoC. */ 356 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 357 /* @brief AOI availability on the SoC. */ 358 #define FSL_FEATURE_SOC_AOI_COUNT (0) 359 /* @brief AXBS availability on the SoC. */ 360 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 361 /* @brief ASMC availability on the SoC. */ 362 #define FSL_FEATURE_SOC_ASMC_COUNT (0) 363 /* @brief CADC availability on the SoC. */ 364 #define FSL_FEATURE_SOC_CADC_COUNT (0) 365 /* @brief FLEXCAN availability on the SoC. */ 366 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) 367 /* @brief MMCAU availability on the SoC. */ 368 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 369 /* @brief CMP availability on the SoC. */ 370 #define FSL_FEATURE_SOC_CMP_COUNT (3) 371 /* @brief CMT availability on the SoC. */ 372 #define FSL_FEATURE_SOC_CMT_COUNT (1) 373 /* @brief CNC availability on the SoC. */ 374 #define FSL_FEATURE_SOC_CNC_COUNT (0) 375 /* @brief CRC availability on the SoC. */ 376 #define FSL_FEATURE_SOC_CRC_COUNT (1) 377 /* @brief DAC availability on the SoC. */ 378 #define FSL_FEATURE_SOC_DAC_COUNT (1) 379 /* @brief DAC32 availability on the SoC. */ 380 #define FSL_FEATURE_SOC_DAC32_COUNT (0) 381 /* @brief DCDC availability on the SoC. */ 382 #define FSL_FEATURE_SOC_DCDC_COUNT (0) 383 /* @brief DDR availability on the SoC. */ 384 #define FSL_FEATURE_SOC_DDR_COUNT (0) 385 /* @brief DMA availability on the SoC. */ 386 #define FSL_FEATURE_SOC_DMA_COUNT (0) 387 /* @brief EDMA availability on the SoC. */ 388 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 389 /* @brief DMAMUX availability on the SoC. */ 390 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 391 /* @brief DRY availability on the SoC. */ 392 #define FSL_FEATURE_SOC_DRY_COUNT (0) 393 /* @brief DSPI availability on the SoC. */ 394 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 395 /* @brief EMVSIM availability on the SoC. */ 396 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) 397 /* @brief ENC availability on the SoC. */ 398 #define FSL_FEATURE_SOC_ENC_COUNT (0) 399 /* @brief ENET availability on the SoC. */ 400 #define FSL_FEATURE_SOC_ENET_COUNT (1) 401 /* @brief EWM availability on the SoC. */ 402 #define FSL_FEATURE_SOC_EWM_COUNT (1) 403 /* @brief FB availability on the SoC. */ 404 #define FSL_FEATURE_SOC_FB_COUNT (1) 405 /* @brief FGPIO availability on the SoC. */ 406 #define FSL_FEATURE_SOC_FGPIO_COUNT (0) 407 /* @brief FLEXIO availability on the SoC. */ 408 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) 409 /* @brief FMC availability on the SoC. */ 410 #define FSL_FEATURE_SOC_FMC_COUNT (1) 411 /* @brief FSKDT availability on the SoC. */ 412 #define FSL_FEATURE_SOC_FSKDT_COUNT (0) 413 /* @brief FTFA availability on the SoC. */ 414 #define FSL_FEATURE_SOC_FTFA_COUNT (0) 415 /* @brief FTFE availability on the SoC. */ 416 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 417 /* @brief FTFL availability on the SoC. */ 418 #define FSL_FEATURE_SOC_FTFL_COUNT (0) 419 /* @brief FTM availability on the SoC. */ 420 #define FSL_FEATURE_SOC_FTM_COUNT (4) 421 /* @brief FTMRA availability on the SoC. */ 422 #define FSL_FEATURE_SOC_FTMRA_COUNT (0) 423 /* @brief FTMRE availability on the SoC. */ 424 #define FSL_FEATURE_SOC_FTMRE_COUNT (0) 425 /* @brief FTMRH availability on the SoC. */ 426 #define FSL_FEATURE_SOC_FTMRH_COUNT (0) 427 /* @brief GPIO availability on the SoC. */ 428 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 429 /* @brief HSADC availability on the SoC. */ 430 #define FSL_FEATURE_SOC_HSADC_COUNT (0) 431 /* @brief I2C availability on the SoC. */ 432 #define FSL_FEATURE_SOC_I2C_COUNT (3) 433 /* @brief I2S availability on the SoC. */ 434 #define FSL_FEATURE_SOC_I2S_COUNT (1) 435 /* @brief ICS availability on the SoC. */ 436 #define FSL_FEATURE_SOC_ICS_COUNT (0) 437 /* @brief INTMUX availability on the SoC. */ 438 #define FSL_FEATURE_SOC_INTMUX_COUNT (0) 439 /* @brief IRQ availability on the SoC. */ 440 #define FSL_FEATURE_SOC_IRQ_COUNT (0) 441 /* @brief KBI availability on the SoC. */ 442 #define FSL_FEATURE_SOC_KBI_COUNT (0) 443 /* @brief SLCD availability on the SoC. */ 444 #define FSL_FEATURE_SOC_SLCD_COUNT (0) 445 /* @brief LCDC availability on the SoC. */ 446 #define FSL_FEATURE_SOC_LCDC_COUNT (0) 447 /* @brief LDO availability on the SoC. */ 448 #define FSL_FEATURE_SOC_LDO_COUNT (0) 449 /* @brief LLWU availability on the SoC. */ 450 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 451 /* @brief LMEM availability on the SoC. */ 452 #define FSL_FEATURE_SOC_LMEM_COUNT (0) 453 /* @brief LPI2C availability on the SoC. */ 454 #define FSL_FEATURE_SOC_LPI2C_COUNT (0) 455 /* @brief LPIT availability on the SoC. */ 456 #define FSL_FEATURE_SOC_LPIT_COUNT (0) 457 /* @brief LPSCI availability on the SoC. */ 458 #define FSL_FEATURE_SOC_LPSCI_COUNT (0) 459 /* @brief LPSPI availability on the SoC. */ 460 #define FSL_FEATURE_SOC_LPSPI_COUNT (0) 461 /* @brief LPTMR availability on the SoC. */ 462 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 463 /* @brief LPTPM availability on the SoC. */ 464 #define FSL_FEATURE_SOC_LPTPM_COUNT (0) 465 /* @brief LPUART availability on the SoC. */ 466 #define FSL_FEATURE_SOC_LPUART_COUNT (0) 467 /* @brief LTC availability on the SoC. */ 468 #define FSL_FEATURE_SOC_LTC_COUNT (0) 469 /* @brief MC availability on the SoC. */ 470 #define FSL_FEATURE_SOC_MC_COUNT (0) 471 /* @brief MCG availability on the SoC. */ 472 #define FSL_FEATURE_SOC_MCG_COUNT (1) 473 /* @brief MCGLITE availability on the SoC. */ 474 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) 475 /* @brief MCM availability on the SoC. */ 476 #define FSL_FEATURE_SOC_MCM_COUNT (1) 477 /* @brief MMAU availability on the SoC. */ 478 #define FSL_FEATURE_SOC_MMAU_COUNT (0) 479 /* @brief MMDVSQ availability on the SoC. */ 480 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) 481 /* @brief SYSMPU availability on the SoC. */ 482 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 483 /* @brief MSCAN availability on the SoC. */ 484 #define FSL_FEATURE_SOC_MSCAN_COUNT (0) 485 /* @brief MSCM availability on the SoC. */ 486 #define FSL_FEATURE_SOC_MSCM_COUNT (0) 487 /* @brief MTB availability on the SoC. */ 488 #define FSL_FEATURE_SOC_MTB_COUNT (0) 489 /* @brief MTBDWT availability on the SoC. */ 490 #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) 491 /* @brief MU availability on the SoC. */ 492 #define FSL_FEATURE_SOC_MU_COUNT (0) 493 /* @brief NFC availability on the SoC. */ 494 #define FSL_FEATURE_SOC_NFC_COUNT (0) 495 /* @brief OPAMP availability on the SoC. */ 496 #define FSL_FEATURE_SOC_OPAMP_COUNT (0) 497 /* @brief OSC availability on the SoC. */ 498 #define FSL_FEATURE_SOC_OSC_COUNT (1) 499 /* @brief OSC32 availability on the SoC. */ 500 #define FSL_FEATURE_SOC_OSC32_COUNT (0) 501 /* @brief OTFAD availability on the SoC. */ 502 #define FSL_FEATURE_SOC_OTFAD_COUNT (0) 503 /* @brief PDB availability on the SoC. */ 504 #define FSL_FEATURE_SOC_PDB_COUNT (1) 505 /* @brief PCC availability on the SoC. */ 506 #define FSL_FEATURE_SOC_PCC_COUNT (0) 507 /* @brief PGA availability on the SoC. */ 508 #define FSL_FEATURE_SOC_PGA_COUNT (0) 509 /* @brief PIT availability on the SoC. */ 510 #define FSL_FEATURE_SOC_PIT_COUNT (1) 511 /* @brief PMC availability on the SoC. */ 512 #define FSL_FEATURE_SOC_PMC_COUNT (1) 513 /* @brief PORT availability on the SoC. */ 514 #define FSL_FEATURE_SOC_PORT_COUNT (5) 515 /* @brief PWM availability on the SoC. */ 516 #define FSL_FEATURE_SOC_PWM_COUNT (0) 517 /* @brief PWT availability on the SoC. */ 518 #define FSL_FEATURE_SOC_PWT_COUNT (0) 519 /* @brief QuadSPI availability on the SoC. */ 520 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) 521 /* @brief RCM availability on the SoC. */ 522 #define FSL_FEATURE_SOC_RCM_COUNT (1) 523 /* @brief RFSYS availability on the SoC. */ 524 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 525 /* @brief RFVBAT availability on the SoC. */ 526 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 527 /* @brief RNG availability on the SoC. */ 528 #define FSL_FEATURE_SOC_RNG_COUNT (1) 529 /* @brief RNGB availability on the SoC. */ 530 #define FSL_FEATURE_SOC_RNGB_COUNT (0) 531 /* @brief ROM availability on the SoC. */ 532 #define FSL_FEATURE_SOC_ROM_COUNT (0) 533 /* @brief RSIM availability on the SoC. */ 534 #define FSL_FEATURE_SOC_RSIM_COUNT (0) 535 /* @brief RTC availability on the SoC. */ 536 #define FSL_FEATURE_SOC_RTC_COUNT (1) 537 /* @brief SCG availability on the SoC. */ 538 #define FSL_FEATURE_SOC_SCG_COUNT (0) 539 /* @brief SCI availability on the SoC. */ 540 #define FSL_FEATURE_SOC_SCI_COUNT (0) 541 /* @brief SDHC availability on the SoC. */ 542 #define FSL_FEATURE_SOC_SDHC_COUNT (1) 543 /* @brief SDRAM availability on the SoC. */ 544 #define FSL_FEATURE_SOC_SDRAM_COUNT (0) 545 /* @brief SEMA42 availability on the SoC. */ 546 #define FSL_FEATURE_SOC_SEMA42_COUNT (0) 547 /* @brief SIM availability on the SoC. */ 548 #define FSL_FEATURE_SOC_SIM_COUNT (1) 549 /* @brief SMC availability on the SoC. */ 550 #define FSL_FEATURE_SOC_SMC_COUNT (1) 551 /* @brief SPI availability on the SoC. */ 552 #define FSL_FEATURE_SOC_SPI_COUNT (0) 553 /* @brief TMR availability on the SoC. */ 554 #define FSL_FEATURE_SOC_TMR_COUNT (0) 555 /* @brief TPM availability on the SoC. */ 556 #define FSL_FEATURE_SOC_TPM_COUNT (0) 557 /* @brief TRGMUX availability on the SoC. */ 558 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) 559 /* @brief TRIAMP availability on the SoC. */ 560 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) 561 /* @brief TRNG availability on the SoC. */ 562 #define FSL_FEATURE_SOC_TRNG_COUNT (0) 563 /* @brief TSI availability on the SoC. */ 564 #define FSL_FEATURE_SOC_TSI_COUNT (0) 565 /* @brief TSTMR availability on the SoC. */ 566 #define FSL_FEATURE_SOC_TSTMR_COUNT (0) 567 /* @brief UART availability on the SoC. */ 568 #define FSL_FEATURE_SOC_UART_COUNT (5) 569 /* @brief USB availability on the SoC. */ 570 #define FSL_FEATURE_SOC_USB_COUNT (1) 571 /* @brief USBDCD availability on the SoC. */ 572 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 573 /* @brief USBHS availability on the SoC. */ 574 #define FSL_FEATURE_SOC_USBHS_COUNT (0) 575 /* @brief USBHSDCD availability on the SoC. */ 576 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) 577 /* @brief USBPHY availability on the SoC. */ 578 #define FSL_FEATURE_SOC_USBPHY_COUNT (0) 579 /* @brief VREF availability on the SoC. */ 580 #define FSL_FEATURE_SOC_VREF_COUNT (1) 581 /* @brief WDOG availability on the SoC. */ 582 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 583 /* @brief XBAR availability on the SoC. */ 584 #define FSL_FEATURE_SOC_XBAR_COUNT (0) 585 /* @brief XBARA availability on the SoC. */ 586 #define FSL_FEATURE_SOC_XBARA_COUNT (0) 587 /* @brief XBARB availability on the SoC. */ 588 #define FSL_FEATURE_SOC_XBARB_COUNT (0) 589 /* @brief XCVR availability on the SoC. */ 590 #define FSL_FEATURE_SOC_XCVR_COUNT (0) 591 /* @brief XRDC availability on the SoC. */ 592 #define FSL_FEATURE_SOC_XRDC_COUNT (0) 593 /* @brief ZLL availability on the SoC. */ 594 #define FSL_FEATURE_SOC_ZLL_COUNT (0) 595 #endif 596 597 /* ADC16 module features */ 598 599 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 600 #define FSL_FEATURE_ADC16_HAS_PGA (0) 601 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 602 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 603 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 604 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 605 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 606 #define FSL_FEATURE_ADC16_HAS_DMA (1) 607 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 608 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 609 /* @brief Has FIFO (bit SC4[AFDEP]). */ 610 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 611 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 612 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 613 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 614 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 615 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 616 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 617 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 618 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 619 /* @brief Has HW averaging (bit SC3[AVGE]). */ 620 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 621 /* @brief Has offset correction (register OFS). */ 622 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 623 /* @brief Maximum ADC resolution. */ 624 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 625 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 626 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 627 628 /* FLEXCAN module features */ 629 630 /* @brief Message buffer size */ 631 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) 632 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 633 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) 634 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 635 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 636 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 637 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) 638 /* @brief Has extended bit timing register (register CBT). */ 639 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) 640 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 641 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) 642 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ 643 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) 644 /* @brief Has bitfield name BUF31TO0M. */ 645 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0) 646 /* @brief Number of interrupt vectors. */ 647 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) 648 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ 649 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 650 651 /* CMP module features */ 652 653 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 654 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) 655 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 656 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 657 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 658 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 659 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 660 #define FSL_FEATURE_CMP_HAS_DMA (1) 661 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 662 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) 663 /* @brief Has DAC Test function in CMP (register DACTEST). */ 664 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 665 666 /* CRC module features */ 667 668 /* @brief Has data register with name CRC */ 669 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 670 671 /* DAC module features */ 672 673 /* @brief Define the size of hardware buffer */ 674 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 675 /* @brief Define whether the buffer supports watermark event detection or not. */ 676 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 677 /* @brief Define whether the buffer supports watermark selection detection or not. */ 678 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 679 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 680 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 681 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 682 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 683 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 684 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 685 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 686 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 687 /* @brief Define whether FIFO buffer mode is available or not. */ 688 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) 689 /* @brief Define whether swing buffer mode is available or not.. */ 690 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 691 692 /* EDMA module features */ 693 694 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 695 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) 696 /* @brief Total number of DMA channels on all modules. */ 697 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16) 698 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 699 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 700 /* @brief Has DMA_Error interrupt vector. */ 701 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 702 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 703 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) 704 705 /* DMAMUX module features */ 706 707 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 708 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 709 /* @brief Total number of DMA channels on all modules. */ 710 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16) 711 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 712 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 713 714 /* ENET module features */ 715 716 /* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */ 717 #define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0) 718 /* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */ 719 #define FSL_FEATURE_ENET_SUPPORT_PTP (1) 720 /* @brief Number of associated interrupt vectors. */ 721 #define FSL_FEATURE_ENET_INTERRUPT_COUNT (4) 722 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ 723 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) 724 725 /* EWM module features */ 726 727 /* @brief Has clock select (register CLKCTRL). */ 728 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 729 /* @brief Has clock prescaler (register CLKPRESCALER). */ 730 #define FSL_FEATURE_EWM_HAS_PRESCALER (0) 731 732 /* FLEXBUS module features */ 733 734 /* No feature definitions */ 735 736 /* FLASH module features */ 737 738 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ 739 defined(CPU_MK64FN1M0VMD12) 740 /* @brief Is of type FTFA. */ 741 #define FSL_FEATURE_FLASH_IS_FTFA (0) 742 /* @brief Is of type FTFE. */ 743 #define FSL_FEATURE_FLASH_IS_FTFE (1) 744 /* @brief Is of type FTFL. */ 745 #define FSL_FEATURE_FLASH_IS_FTFL (0) 746 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 747 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 748 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 749 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) 750 /* @brief Has EEPROM region protection (register FEPROT). */ 751 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 752 /* @brief Has data flash region protection (register FDPROT). */ 753 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 754 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 755 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 756 /* @brief Has flash cache control in FMC module. */ 757 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 758 /* @brief Has flash cache control in MCM module. */ 759 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 760 /* @brief Has flash cache control in MSCM module. */ 761 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 762 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 763 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 764 /* @brief P-Flash start address. */ 765 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 766 /* @brief P-Flash block count. */ 767 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 768 /* @brief P-Flash block size. */ 769 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 770 /* @brief P-Flash sector size. */ 771 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 772 /* @brief P-Flash write unit size. */ 773 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 774 /* @brief P-Flash data path width. */ 775 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 776 /* @brief P-Flash block swap feature. */ 777 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) 778 /* @brief P-Flash protection region count. */ 779 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 780 /* @brief Has FlexNVM memory. */ 781 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 782 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 783 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 784 /* @brief FlexNVM block count. */ 785 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 786 /* @brief FlexNVM block size. */ 787 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 788 /* @brief FlexNVM sector size. */ 789 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 790 /* @brief FlexNVM write unit size. */ 791 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 792 /* @brief FlexNVM data path width. */ 793 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 794 /* @brief Has FlexRAM memory. */ 795 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 796 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 797 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 798 /* @brief FlexRAM size. */ 799 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 800 /* @brief Has 0x00 Read 1s Block command. */ 801 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 802 /* @brief Has 0x01 Read 1s Section command. */ 803 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 804 /* @brief Has 0x02 Program Check command. */ 805 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 806 /* @brief Has 0x03 Read Resource command. */ 807 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 808 /* @brief Has 0x06 Program Longword command. */ 809 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 810 /* @brief Has 0x07 Program Phrase command. */ 811 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 812 /* @brief Has 0x08 Erase Flash Block command. */ 813 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 814 /* @brief Has 0x09 Erase Flash Sector command. */ 815 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 816 /* @brief Has 0x0B Program Section command. */ 817 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 818 /* @brief Has 0x40 Read 1s All Blocks command. */ 819 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 820 /* @brief Has 0x41 Read Once command. */ 821 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 822 /* @brief Has 0x43 Program Once command. */ 823 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 824 /* @brief Has 0x44 Erase All Blocks command. */ 825 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 826 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 827 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 828 /* @brief Has 0x46 Swap Control command. */ 829 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) 830 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 831 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 832 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 833 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 834 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 835 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 836 /* @brief Has 0x80 Program Partition command. */ 837 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 838 /* @brief Has 0x81 Set FlexRAM Function command. */ 839 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 840 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 841 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 842 /* @brief P-Flash Erase sector command address alignment. */ 843 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 844 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 845 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 846 /* @brief P-Flash Read resource command address alignment. */ 847 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 848 /* @brief P-Flash Program check command address alignment. */ 849 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 850 /* @brief P-Flash Program check command address alignment. */ 851 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) 852 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 853 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 854 /* @brief FlexNVM Erase sector command address alignment. */ 855 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 856 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 857 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 858 /* @brief FlexNVM Read resource command address alignment. */ 859 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 860 /* @brief FlexNVM Program check command address alignment. */ 861 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 862 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 863 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 864 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 865 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 866 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 867 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 868 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 869 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 870 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 871 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 872 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 873 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 874 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 875 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 876 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 877 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 878 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 879 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 880 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 881 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 882 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 883 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 884 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 885 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 886 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 887 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 888 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 889 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 890 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 891 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 892 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 893 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 894 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 895 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 896 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 897 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 898 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 899 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 900 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 901 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 902 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 903 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 904 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 905 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 906 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 907 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 908 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 909 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 910 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 911 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 912 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 913 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 914 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 915 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 916 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 917 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 918 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 919 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 920 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 921 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 922 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 923 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 924 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 925 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 926 #elif defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) 927 /* @brief Is of type FTFA. */ 928 #define FSL_FEATURE_FLASH_IS_FTFA (0) 929 /* @brief Is of type FTFE. */ 930 #define FSL_FEATURE_FLASH_IS_FTFE (1) 931 /* @brief Is of type FTFL. */ 932 #define FSL_FEATURE_FLASH_IS_FTFL (0) 933 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 934 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 935 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 936 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) 937 /* @brief Has EEPROM region protection (register FEPROT). */ 938 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 939 /* @brief Has data flash region protection (register FDPROT). */ 940 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 941 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 942 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 943 /* @brief Has flash cache control in FMC module. */ 944 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 945 /* @brief Has flash cache control in MCM module. */ 946 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 947 /* @brief Has flash cache control in MSCM module. */ 948 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 949 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 950 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 951 /* @brief P-Flash start address. */ 952 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 953 /* @brief P-Flash block count. */ 954 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 955 /* @brief P-Flash block size. */ 956 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 957 /* @brief P-Flash sector size. */ 958 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 959 /* @brief P-Flash write unit size. */ 960 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 961 /* @brief P-Flash data path width. */ 962 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 963 /* @brief P-Flash block swap feature. */ 964 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 965 /* @brief P-Flash protection region count. */ 966 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 967 /* @brief Has FlexNVM memory. */ 968 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 969 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 970 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 971 /* @brief FlexNVM block count. */ 972 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 973 /* @brief FlexNVM block size. */ 974 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072) 975 /* @brief FlexNVM sector size. */ 976 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096) 977 /* @brief FlexNVM write unit size. */ 978 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8) 979 /* @brief FlexNVM data path width. */ 980 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16) 981 /* @brief Has FlexRAM memory. */ 982 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 983 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 984 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 985 /* @brief FlexRAM size. */ 986 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 987 /* @brief Has 0x00 Read 1s Block command. */ 988 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 989 /* @brief Has 0x01 Read 1s Section command. */ 990 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 991 /* @brief Has 0x02 Program Check command. */ 992 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 993 /* @brief Has 0x03 Read Resource command. */ 994 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 995 /* @brief Has 0x06 Program Longword command. */ 996 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 997 /* @brief Has 0x07 Program Phrase command. */ 998 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 999 /* @brief Has 0x08 Erase Flash Block command. */ 1000 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 1001 /* @brief Has 0x09 Erase Flash Sector command. */ 1002 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 1003 /* @brief Has 0x0B Program Section command. */ 1004 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 1005 /* @brief Has 0x40 Read 1s All Blocks command. */ 1006 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 1007 /* @brief Has 0x41 Read Once command. */ 1008 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 1009 /* @brief Has 0x43 Program Once command. */ 1010 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 1011 /* @brief Has 0x44 Erase All Blocks command. */ 1012 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 1013 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 1014 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 1015 /* @brief Has 0x46 Swap Control command. */ 1016 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 1017 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 1018 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 1019 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 1020 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 1021 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 1022 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 1023 /* @brief Has 0x80 Program Partition command. */ 1024 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 1025 /* @brief Has 0x81 Set FlexRAM Function command. */ 1026 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 1027 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 1028 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 1029 /* @brief P-Flash Erase sector command address alignment. */ 1030 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 1031 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 1032 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 1033 /* @brief P-Flash Read resource command address alignment. */ 1034 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 1035 /* @brief P-Flash Program check command address alignment. */ 1036 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 1037 /* @brief P-Flash Program check command address alignment. */ 1038 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 1039 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 1040 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16) 1041 /* @brief FlexNVM Erase sector command address alignment. */ 1042 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16) 1043 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 1044 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16) 1045 /* @brief FlexNVM Read resource command address alignment. */ 1046 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 1047 /* @brief FlexNVM Program check command address alignment. */ 1048 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 1049 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1050 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000) 1051 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1052 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 1053 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1054 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000) 1055 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1056 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000) 1057 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1058 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000) 1059 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1060 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000) 1061 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1062 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 1063 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1064 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 1065 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1066 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000) 1067 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1068 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 1069 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1070 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000) 1071 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1072 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000) 1073 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1074 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000) 1075 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1076 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000) 1077 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1078 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 1079 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 1080 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000) 1081 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1082 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 1083 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1084 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 1085 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1086 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 1087 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1088 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 1089 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1090 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 1091 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1092 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 1093 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1094 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 1095 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1096 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 1097 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1098 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 1099 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1100 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 1101 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1102 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 1103 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1104 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 1105 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1106 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 1107 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1108 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 1109 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1110 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 1111 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 1112 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 1113 #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ 1114 defined(CPU_MK64FN1M0VMD12) */ 1115 1116 /* FTM module features */ 1117 1118 /* @brief Number of channels. */ 1119 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 1120 ((x) == FTM0 ? (8) : \ 1121 ((x) == FTM1 ? (2) : \ 1122 ((x) == FTM2 ? (2) : \ 1123 ((x) == FTM3 ? (8) : (-1))))) 1124 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1125 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 1126 /* @brief Has extended deadtime value. */ 1127 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 1128 /* @brief Enable pwm output for the module. */ 1129 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 1130 /* @brief Has half-cycle reload for the module. */ 1131 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 1132 /* @brief Has reload interrupt. */ 1133 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 1134 /* @brief Has reload initialization trigger. */ 1135 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 1136 1137 /* GPIO module features */ 1138 1139 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ 1140 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) 1141 /* @brief Has port input disable register (PIDR). */ 1142 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) 1143 /* @brief Has dedicated interrupt vector. */ 1144 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) 1145 1146 /* I2C module features */ 1147 1148 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 1149 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 1150 /* @brief Maximum supported baud rate in kilobit per second. */ 1151 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 1152 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 1153 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 1154 /* @brief Has DMA support (register bit C1[DMAEN]). */ 1155 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 1156 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 1157 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 1158 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 1159 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 1160 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 1161 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 1162 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 1163 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 1164 /* @brief Has control of the drive capability of the I2C pins. */ 1165 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 1166 /* @brief Has double buffering support (register S2). */ 1167 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 1168 /* @brief Has double buffer enable. */ 1169 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 1170 1171 /* SAI module features */ 1172 1173 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 1174 #define FSL_FEATURE_SAI_FIFO_COUNT (8) 1175 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 1176 #define FSL_FEATURE_SAI_CHANNEL_COUNT (2) 1177 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 1178 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 1179 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 1180 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) 1181 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 1182 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) 1183 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 1184 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) 1185 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 1186 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) 1187 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 1188 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 1189 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 1190 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) 1191 /* @brief Ihe interrupt source number */ 1192 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 1193 /* @brief Has register of MCR. */ 1194 #define FSL_FEATURE_SAI_HAS_MCR (1) 1195 /* @brief Has register of MDR */ 1196 #define FSL_FEATURE_SAI_HAS_MDR (1) 1197 1198 /* LLWU module features */ 1199 1200 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 1201 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 1202 /* @brief Has pins 8-15 connected to LLWU device. */ 1203 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 1204 /* @brief Maximum number of internal modules connected to LLWU device. */ 1205 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 1206 /* @brief Number of digital filters. */ 1207 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 1208 /* @brief Has MF register. */ 1209 #define FSL_FEATURE_LLWU_HAS_MF (0) 1210 /* @brief Has PF register. */ 1211 #define FSL_FEATURE_LLWU_HAS_PF (0) 1212 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 1213 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) 1214 /* @brief Has no internal module wakeup flag register. */ 1215 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 1216 /* @brief Has external pin 0 connected to LLWU device. */ 1217 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 1218 /* @brief Index of port of external pin. */ 1219 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 1220 /* @brief Number of external pin port on specified port. */ 1221 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 1222 /* @brief Has external pin 1 connected to LLWU device. */ 1223 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 1224 /* @brief Index of port of external pin. */ 1225 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 1226 /* @brief Number of external pin port on specified port. */ 1227 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 1228 /* @brief Has external pin 2 connected to LLWU device. */ 1229 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 1230 /* @brief Index of port of external pin. */ 1231 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 1232 /* @brief Number of external pin port on specified port. */ 1233 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 1234 /* @brief Has external pin 3 connected to LLWU device. */ 1235 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 1236 /* @brief Index of port of external pin. */ 1237 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 1238 /* @brief Number of external pin port on specified port. */ 1239 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 1240 /* @brief Has external pin 4 connected to LLWU device. */ 1241 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 1242 /* @brief Index of port of external pin. */ 1243 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 1244 /* @brief Number of external pin port on specified port. */ 1245 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 1246 /* @brief Has external pin 5 connected to LLWU device. */ 1247 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 1248 /* @brief Index of port of external pin. */ 1249 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 1250 /* @brief Number of external pin port on specified port. */ 1251 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 1252 /* @brief Has external pin 6 connected to LLWU device. */ 1253 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 1254 /* @brief Index of port of external pin. */ 1255 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 1256 /* @brief Number of external pin port on specified port. */ 1257 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 1258 /* @brief Has external pin 7 connected to LLWU device. */ 1259 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 1260 /* @brief Index of port of external pin. */ 1261 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 1262 /* @brief Number of external pin port on specified port. */ 1263 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 1264 /* @brief Has external pin 8 connected to LLWU device. */ 1265 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 1266 /* @brief Index of port of external pin. */ 1267 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 1268 /* @brief Number of external pin port on specified port. */ 1269 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 1270 /* @brief Has external pin 9 connected to LLWU device. */ 1271 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 1272 /* @brief Index of port of external pin. */ 1273 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 1274 /* @brief Number of external pin port on specified port. */ 1275 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 1276 /* @brief Has external pin 10 connected to LLWU device. */ 1277 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 1278 /* @brief Index of port of external pin. */ 1279 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 1280 /* @brief Number of external pin port on specified port. */ 1281 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 1282 /* @brief Has external pin 11 connected to LLWU device. */ 1283 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 1284 /* @brief Index of port of external pin. */ 1285 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 1286 /* @brief Number of external pin port on specified port. */ 1287 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 1288 /* @brief Has external pin 12 connected to LLWU device. */ 1289 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 1290 /* @brief Index of port of external pin. */ 1291 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 1292 /* @brief Number of external pin port on specified port. */ 1293 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 1294 /* @brief Has external pin 13 connected to LLWU device. */ 1295 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 1296 /* @brief Index of port of external pin. */ 1297 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 1298 /* @brief Number of external pin port on specified port. */ 1299 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 1300 /* @brief Has external pin 14 connected to LLWU device. */ 1301 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1302 /* @brief Index of port of external pin. */ 1303 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1304 /* @brief Number of external pin port on specified port. */ 1305 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1306 /* @brief Has external pin 15 connected to LLWU device. */ 1307 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1308 /* @brief Index of port of external pin. */ 1309 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1310 /* @brief Number of external pin port on specified port. */ 1311 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1312 /* @brief Has external pin 16 connected to LLWU device. */ 1313 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 1314 /* @brief Index of port of external pin. */ 1315 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 1316 /* @brief Number of external pin port on specified port. */ 1317 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 1318 /* @brief Has external pin 17 connected to LLWU device. */ 1319 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 1320 /* @brief Index of port of external pin. */ 1321 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 1322 /* @brief Number of external pin port on specified port. */ 1323 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 1324 /* @brief Has external pin 18 connected to LLWU device. */ 1325 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 1326 /* @brief Index of port of external pin. */ 1327 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 1328 /* @brief Number of external pin port on specified port. */ 1329 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 1330 /* @brief Has external pin 19 connected to LLWU device. */ 1331 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 1332 /* @brief Index of port of external pin. */ 1333 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 1334 /* @brief Number of external pin port on specified port. */ 1335 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 1336 /* @brief Has external pin 20 connected to LLWU device. */ 1337 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 1338 /* @brief Index of port of external pin. */ 1339 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 1340 /* @brief Number of external pin port on specified port. */ 1341 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 1342 /* @brief Has external pin 21 connected to LLWU device. */ 1343 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 1344 /* @brief Index of port of external pin. */ 1345 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 1346 /* @brief Number of external pin port on specified port. */ 1347 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 1348 /* @brief Has external pin 22 connected to LLWU device. */ 1349 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 1350 /* @brief Index of port of external pin. */ 1351 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 1352 /* @brief Number of external pin port on specified port. */ 1353 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 1354 /* @brief Has external pin 23 connected to LLWU device. */ 1355 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 1356 /* @brief Index of port of external pin. */ 1357 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 1358 /* @brief Number of external pin port on specified port. */ 1359 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 1360 /* @brief Has external pin 24 connected to LLWU device. */ 1361 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 1362 /* @brief Index of port of external pin. */ 1363 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 1364 /* @brief Number of external pin port on specified port. */ 1365 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 1366 /* @brief Has external pin 25 connected to LLWU device. */ 1367 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 1368 /* @brief Index of port of external pin. */ 1369 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 1370 /* @brief Number of external pin port on specified port. */ 1371 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 1372 /* @brief Has external pin 26 connected to LLWU device. */ 1373 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1374 /* @brief Index of port of external pin. */ 1375 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1376 /* @brief Number of external pin port on specified port. */ 1377 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1378 /* @brief Has external pin 27 connected to LLWU device. */ 1379 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1380 /* @brief Index of port of external pin. */ 1381 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1382 /* @brief Number of external pin port on specified port. */ 1383 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1384 /* @brief Has external pin 28 connected to LLWU device. */ 1385 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1386 /* @brief Index of port of external pin. */ 1387 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1388 /* @brief Number of external pin port on specified port. */ 1389 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1390 /* @brief Has external pin 29 connected to LLWU device. */ 1391 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1392 /* @brief Index of port of external pin. */ 1393 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1394 /* @brief Number of external pin port on specified port. */ 1395 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1396 /* @brief Has external pin 30 connected to LLWU device. */ 1397 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1398 /* @brief Index of port of external pin. */ 1399 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1400 /* @brief Number of external pin port on specified port. */ 1401 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1402 /* @brief Has external pin 31 connected to LLWU device. */ 1403 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1404 /* @brief Index of port of external pin. */ 1405 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1406 /* @brief Number of external pin port on specified port. */ 1407 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1408 /* @brief Has internal module 0 connected to LLWU device. */ 1409 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1410 /* @brief Has internal module 1 connected to LLWU device. */ 1411 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1412 /* @brief Has internal module 2 connected to LLWU device. */ 1413 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1414 /* @brief Has internal module 3 connected to LLWU device. */ 1415 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 1416 /* @brief Has internal module 4 connected to LLWU device. */ 1417 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1418 /* @brief Has internal module 5 connected to LLWU device. */ 1419 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 1420 /* @brief Has internal module 6 connected to LLWU device. */ 1421 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1422 /* @brief Has internal module 7 connected to LLWU device. */ 1423 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 1424 /* @brief Has Version ID Register (LLWU_VERID). */ 1425 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1426 /* @brief Has Parameter Register (LLWU_PARAM). */ 1427 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1428 /* @brief Width of registers of the LLWU. */ 1429 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1430 /* @brief Has DMA Enable register (LLWU_DE). */ 1431 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1432 1433 /* LPTMR module features */ 1434 1435 /* @brief Has shared interrupt handler with another LPTMR module. */ 1436 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 1437 /* @brief Whether LPTMR counter is 32 bits width. */ 1438 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1439 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1440 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1441 1442 /* MCG module features */ 1443 1444 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1445 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 1446 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1447 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) 1448 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1449 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) 1450 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1451 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) 1452 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1453 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) 1454 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1455 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 1456 /* @brief FRDIV supports 1280. */ 1457 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1458 /* @brief FRDIV supports 1536. */ 1459 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1460 /* @brief MCGFFCLK divider. */ 1461 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1462 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1463 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 1464 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1465 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 1466 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1467 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1468 /* @brief Has 48MHz internal oscillator. */ 1469 #define FSL_FEATURE_MCG_HAS_IRC_48M (1) 1470 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1471 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1472 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1473 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1474 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1475 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 1476 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1477 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 1478 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1479 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1480 /* @brief TBD */ 1481 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1482 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1483 #define FSL_FEATURE_MCG_HAS_PLL (1) 1484 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1485 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 1486 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1487 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 1488 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1489 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 1490 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1491 #define FSL_FEATURE_MCG_HAS_FLL (1) 1492 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1493 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1494 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1495 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1496 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1497 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 1498 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1499 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1500 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1501 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1502 /* @brief Has external clock monitor (register bit C6[CME]). */ 1503 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1504 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1505 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1506 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1507 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1508 /* @brief Has PEI mode or PBI mode. */ 1509 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1510 /* @brief Reset clock mode is BLPI. */ 1511 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1512 1513 /* interrupt module features */ 1514 1515 /* @brief Lowest interrupt request number. */ 1516 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1517 /* @brief Highest interrupt request number. */ 1518 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) 1519 1520 /* OSC module features */ 1521 1522 /* @brief Has OSC1 external oscillator. */ 1523 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1524 /* @brief Has OSC0 external oscillator. */ 1525 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 1526 /* @brief Has OSC external oscillator (without index). */ 1527 #define FSL_FEATURE_OSC_HAS_OSC (1) 1528 /* @brief Number of OSC external oscillators. */ 1529 #define FSL_FEATURE_OSC_OSC_COUNT (1) 1530 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1531 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 1532 1533 /* PDB module features */ 1534 1535 /* @brief Define the count of supporting ADC pre-trigger for each channel. */ 1536 #define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) 1537 /* @brief Has DAC support. */ 1538 #define FSL_FEATURE_PDB_HAS_DAC (1) 1539 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1540 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 1541 1542 /* PIT module features */ 1543 1544 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1545 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 1546 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1547 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) 1548 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1549 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1550 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1551 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 1552 1553 /* PMC module features */ 1554 1555 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1556 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1557 /* @brief Has Bandgap Buffer Enable. */ 1558 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1559 /* @brief Has Bandgap Buffer Drive Select. */ 1560 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1561 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1562 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1563 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1564 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1565 /* @brief Has LPO. */ 1566 #define FSL_FEATURE_PMC_HAS_LPO (0) 1567 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1568 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1569 /* @brief Has acknowledge isolation support. */ 1570 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1571 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1572 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1573 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1574 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1575 /* @brief Has PMC_HVDSC1. */ 1576 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1577 /* @brief Has PMC_PARAM. */ 1578 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1579 /* @brief Has PMC_VERID. */ 1580 #define FSL_FEATURE_PMC_HAS_VERID (0) 1581 1582 /* PORT module features */ 1583 1584 /* @brief Has control lock (register bit PCR[LK]). */ 1585 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1586 /* @brief Has open drain control (register bit PCR[ODE]). */ 1587 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1588 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1589 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1590 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1591 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1592 /* @brief Has pull resistor selection available. */ 1593 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1594 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1595 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1596 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1597 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1598 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1599 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1600 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1601 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1602 /* @brief Has separate drive strength register (HDRVE). */ 1603 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1604 /* @brief Has glitch filter (register IOFLT). */ 1605 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1606 /* @brief Defines width of PCR[MUX] field. */ 1607 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1608 /* @brief Has dedicated interrupt vector. */ 1609 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1610 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1611 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1612 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1613 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1614 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1615 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1616 1617 /* RCM module features */ 1618 1619 /* @brief Has Loss-of-Lock Reset support. */ 1620 #define FSL_FEATURE_RCM_HAS_LOL (1) 1621 /* @brief Has Loss-of-Clock Reset support. */ 1622 #define FSL_FEATURE_RCM_HAS_LOC (1) 1623 /* @brief Has JTAG generated Reset support. */ 1624 #define FSL_FEATURE_RCM_HAS_JTAG (1) 1625 /* @brief Has EzPort generated Reset support. */ 1626 #define FSL_FEATURE_RCM_HAS_EZPORT (1) 1627 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1628 #define FSL_FEATURE_RCM_HAS_EZPMS (1) 1629 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1630 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1631 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1632 #define FSL_FEATURE_RCM_HAS_SSRS (0) 1633 /* @brief Has Version ID Register (RCM_VERID). */ 1634 #define FSL_FEATURE_RCM_HAS_VERID (0) 1635 /* @brief Has Parameter Register (RCM_PARAM). */ 1636 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1637 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1638 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1639 /* @brief Width of registers of the RCM. */ 1640 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1641 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1642 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1643 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1644 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1645 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1646 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1647 1648 /* RTC module features */ 1649 1650 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ 1651 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) 1652 /* @brief Has wakeup pin. */ 1653 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1654 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1655 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 1656 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1657 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 1658 /* @brief Has read/write access control (registers WAR and RAR). */ 1659 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 1660 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1661 #define FSL_FEATURE_RTC_HAS_SECURITY (1) 1662 /* @brief Has RTC_CLKIN available. */ 1663 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 1664 /* @brief Has prescaler adjust for LPO. */ 1665 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 1666 /* @brief Has Clock Pin Enable field. */ 1667 #define FSL_FEATURE_RTC_HAS_CPE (0) 1668 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1669 #define FSL_FEATURE_RTC_HAS_TSIC (0) 1670 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1671 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1672 #elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) 1673 /* @brief Has wakeup pin. */ 1674 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1675 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1676 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 1677 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1678 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 1679 /* @brief Has read/write access control (registers WAR and RAR). */ 1680 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 1681 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1682 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 1683 /* @brief Has RTC_CLKIN available. */ 1684 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 1685 /* @brief Has prescaler adjust for LPO. */ 1686 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 1687 /* @brief Has Clock Pin Enable field. */ 1688 #define FSL_FEATURE_RTC_HAS_CPE (0) 1689 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1690 #define FSL_FEATURE_RTC_HAS_TSIC (0) 1691 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1692 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1693 #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ 1694 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) */ 1695 1696 /* SDHC module features */ 1697 1698 /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ 1699 #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1) 1700 /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ 1701 #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) 1702 /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ 1703 #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) 1704 1705 /* SIM module features */ 1706 1707 /* @brief Has USB FS divider. */ 1708 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1709 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1710 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1711 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1712 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1713 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1714 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1715 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1716 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1717 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1718 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1719 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1720 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 1721 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1722 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 1723 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1724 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1725 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1726 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) 1727 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1728 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) 1729 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1730 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1731 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1732 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1733 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1734 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1735 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1736 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1737 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1738 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) 1739 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1740 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1741 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1742 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1743 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1744 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1745 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1746 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1747 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1748 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1749 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1750 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1751 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1752 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1753 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1754 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1755 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1756 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1757 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1758 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1759 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1760 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1761 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1762 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1763 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1764 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1765 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1766 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1767 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1768 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1769 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1770 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1771 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1772 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1773 /* @brief Has FTM module(s) configuration. */ 1774 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1775 /* @brief Number of FTM modules. */ 1776 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) 1777 /* @brief Number of FTM triggers with selectable source. */ 1778 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1779 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1780 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1781 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1782 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) 1783 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1784 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1785 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1786 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1787 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1788 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1789 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1790 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1791 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1792 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) 1793 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1794 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1795 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1796 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1797 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1798 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) 1799 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1800 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1801 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1802 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1803 /* @brief Has TPM module(s) configuration. */ 1804 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1805 /* @brief The highest TPM module index. */ 1806 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1807 /* @brief Has TPM module with index 0. */ 1808 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1809 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1810 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1811 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1812 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1813 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1814 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1815 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1816 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1817 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1818 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1819 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1820 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1821 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1822 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1823 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1824 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1825 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1826 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1827 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1828 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1829 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1830 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1831 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1832 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) 1833 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1834 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1835 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1836 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) 1837 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1838 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) 1839 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1840 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) 1841 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1842 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1843 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1844 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1845 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1846 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1847 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1848 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1849 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1850 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1851 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1852 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1853 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1854 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1855 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1856 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1857 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1858 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1859 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1860 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) 1861 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1862 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 1863 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1864 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) 1865 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1866 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1867 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1868 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1869 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1870 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1871 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1872 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1873 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1874 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1875 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1876 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1877 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1878 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1879 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1880 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1881 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1882 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1883 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1884 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) 1885 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1886 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1887 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1888 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1889 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1890 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1891 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1892 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) 1893 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1894 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1895 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1896 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1897 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1898 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1899 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1900 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1901 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1902 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1903 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1904 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1905 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1906 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) 1907 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1908 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1909 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1910 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1911 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1912 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1913 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1914 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1915 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1916 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1917 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1918 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1919 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1920 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1921 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1922 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1923 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1924 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) 1925 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1926 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) 1927 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1928 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) 1929 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1930 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1931 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1932 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1933 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1934 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1935 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1936 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1937 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1938 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) 1939 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1940 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1941 /* @brief Has miscellanious control register (register MCR). */ 1942 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1943 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1944 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1945 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1946 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1947 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1948 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1949 1950 /* SMC module features */ 1951 1952 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1953 #define FSL_FEATURE_SMC_HAS_PSTOPO (0) 1954 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1955 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1956 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1957 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1958 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1959 #define FSL_FEATURE_SMC_HAS_LPWUI (1) 1960 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1961 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1962 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1963 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) 1964 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1965 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1966 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1967 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1968 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1969 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1970 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1971 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1972 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1973 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1974 /* @brief Has stop submode. */ 1975 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1976 /* @brief Has stop submode 0(VLLS0). */ 1977 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1978 /* @brief Has stop submode 2(VLLS2). */ 1979 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1980 /* @brief Has SMC_PARAM. */ 1981 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1982 /* @brief Has SMC_VERID. */ 1983 #define FSL_FEATURE_SMC_HAS_VERID (0) 1984 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1985 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1986 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1987 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1988 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1989 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1990 1991 /* DSPI module features */ 1992 1993 /* @brief Receive/transmit FIFO size in number of items. */ 1994 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ 1995 ((x) == DSPI0 ? (4) : \ 1996 ((x) == DSPI1 ? (1) : \ 1997 ((x) == DSPI2 ? (1) : (-1)))) 1998 /* @brief Maximum transfer data width in bits. */ 1999 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 2000 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 2001 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 2002 /* @brief Number of chip select pins. */ 2003 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) 2004 /* @brief Has chip select strobe capability on the PCS5 pin. */ 2005 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 2006 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 2007 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 2008 /* @brief Has 16-bit data transfer support. */ 2009 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 2010 /* @brief Has separate DMA RX and TX requests. */ 2011 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 2012 ((x) == DSPI0 ? (1) : \ 2013 ((x) == DSPI1 ? (0) : \ 2014 ((x) == DSPI2 ? (0) : (-1)))) 2015 2016 /* SYSMPU module features */ 2017 2018 /* @brief Specifies number of descriptors available. */ 2019 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) 2020 /* @brief Has process identifier support. */ 2021 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 2022 /* @brief Total number of MPU slave. */ 2023 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5) 2024 /* @brief Total number of MPU master. */ 2025 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (6) 2026 2027 /* SysTick module features */ 2028 2029 /* @brief Systick has external reference clock. */ 2030 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 2031 /* @brief Systick external reference clock is core clock divided by this value. */ 2032 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 2033 2034 /* UART module features */ 2035 2036 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ 2037 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) 2038 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 2039 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 2040 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 2041 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 2042 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 2043 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 2044 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 2045 #define FSL_FEATURE_UART_HAS_FIFO (1) 2046 /* @brief Hardware flow control (RTS, CTS) is supported. */ 2047 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 2048 /* @brief Infrared (modulation) is supported. */ 2049 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 2050 /* @brief 2 bits long stop bit is available. */ 2051 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 2052 /* @brief If 10-bit mode is supported. */ 2053 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 2054 /* @brief Baud rate fine adjustment is available. */ 2055 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 2056 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 2057 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 2058 /* @brief Baud rate oversampling is available. */ 2059 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 2060 /* @brief Baud rate oversampling is available. */ 2061 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 2062 /* @brief Peripheral type. */ 2063 #define FSL_FEATURE_UART_IS_SCI (0) 2064 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 2065 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 2066 ((x) == UART0 ? (8) : \ 2067 ((x) == UART1 ? (8) : \ 2068 ((x) == UART2 ? (1) : \ 2069 ((x) == UART3 ? (1) : \ 2070 ((x) == UART4 ? (1) : \ 2071 ((x) == UART5 ? (1) : (-1))))))) 2072 /* @brief Maximal data width without parity bit. */ 2073 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) 2074 /* @brief Maximal data width with parity bit. */ 2075 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) 2076 /* @brief Supports two match addresses to filter incoming frames. */ 2077 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 2078 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 2079 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 2080 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 2081 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 2082 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 2083 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 2084 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 2085 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 2086 /* @brief Has improved smart card (ISO7816 protocol) support. */ 2087 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 2088 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 2089 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 2090 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 2091 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 2092 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 2093 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 2094 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 2095 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 2096 /* @brief Has separate DMA RX and TX requests. */ 2097 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 2098 ((x) == UART0 ? (1) : \ 2099 ((x) == UART1 ? (1) : \ 2100 ((x) == UART2 ? (1) : \ 2101 ((x) == UART3 ? (1) : \ 2102 ((x) == UART4 ? (0) : \ 2103 ((x) == UART5 ? (0) : (-1))))))) 2104 #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12) 2105 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 2106 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 2107 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 2108 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 2109 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 2110 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 2111 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 2112 #define FSL_FEATURE_UART_HAS_FIFO (1) 2113 /* @brief Hardware flow control (RTS, CTS) is supported. */ 2114 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 2115 /* @brief Infrared (modulation) is supported. */ 2116 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 2117 /* @brief 2 bits long stop bit is available. */ 2118 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 2119 /* @brief If 10-bit mode is supported. */ 2120 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 2121 /* @brief Baud rate fine adjustment is available. */ 2122 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 2123 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 2124 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 2125 /* @brief Baud rate oversampling is available. */ 2126 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 2127 /* @brief Baud rate oversampling is available. */ 2128 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 2129 /* @brief Peripheral type. */ 2130 #define FSL_FEATURE_UART_IS_SCI (0) 2131 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 2132 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 2133 ((x) == UART0 ? (8) : \ 2134 ((x) == UART1 ? (8) : \ 2135 ((x) == UART2 ? (1) : \ 2136 ((x) == UART3 ? (1) : \ 2137 ((x) == UART4 ? (1) : (-1)))))) 2138 /* @brief Maximal data width without parity bit. */ 2139 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) 2140 /* @brief Maximal data width with parity bit. */ 2141 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) 2142 /* @brief Supports two match addresses to filter incoming frames. */ 2143 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 2144 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 2145 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 2146 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 2147 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 2148 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 2149 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 2150 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 2151 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 2152 /* @brief Has improved smart card (ISO7816 protocol) support. */ 2153 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 2154 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 2155 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 2156 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 2157 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 2158 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 2159 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 2160 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 2161 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 2162 /* @brief Has separate DMA RX and TX requests. */ 2163 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 2164 ((x) == UART0 ? (1) : \ 2165 ((x) == UART1 ? (1) : \ 2166 ((x) == UART2 ? (1) : \ 2167 ((x) == UART3 ? (1) : \ 2168 ((x) == UART4 ? (0) : (-1)))))) 2169 #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ 2170 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) */ 2171 2172 /* USB module features */ 2173 2174 /* @brief KHCI module instance count */ 2175 #define FSL_FEATURE_USB_KHCI_COUNT (1) 2176 /* @brief HOST mode enabled */ 2177 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 2178 /* @brief OTG mode enabled */ 2179 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 2180 /* @brief Size of the USB dedicated RAM */ 2181 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 2182 /* @brief Has KEEP_ALIVE_CTRL register */ 2183 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 2184 /* @brief Has the Dynamic SOF threshold compare support */ 2185 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) 2186 /* @brief Has the VBUS detect support */ 2187 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) 2188 /* @brief Has the IRC48M module clock support */ 2189 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) 2190 /* @brief Number of endpoints supported */ 2191 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 2192 2193 /* VREF module features */ 2194 2195 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 2196 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 2197 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 2198 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 2199 /* @brief If high/low buffer mode supported */ 2200 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 2201 /* @brief Module has also low reference (registers VREFL/VREFH) */ 2202 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 2203 /* @brief Has VREF_TRM4. */ 2204 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 2205 2206 /* WDOG module features */ 2207 2208 /* @brief Watchdog is available. */ 2209 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 2210 /* @brief Has Wait mode support. */ 2211 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 2212 2213 #endif /* _MK64F12_FEATURES_H_ */ 2214 2215