1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_ll_fsmc.h 4 * @author MCD Application Team 5 * @brief Header file of FSMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L1xx_LL_FSMC_H 22 #define STM32L1xx_LL_FSMC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l1xx_hal_def.h" 30 31 /** @addtogroup STM32L1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FSMC_LL 36 * @{ 37 */ 38 39 /** @addtogroup FSMC_LL_Private_Macros 40 * @{ 41 */ 42 #if defined(FSMC_BANK1) 43 44 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ 45 ((__BANK__) == FSMC_NORSRAM_BANK2) || \ 46 ((__BANK__) == FSMC_NORSRAM_BANK3) || \ 47 ((__BANK__) == FSMC_NORSRAM_BANK4)) 48 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ 49 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) 50 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ 51 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ 52 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) 53 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 54 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 55 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) 56 #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ 57 ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ 58 ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ 59 ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ 60 ((__SIZE__) == FSMC_PAGE_SIZE_1024)) 61 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ 62 ((__MODE__) == FSMC_ACCESS_MODE_B) || \ 63 ((__MODE__) == FSMC_ACCESS_MODE_C) || \ 64 ((__MODE__) == FSMC_ACCESS_MODE_D)) 65 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ 66 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) 67 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ 68 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) 69 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ 70 ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 71 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ 72 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 73 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ 74 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) 75 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ 76 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 77 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ 78 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) 79 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 80 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) 81 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 82 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ 83 ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 84 #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 85 ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 86 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 87 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 88 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 89 #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 90 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 91 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 92 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) 93 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) 94 95 #endif /* FSMC_BANK1 */ 96 97 /** 98 * @} 99 */ 100 101 /* Exported typedef ----------------------------------------------------------*/ 102 103 /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types 104 * @{ 105 */ 106 107 #if defined(FSMC_BANK1) 108 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef 109 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef 110 #endif /* FSMC_BANK1 */ 111 112 #if defined(FSMC_BANK1) 113 #define FSMC_NORSRAM_DEVICE FSMC_Bank1 114 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E 115 #endif /* FSMC_BANK1 */ 116 117 #if defined(FSMC_BANK1) 118 /** 119 * @brief FSMC NORSRAM Configuration Structure definition 120 */ 121 typedef struct 122 { 123 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 124 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ 125 126 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 127 multiplexed on the data bus or not. 128 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ 129 130 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 131 the corresponding memory device. 132 This parameter can be a value of @ref FSMC_Memory_Type */ 133 134 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 135 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ 136 137 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 138 valid only with synchronous burst Flash memories. 139 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ 140 141 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 142 the Flash memory in burst mode. 143 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ 144 145 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 146 memory, valid only when accessing Flash memories in burst mode. 147 This parameter can be a value of @ref FSMC_Wrap_Mode */ 148 149 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 150 clock cycle before the wait state or during the wait state, 151 valid only when accessing memories in burst mode. 152 This parameter can be a value of @ref FSMC_Wait_Timing */ 153 154 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. 155 This parameter can be a value of @ref FSMC_Write_Operation */ 156 157 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 158 signal, valid for Flash memory access in burst mode. 159 This parameter can be a value of @ref FSMC_Wait_Signal */ 160 161 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 162 This parameter can be a value of @ref FSMC_Extended_Mode */ 163 164 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 165 valid only with asynchronous Flash memories. 166 This parameter can be a value of @ref FSMC_AsynchronousWait */ 167 168 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 169 This parameter can be a value of @ref FSMC_Write_Burst */ 170 171 172 uint32_t PageSize; /*!< Specifies the memory page size. 173 This parameter can be a value of @ref FSMC_Page_Size */ 174 } FSMC_NORSRAM_InitTypeDef; 175 176 /** 177 * @brief FSMC NORSRAM Timing parameters structure definition 178 */ 179 typedef struct 180 { 181 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 182 the duration of the address setup time. 183 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 184 @note This parameter is not used with synchronous NOR Flash memories. */ 185 186 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 187 the duration of the address hold time. 188 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 189 @note This parameter is not used with synchronous NOR Flash memories. */ 190 191 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 192 the duration of the data setup time. 193 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 194 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 195 NOR Flash memories. */ 196 197 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 198 the duration of the bus turnaround. 199 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 200 @note This parameter is only used for multiplexed NOR Flash memories. */ 201 202 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 203 HCLK cycles. This parameter can be a value between Min_Data = 2 and 204 Max_Data = 16. 205 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 206 accesses. */ 207 208 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 209 to the memory before getting the first data. 210 The parameter value depends on the memory type as shown below: 211 - It must be set to 0 in case of a CRAM 212 - It is don't care in asynchronous NOR, SRAM or ROM accesses 213 - It may assume a value between Min_Data = 2 and Max_Data = 17 214 in NOR Flash memories with synchronous burst mode enable */ 215 216 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 217 This parameter can be a value of @ref FSMC_Access_Mode */ 218 } FSMC_NORSRAM_TimingTypeDef; 219 #endif /* FSMC_BANK1 */ 220 221 222 223 224 /** 225 * @} 226 */ 227 228 /* Exported constants --------------------------------------------------------*/ 229 /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants 230 * @{ 231 */ 232 #if defined(FSMC_BANK1) 233 234 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller 235 * @{ 236 */ 237 238 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank 239 * @{ 240 */ 241 #define FSMC_NORSRAM_BANK1 (0x00000000U) 242 #define FSMC_NORSRAM_BANK2 (0x00000002U) 243 #define FSMC_NORSRAM_BANK3 (0x00000004U) 244 #define FSMC_NORSRAM_BANK4 (0x00000006U) 245 /** 246 * @} 247 */ 248 249 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing 250 * @{ 251 */ 252 #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 253 #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 254 /** 255 * @} 256 */ 257 258 /** @defgroup FSMC_Memory_Type FSMC Memory Type 259 * @{ 260 */ 261 #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) 262 #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) 263 #define FSMC_MEMORY_TYPE_NOR (0x00000008U) 264 /** 265 * @} 266 */ 267 268 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width 269 * @{ 270 */ 271 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 272 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 273 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 274 /** 275 * @} 276 */ 277 278 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access 279 * @{ 280 */ 281 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 282 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 283 /** 284 * @} 285 */ 286 287 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode 288 * @{ 289 */ 290 #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 291 #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 292 /** 293 * @} 294 */ 295 296 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity 297 * @{ 298 */ 299 #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 300 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 301 /** 302 * @} 303 */ 304 305 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode 306 * @{ 307 */ 308 #define FSMC_WRAP_MODE_DISABLE (0x00000000U) 309 #define FSMC_WRAP_MODE_ENABLE (0x00000400U) 310 /** 311 * @} 312 */ 313 314 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing 315 * @{ 316 */ 317 #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 318 #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) 319 /** 320 * @} 321 */ 322 323 /** @defgroup FSMC_Write_Operation FSMC Write Operation 324 * @{ 325 */ 326 #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) 327 #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) 328 /** 329 * @} 330 */ 331 332 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal 333 * @{ 334 */ 335 #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) 336 #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) 337 /** 338 * @} 339 */ 340 341 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode 342 * @{ 343 */ 344 #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) 345 #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) 346 /** 347 * @} 348 */ 349 350 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait 351 * @{ 352 */ 353 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 354 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 355 /** 356 * @} 357 */ 358 359 /** @defgroup FSMC_Page_Size FSMC Page Size 360 * @{ 361 */ 362 #define FSMC_PAGE_SIZE_NONE (0x00000000U) 363 #define FSMC_PAGE_SIZE_128 FSMC_BCRx_CPSIZE_0 364 #define FSMC_PAGE_SIZE_256 FSMC_BCRx_CPSIZE_1 365 #define FSMC_PAGE_SIZE_512 (FSMC_BCRx_CPSIZE_0\ 366 | FSMC_BCRx_CPSIZE_1) 367 #define FSMC_PAGE_SIZE_1024 FSMC_BCRx_CPSIZE_2 368 /** 369 * @} 370 */ 371 372 /** @defgroup FSMC_Write_Burst FSMC Write Burst 373 * @{ 374 */ 375 #define FSMC_WRITE_BURST_DISABLE (0x00000000U) 376 #define FSMC_WRITE_BURST_ENABLE (0x00080000U) 377 /** 378 * @} 379 */ 380 381 /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock 382 * @{ 383 */ 384 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 385 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 386 /** 387 * @} 388 */ 389 390 /** @defgroup FSMC_Access_Mode FSMC Access Mode 391 * @{ 392 */ 393 #define FSMC_ACCESS_MODE_A (0x00000000U) 394 #define FSMC_ACCESS_MODE_B (0x10000000U) 395 #define FSMC_ACCESS_MODE_C (0x20000000U) 396 #define FSMC_ACCESS_MODE_D (0x30000000U) 397 /** 398 * @} 399 */ 400 401 /** 402 * @} 403 */ 404 #endif /* FSMC_BANK1 */ 405 406 407 408 /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition 409 * @{ 410 */ 411 /** 412 * @} 413 */ 414 415 /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition 416 * @{ 417 */ 418 /** 419 * @} 420 */ 421 422 /** 423 * @} 424 */ 425 426 /** 427 * @} 428 */ 429 430 /* Private macro -------------------------------------------------------------*/ 431 /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros 432 * @{ 433 */ 434 #if defined(FSMC_BANK1) 435 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros 436 * @brief macros to handle NOR device enable/disable and read/write operations 437 * @{ 438 */ 439 440 /** 441 * @brief Enable the NORSRAM device access. 442 * @param __INSTANCE__ FSMC_NORSRAM Instance 443 * @param __BANK__ FSMC_NORSRAM Bank 444 * @retval None 445 */ 446 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 447 |= FSMC_BCRx_MBKEN) 448 449 /** 450 * @brief Disable the NORSRAM device access. 451 * @param __INSTANCE__ FSMC_NORSRAM Instance 452 * @param __BANK__ FSMC_NORSRAM Bank 453 * @retval None 454 */ 455 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 456 &= ~FSMC_BCRx_MBKEN) 457 458 /** 459 * @} 460 */ 461 #endif /* FSMC_BANK1 */ 462 463 464 465 466 /** 467 * @} 468 */ 469 470 /** 471 * @} 472 */ 473 474 /* Private functions ---------------------------------------------------------*/ 475 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions 476 * @{ 477 */ 478 479 #if defined(FSMC_BANK1) 480 /** @defgroup FSMC_LL_NORSRAM NOR SRAM 481 * @{ 482 */ 483 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 484 * @{ 485 */ 486 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, 487 FSMC_NORSRAM_InitTypeDef *Init); 488 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, 489 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 490 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, 491 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 492 uint32_t ExtendedMode); 493 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, 494 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 495 /** 496 * @} 497 */ 498 499 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 500 * @{ 501 */ 502 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 503 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 504 /** 505 * @} 506 */ 507 /** 508 * @} 509 */ 510 #endif /* FSMC_BANK1 */ 511 512 513 514 515 /** 516 * @} 517 */ 518 519 /** 520 * @} 521 */ 522 523 /** 524 * @} 525 */ 526 527 #ifdef __cplusplus 528 } 529 #endif 530 531 #endif /* STM32L1xx_LL_FSMC_H */ 532 533 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 534