1 /* 2 * Copyright (c) 2006-2022, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2013-07-20 Bernard first version 9 * 2014-04-03 Grissiom many enhancements 10 * 2018-11-22 Jesven add rt_hw_ipi_send() 11 * add rt_hw_ipi_handler_install() 12 * 2023-02-01 GuEe-GUI move macros to header 13 */ 14 15 #ifndef __PIC_GICV3_H__ 16 #define __PIC_GICV3_H__ 17 18 #include <rtdef.h> 19 20 #include <cpuport.h> 21 22 #include <drivers/pic.h> 23 #include <drivers/core/dm.h> 24 #include <dt-bindings/size.h> 25 26 /* Distributor registers */ 27 #define GICD_CTLR 0x0000 28 #define GICD_TYPER 0x0004 29 #define GICD_IIDR 0x0008 30 #define GICD_TYPER2 0x000C 31 #define GICD_STATUSR 0x0010 32 #define GICD_SETSPI_NSR 0x0040 33 #define GICD_CLRSPI_NSR 0x0048 34 #define GICD_SETSPI_SR 0x0050 35 #define GICD_CLRSPI_SR 0x0058 36 #define GICD_IGROUPR 0x0080 37 #define GICD_ISENABLER 0x0100 38 #define GICD_ICENABLER 0x0180 39 #define GICD_ISPENDR 0x0200 40 #define GICD_ICPENDR 0x0280 41 #define GICD_ISACTIVER 0x0300 42 #define GICD_ICACTIVER 0x0380 43 #define GICD_IPRIORITYR 0x0400 44 #define GICD_ICFGR 0x0C00 45 #define GICD_IGRPMODR 0x0D00 46 #define GICD_NSACR 0x0E00 47 #define GICD_IGROUPRnE 0x1000 48 #define GICD_ISENABLERnE 0x1200 49 #define GICD_ICENABLERnE 0x1400 50 #define GICD_ISPENDRnE 0x1600 51 #define GICD_ICPENDRnE 0x1800 52 #define GICD_ISACTIVERnE 0x1A00 53 #define GICD_ICACTIVERnE 0x1C00 54 #define GICD_IPRIORITYRnE 0x2000 55 #define GICD_ICFGRnE 0x3000 56 #define GICD_IROUTER 0x6000 57 #define GICD_IROUTERnE 0x8000 58 #define GICD_IDREGS 0xFFD0 59 #define GICD_PIDR2 0xFFE8 60 61 #define GICD_ITARGETSR 0x0800 62 #define GICD_SGIR 0x0F00 63 #define GICD_CPENDSGIR 0x0F10 64 #define GICD_SPENDSGIR 0x0F20 65 66 #define GICD_CTLR_RWP (1U << 31) 67 #define GICD_CTLR_nASSGIreq (1U << 8) 68 #define GICD_CTLR_DS (1U << 6) 69 #define GICD_CTLR_ARE_NS (1U << 4) 70 #define GICD_CTLR_ENABLE_G1A (1U << 1) 71 #define GICD_CTLR_ENABLE_G1 (1U << 0) 72 73 #define GICD_TYPER_RSS (1U << 26) 74 #define GICD_TYPER_LPIS (1U << 17) 75 #define GICD_TYPER_MBIS (1U << 16) 76 #define GICD_TYPER_ESPI (1U << 8) 77 #define GICD_TYPER_ID_BITS(t) ((((t) >> 19) & 0x1f) + 1) 78 #define GICD_TYPER_NUM_LPIS(t) ((((t) >> 11) & 0x1f) + 1) 79 #define GICD_TYPER_SPIS(t) ((((t) & 0x1f) + 1) * 32) 80 #define GICD_TYPER_ESPIS(t) (((t) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((t) >> 27) : 0) 81 82 /* Redistributor registers */ 83 #define GICR_CTLR 0x0000 84 #define GICR_IIDR 0x0004 85 #define GICR_TYPER 0x0008 86 #define GICR_STATUSR 0x0010 87 #define GICR_WAKER 0x0014 88 #define GICR_MPAMIDR 0x0018 89 #define GICR_PARTIDR 0x001C 90 #define GICR_SETLPIR 0x0040 91 #define GICR_CLRLPIR 0x0048 92 #define GICR_PROPBASER 0x0070 93 #define GICR_PENDBASER 0x0078 94 #define GICR_INVLPIR 0x00A0 95 #define GICR_INVALLR 0x00B0 96 #define GICR_SYNCR 0x00C0 97 #define GICR_PIDR2 GICD_PIDR2 98 99 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) 100 #define GICR_CTLR_CES (1UL << 1) 101 #define GICR_CTLR_IR (1UL << 2) 102 #define GICR_CTLR_RWP (1UL << 3) 103 104 #define GICR_TYPER_CPU_NO(r) (((r) >> 8) & 0xffff) 105 106 #define GICR_RD_BASE_SIZE (64 * SIZE_KB) 107 #define GICR_SGI_OFFSET (64 * SIZE_KB) 108 #define GICR_SGI_BASE_SIZE GICR_SGI_OFFSET 109 110 /* Re-Distributor registers, offsets from SGI_base */ 111 #define GICR_IGROUPR0 GICD_IGROUPR 112 #define GICR_ISENABLER0 GICD_ISENABLER 113 #define GICR_ICENABLER0 GICD_ICENABLER 114 #define GICR_ISPENDR0 GICD_ISPENDR 115 #define GICR_ICPENDR0 GICD_ICPENDR 116 #define GICR_ISACTIVER0 GICD_ISACTIVER 117 #define GICR_ICACTIVER0 GICD_ICACTIVER 118 #define GICR_IPRIORITYR0 GICD_IPRIORITYR 119 #define GICR_ICFGR0 GICD_ICFGR 120 #define GICR_IGRPMODR0 GICD_IGRPMODR 121 #define GICR_NSACR GICD_NSACR 122 123 #define GICR_TYPER_PLPIS (1U << 0) 124 #define GICR_TYPER_VLPIS (1U << 1) 125 #define GICR_TYPER_DIRTY (1U << 2) 126 #define GICR_TYPER_DirectLPIS (1U << 3) 127 #define GICR_TYPER_LAST (1U << 4) 128 #define GICR_TYPER_RVPEID (1U << 7) 129 #define GICR_TYPER_COM_LPI_AFF RT_GENMASK_ULL(25, 24) 130 #define GICR_TYPER_AFFINITY RT_GENMASK_ULL(63, 32) 131 132 #define GICR_INVLPIR_INTID RT_GENMASK_ULL(31, 0) 133 #define GICR_INVLPIR_VPEID RT_GENMASK_ULL(47, 32) 134 #define GICR_INVLPIR_V RT_GENMASK_ULL(63, 63) 135 136 #define GICR_INVALLR_VPEID GICR_INVLPIR_VPEID 137 #define GICR_INVALLR_V GICR_INVLPIR_V 138 139 #define GICR_VLPI_BASE_SIZE (64 * SIZE_KB) 140 #define GICR_RESERVED_SIZE (64 * SIZE_KB) 141 142 #define GIC_V3_REDIST_SIZE 0x20000 143 144 #define GICR_TYPER_NR_PPIS(t) (16 + ({ int __ppinum = (((t) >> 27) & 0x1f); __ppinum <= 2 ? __ppinum : 0; }) * 32) 145 146 #define GICR_WAKER_ProcessorSleep (1U << 1) 147 #define GICR_WAKER_ChildrenAsleep (1U << 2) 148 149 #define GICR_PROPBASER_IDBITS_MASK (0x1f) 150 #define GICR_PROPBASER_ADDRESS(x) ((x) & RT_GENMASK_ULL(51, 12)) 151 #define GICR_PENDBASER_ADDRESS(x) ((x) & RT_GENMASK_ULL(51, 16)) 152 153 /* ITS registers */ 154 #define GITS_CTLR 0x0000 155 #define GITS_IIDR 0x0004 156 #define GITS_TYPER 0x0008 157 #define GITS_MPIDR 0x0018 158 #define GITS_CBASER 0x0080 159 #define GITS_CWRITER 0x0088 160 #define GITS_CREADR 0x0090 161 #define GITS_BASER 0x0100 162 #define GITS_IDREGS_BASE 0xffd0 163 #define GITS_PIDR0 0xffe0 164 #define GITS_PIDR1 0xffe4 165 #define GITS_PIDR2 GICR_PIDR2 166 #define GITS_PIDR4 0xffd0 167 #define GITS_CIDR0 0xfff0 168 #define GITS_CIDR1 0xfff4 169 #define GITS_CIDR2 0xfff8 170 #define GITS_CIDR3 0xfffc 171 172 #define GITS_TRANSLATER 0x10040 173 174 #define GITS_SGIR 0x20020 175 176 #define GITS_SGIR_VPEID RT_GENMASK_ULL(47, 32) 177 #define GITS_SGIR_VINTID RT_GENMASK_ULL(3, 0) 178 179 #define GITS_CTLR_ENABLE (1U << 0) 180 #define GITS_CTLR_ImDe (1U << 1) 181 #define GITS_CTLR_ITS_NUMBER_SHIFT 4 182 #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT) 183 #define GITS_CTLR_QUIESCENT (1U << 31) 184 185 #define GITS_TYPER_PLPIS (1UL << 0) 186 #define GITS_TYPER_VLPIS (1UL << 1) 187 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 188 #define GITS_TYPER_ITT_ENTRY_SIZE RT_GENMASK_ULL(7, 4) 189 #define GITS_TYPER_IDBITS_SHIFT 8 190 #define GITS_TYPER_DEVBITS_SHIFT 13 191 #define GITS_TYPER_DEVBITS RT_GENMASK_ULL(17, 13) 192 #define GITS_TYPER_PTA (1UL << 19) 193 #define GITS_TYPER_HCC_SHIFT 24 194 #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff) 195 #define GITS_TYPER_VMOVP (1ULL << 37) 196 #define GITS_TYPER_VMAPP (1ULL << 40) 197 #define GITS_TYPER_SVPET RT_GENMASK_ULL(42, 41) 198 199 /* 200 * ITS commands 201 */ 202 #define GITS_CMD_MAPD 0x08 203 #define GITS_CMD_MAPC 0x09 204 #define GITS_CMD_MAPTI 0x0a 205 #define GITS_CMD_MAPI 0x0b 206 #define GITS_CMD_MOVI 0x01 207 #define GITS_CMD_DISCARD 0x0f 208 #define GITS_CMD_INV 0x0c 209 #define GITS_CMD_MOVALL 0x0e 210 #define GITS_CMD_INVALL 0x0d 211 #define GITS_CMD_INT 0x03 212 #define GITS_CMD_CLEAR 0x04 213 #define GITS_CMD_SYNC 0x05 214 215 /* ITS Config Area */ 216 #define GITS_LPI_CFG_GROUP1 (1 << 1) 217 #define GITS_LPI_CFG_ENABLED (1 << 0) 218 219 /* ITS Command Queue Descriptor */ 220 #define GITS_BASER_SHAREABILITY_SHIFT 10 221 #define GITS_BASER_INNER_CACHEABILITY_SHIFT 59 222 #define GITS_BASER_OUTER_CACHEABILITY_SHIFT 53 223 #define GITS_CBASER_VALID (1UL << 63) 224 #define GITS_CBASER_SHAREABILITY_SHIFT 10 225 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT 59 226 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT 53 227 #define GICR_PBASER_SHAREABILITY_SHIFT 10 228 #define GICR_PBASER_INNER_CACHEABILITY_SHIFT 7 229 #define GICR_PBASER_OUTER_CACHEABILITY_SHIFT 56 230 231 #define GITS_BASER_NR_REGS 8 232 #define GITS_BASERn(idx) (GITS_BASER + sizeof(rt_uint64_t) * idx) 233 234 #define GITS_BASER_VALID (1ULL << 63) 235 #define GITS_BASER_INDIRECT (1ULL << 62) 236 #define GITS_BASER_TYPE_SHIFT 56 237 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) 238 #define GITS_BASER_ENTRY_SIZE_SHIFT 48 239 #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) 240 #define GITS_BASER_PAGE_SIZE_SHIFT 8 241 #define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT) 242 #define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT) 243 #define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT) 244 #define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT) 245 #define GITS_BASER_PAGES_SHIFT 0 246 247 #define GITS_LVL1_ENTRY_SIZE 8UL 248 249 #define GITS_BASER_TYPE_NONE 0 250 #define GITS_BASER_TYPE_DEVICE 1 251 #define GITS_BASER_TYPE_VPE 2 252 #define GITS_BASER_TYPE_RESERVED3 3 253 #define GITS_BASER_TYPE_COLLECTION 4 254 #define GITS_BASER_TYPE_RESERVED5 5 255 #define GITS_BASER_TYPE_RESERVED6 6 256 #define GITS_BASER_TYPE_RESERVED7 7 257 258 #define GITS_BASER_CACHEABILITY(reg, inner_outer, type) \ 259 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) 260 #define GITS_BASER_SHAREABILITY(reg, type) \ 261 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) 262 263 #define GIC_BASER_CACHE_DnGnRnE 0x0UL /* Device-nGnRnE. */ 264 #define GIC_BASER_CACHE_NIN 0x1UL /* Normal Inner Non-cacheable. */ 265 #define GIC_BASER_CACHE_NIRAWT 0x2UL /* Normal Inner Cacheable Read-allocate, Write-through. */ 266 #define GIC_BASER_CACHE_NIRAWB 0x3UL /* Normal Inner Cacheable Read-allocate, Write-back. */ 267 #define GIC_BASER_CACHE_NIWAWT 0x4UL /* Normal Inner Cacheable Write-allocate, Write-through. */ 268 #define GIC_BASER_CACHE_NIWAWB 0x5UL /* Normal Inner Cacheable Write-allocate, Write-back. */ 269 #define GIC_BASER_CACHE_NIRAWAWT 0x6UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. */ 270 #define GIC_BASER_CACHE_NIRAWAWB 0x7UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. */ 271 #define GIC_BASER_CACHE_MASK 0x7UL 272 #define GIC_BASER_SHARE_NS 0x0UL /* Non-shareable. */ 273 #define GIC_BASER_SHARE_IS 0x1UL /* Inner Shareable. */ 274 #define GIC_BASER_SHARE_OS 0x2UL /* Outer Shareable. */ 275 #define GIC_BASER_SHARE_RES 0x3UL /* Reserved. Treated as 0b00 */ 276 #define GIC_BASER_SHARE_MASK 0x3UL 277 278 #define GITS_BASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_BASER, SHARE_IS) 279 #define GITS_BASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_BASER, SHARE_MASK) 280 #define GITS_BASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GITS_BASER, INNER, MASK) 281 #define GITS_BASER_nCnB GITS_BASER_CACHEABILITY(GITS_BASER, INNER, DnGnRnE) 282 #define GITS_BASER_nC GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIN) 283 #define GITS_BASER_RaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWT) 284 #define GITS_BASER_RaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWB) 285 #define GITS_BASER_WaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIWAWT) 286 #define GITS_BASER_WaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIWAWB) 287 #define GITS_BASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWAWT) 288 #define GITS_BASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWAWB) 289 290 #define GITS_CBASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_IS) 291 #define GITS_CBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_MASK) 292 #define GITS_CBASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) 293 #define GITS_CBASER_nCnB GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, DnGnRnE) 294 #define GITS_CBASER_nC GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIN) 295 #define GITS_CBASER_RaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWT) 296 #define GITS_CBASER_RaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWB) 297 #define GITS_CBASER_WaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIWAWT) 298 #define GITS_CBASER_WaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIWAWB) 299 #define GITS_CBASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWT) 300 #define GITS_CBASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWB) 301 302 #define GICR_PBASER_InnerShareable GITS_BASER_SHAREABILITY(GICR_PBASER, SHARE_IS) 303 #define GICR_PBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GICR_PBASER, SHARE_MASK) 304 #define GICR_PBASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, MASK) 305 #define GICR_PBASER_nCnB GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, DnGnRnE) 306 #define GICR_PBASER_nC GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIN) 307 #define GICR_PBASER_RaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWT) 308 #define GICR_PBASER_RaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWB) 309 #define GICR_PBASER_WaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIWAWT) 310 #define GICR_PBASER_WaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIWAWB) 311 #define GICR_PBASER_RaWaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWAWT) 312 #define GICR_PBASER_RaWaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWAWB) 313 314 #define GIC_EPPI_BASE_INTID 1056 315 #define GIC_ESPI_BASE_INTID 4096 316 317 #define GIC_IRQ_TYPE_LPI 0xa110c8ed 318 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) 319 320 #define read_gicreg(reg, out) rt_hw_sysreg_read(reg, out) 321 #define write_gicreg(reg, in) rt_hw_sysreg_write(reg, in) 322 323 #define ICC_CTLR_EOImode 0x2 324 #define ICC_PMR_MASK 0xff 325 #define ICC_PMR_DEFAULT 0xf0 326 #define ICC_IGRPEN1_EN 0x1 327 328 #define ICC_SGIR_AFF3_SHIFT 48 329 #define ICC_SGIR_AFF2_SHIFT 32 330 #define ICC_SGIR_AFF1_SHIFT 16 331 #define ICC_SGIR_TARGET_MASK 0xffff 332 #define ICC_SGIR_IRQN_SHIFT 24 333 #define ICC_SGIR_ROUTING_BIT (1ULL << 40) 334 335 #define ICC_SGI1R_TARGET_LIST_SHIFT 0 336 #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT) 337 #define ICC_SGI1R_TARGET_LIST_MAX 16 338 #define ICC_SGI1R_AFFINITY_1_SHIFT 16 339 #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT) 340 #define ICC_SGI1R_SGI_ID_SHIFT 24 341 #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT) 342 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 343 #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT) 344 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40 345 #define ICC_SGI1R_RS_SHIFT 44 346 #define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT) 347 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 348 #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT) 349 350 #define ICC_CTLR_EL1_CBPR_SHIFT 0 351 #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT) 352 #define ICC_CTLR_EL1_EOImode_SHIFT (1) 353 #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT) 354 #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT) 355 #define ICC_CTLR_EL1_PRI_BITS_SHIFT (8) 356 #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT) 357 #define ICC_CTLR_EL1_RSS (0x1 << 18) 358 #define ICC_CTLR_EL1_ExtRange (0x1 << 19) 359 360 struct gicv3 361 { 362 struct rt_pic parent; 363 364 int version; 365 int irq_nr; 366 rt_uint32_t gicd_typer; 367 rt_size_t line_nr; 368 rt_size_t espi_nr; 369 rt_size_t lpi_nr; 370 rt_ubase_t flags; 371 372 void *dist_base; 373 rt_size_t dist_size; 374 375 void *redist_percpu_base[RT_CPUS_NR]; 376 rt_uint64_t redist_percpu_flags[RT_CPUS_NR]; 377 rt_size_t percpu_ppi_nr[RT_CPUS_NR]; 378 379 struct 380 { 381 void *base; 382 void *base_phy; 383 rt_size_t size; 384 } *redist_regions; 385 rt_uint64_t redist_flags; 386 rt_size_t redist_stride; 387 rt_size_t redist_regions_nr; 388 389 rt_bool_t skip_init; 390 }; 391 392 #endif /* __PIC_GICV3_H__ */ 393