1 /* 2 * Copyright (c) 2020-2020, BLUETRUM Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef AB32VG1_H__ 8 #define AB32VG1_H__ 9 10 #ifndef __ASSEMBLER__ 11 #include <stdint.h> 12 #include "system_ab32vgx.h" 13 14 /*!< Interrupt Number Definition */ 15 typedef enum 16 { 17 IRQ_SW_VECTOR = 2, 18 IRQ_TMR0_VECTOR = 3, 19 IRQ_TMR1_VECTOR = 4, 20 IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */ 21 IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */ 22 IRQ_USB_VECTOR = 7, 23 IRQ_SD_VECTOR = 8, 24 IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */ 25 IRQ_SDADC_VECTOR = 10, 26 IRQ_AUDEC_VECTOR = 11, /*!< Audio codec, SBC encode and AEC FFT Interrupt */ 27 IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */ 28 IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */ 29 IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */ 30 IRQ_HSUART_VECTOR = 15, 31 IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */ 32 IRQ_I2S_VECTOR = 17, 33 IRQ_GPIO_IRQ = 18, 34 IRQ_TOTAL_NUM = 23, 35 } irq_type; 36 #endif // __ASSEMBLER__ 37 38 #ifndef __ASSEMBLER__ 39 #define SFR_RO *(volatile unsigned long const *) 40 #define SFR_WO *(volatile unsigned long*) 41 #define SFR_RW *(volatile unsigned long*) 42 #define SWINT() asm(".long 0xb0030057") 43 #define EEBREAKINT() asm(".long 0xb0040057") 44 #else 45 #define SFR_RO 46 #define SFR_WO 47 #define SFR_RW 48 #define SWINT .long 0xb0030057 49 #define EEBREAKINT .long 0xb0040057 50 #endif 51 52 #define SFR_BASE 0x00000000 53 #define SFR0_BASE (0x00000000 + 0x000) 54 #define SFR1_BASE (0x00000000 + 0x100) 55 #define SFR2_BASE (0x00000000 + 0x200) 56 #define SFR3_BASE (0x00000000 + 0x300) 57 #define SFR4_BASE (0x00000000 + 0x400) 58 #define SFR5_BASE (0x00000000 + 0x500) 59 #define SFR6_BASE (0x00000000 + 0x600) 60 #define SFR7_BASE (0x00000000 + 0x700) 61 #define SFR8_BASE (0x00000000 + 0x800) 62 #define SFR9_BASE (0x00000000 + 0x900) 63 #define SFR10_BASE (0x00000000 + 0xa00) 64 #define SFR11_BASE (0x00000000 + 0xb00) 65 #define SFR12_BASE (0x00000000 + 0xc00) 66 #define SFR13_BASE (0x00000000 + 0xd00) 67 #define SFR14_BASE (0x00000000 + 0xe00) 68 #define SFR15_BASE (0x00000000 + 0xf00) 69 70 #define RTC_WR 0x200 71 #define RTC_RD 0x100 72 73 #define RTCCNT_CMD 0x01 74 #define RTCALM_CMD 0x02 75 #define RTCRAM_CMD 0x03 76 #define RTCCON0_CMD 0x04 77 #define RTCCON1_CMD 0x05 78 #define RTCCON2_CMD 0x06 79 #define RTCCON3_CMD 0x07 80 #define RTCCON4_CMD 0x08 81 #define RTCCON5_CMD 0x09 82 #define RTCCON6_CMD 0x0a 83 #define RTCCON7_CMD 0x0b 84 #define RTCCON8_CMD 0x0c 85 #define RTCCON9_CMD 0x0d 86 #define RTCCON10_CMD 0x0e 87 88 #define FUNCMCON0 SFR_RW (SFR0_BASE + 0x07*4) 89 #define FUNCMCON1 SFR_RW (SFR0_BASE + 0x08*4) 90 #define FUNCMCON2 SFR_RW (SFR0_BASE + 0x09*4) 91 92 #define UART0CON SFR_RW (SFR0_BASE + 0x10*4) 93 #define UART0CPND SFR_WO (SFR0_BASE + 0x11*4) 94 #define UART0BAUD SFR_RW (SFR0_BASE + 0x12*4) 95 #define UART0DATA SFR_RW (SFR0_BASE + 0x13*4) 96 #define TMR0CON SFR_RW (SFR0_BASE + 0x14*4) 97 #define TMR0CPND SFR_RW (SFR0_BASE + 0x15*4) 98 #define TMR0CNT SFR_RW (SFR0_BASE + 0x16*4) 99 #define TMR0PR SFR_RW (SFR0_BASE + 0x17*4) 100 #define CLKCON0 SFR_RW (SFR0_BASE + 0x19*4) 101 #define WDTCON SFR_RW (SFR0_BASE + 0x1a*4) 102 #define RTCCON SFR_RW (SFR0_BASE + 0x1b*4) 103 #define RTCDAT SFR_RW (SFR0_BASE + 0x1c*4) 104 #define CLKCON1 SFR_RW (SFR0_BASE + 0x1d*4) 105 #define RTCCPND SFR_WO (SFR0_BASE + 0x1e*4) 106 107 #define SD0CON SFR_RW (SFR0_BASE + 0x20*4) 108 #define SD0CPND SFR_WO (SFR0_BASE + 0x21*4) 109 #define SD0BAUD SFR_RW (SFR0_BASE + 0x22*4) 110 #define SD0CMD SFR_RW (SFR0_BASE + 0x23*4) 111 #define SD0ARG3 SFR_RW (SFR0_BASE + 0x24*4) 112 #define SD0ARG2 SFR_RW (SFR0_BASE + 0x25*4) 113 #define SD0ARG1 SFR_RW (SFR0_BASE + 0x26*4) 114 #define SD0ARG0 SFR_RW (SFR0_BASE + 0x27*4) 115 #define SD0DMAADR SFR_RW (SFR0_BASE + 0x28*4) 116 #define SD0DMACNT SFR_RW (SFR0_BASE + 0x29*4) 117 #define SPI0CON SFR_RW (SFR0_BASE + 0x2a*4) 118 #define SPI0BUF SFR_RW (SFR0_BASE + 0x2b*4) 119 #define SPI0BAUD SFR_RW (SFR0_BASE + 0x2c*4) 120 #define SPI0CPND SFR_RW (SFR0_BASE + 0x2d*4) 121 #define SPI0DMACNT SFR_RW (SFR0_BASE + 0x2e*4) 122 #define SPI0DMAADR SFR_RW (SFR0_BASE + 0x2f*4) 123 124 #define UART1CON SFR_RW (SFR0_BASE + 0x30*4) 125 #define UART1CPND SFR_WO (SFR0_BASE + 0x31*4) 126 #define UART1BAUD SFR_RW (SFR0_BASE + 0x32*4) 127 #define UART1DATA SFR_RW (SFR0_BASE + 0x33*4) 128 #define TMR1CON SFR_RW (SFR0_BASE + 0x35*4) 129 #define TMR1CPND SFR_RW (SFR0_BASE + 0x36*4) 130 #define TMR1CNT SFR_RW (SFR0_BASE + 0x37*4) 131 #define TMR1PR SFR_RW (SFR0_BASE + 0x38*4) 132 #define TMR2CON SFR_RW (SFR0_BASE + 0x3a*4) 133 #define TMR2CPND SFR_RW (SFR0_BASE + 0x3b*4) 134 #define TMR2CNT SFR_RW (SFR0_BASE + 0x3c*4) 135 #define TMR2PR SFR_RW (SFR0_BASE + 0x3d*4) 136 137 //------------------------- SFR Group1 ---------------------------------------// 138 #define AUBUFDATA SFR_RW (SFR1_BASE + 0x01*4) 139 #define AUBUFCON SFR_RW (SFR1_BASE + 0x02*4) 140 #define AUBUFSTARTADDR SFR_RW (SFR1_BASE + 0x03*4) 141 #define AUBUFSIZE SFR_RW (SFR1_BASE + 0x04*4) 142 #define AUBUFFIFOCNT SFR_RW (SFR1_BASE + 0x05*4) 143 #define AUBUF1DATA SFR_RW (SFR1_BASE + 0x06*4) 144 #define AUBUF1CON SFR_RW (SFR1_BASE + 0x07*4) 145 #define AUBUF1STARTADDR SFR_RW (SFR1_BASE + 0x08*4) 146 #define AUBUF1SIZE SFR_RW (SFR1_BASE + 0x09*4) 147 #define AUBUF1FIFOCNT SFR_RW (SFR1_BASE + 0x0a*4) 148 149 #define DACDIGCON0 SFR_RW (SFR1_BASE + 0x10*4) 150 #define DACVOLCON SFR_RW (SFR1_BASE + 0x11*4) 151 #define AU0LMIXCOEF SFR_RW (SFR1_BASE + 0x12*4) 152 #define AU0RMIXCOEF SFR_RW (SFR1_BASE + 0x13*4) 153 #define AU1LMIXCOEF SFR_RW (SFR1_BASE + 0x14*4) 154 #define AU1RMIXCOEF SFR_RW (SFR1_BASE + 0x15*4) 155 156 #define AUANGCON0 SFR_RW (SFR1_BASE + 0x3c*4) 157 #define AUANGCON1 SFR_RW (SFR1_BASE + 0x3d*4) 158 #define AUANGCON2 SFR_RW (SFR1_BASE + 0x3e*4) 159 #define AUANGCON3 SFR_RW (SFR1_BASE + 0x3f*4) 160 161 #define USBCON0 SFR_RW (SFR3_BASE + 0x00*4) 162 #define USBCON1 SFR_RW (SFR3_BASE + 0x01*4) 163 #define USBCON2 SFR_RW (SFR3_BASE + 0x02*4) 164 165 #define PWRCON0 SFR_RW (SFR3_BASE + 0x1d*4) 166 #define LVDCON SFR_RW (SFR3_BASE + 0x1e*4) 167 #define CHAGCON SFR_RW (SFR3_BASE + 0x1f*4) 168 169 #define PLL0DIV SFR_RW (SFR3_BASE + 0x23*4) 170 #define PLL1DIV SFR_RW (SFR3_BASE + 0x24*4) 171 #define PLL0CON SFR_RW (SFR3_BASE + 0x26*4) 172 #define PLL1CON SFR_RW (SFR3_BASE + 0x27*4) 173 #define PLL2CON SFR_RW (SFR3_BASE + 0x28*4) 174 #define XO26MCON SFR_RW (SFR3_BASE + 0x29*4) 175 #define CLKCON2 SFR_RW (SFR3_BASE + 0x2a*4) 176 #define CLKGAT0 SFR_RW (SFR3_BASE + 0x2c*4) 177 #define LPMCON SFR_RW (SFR3_BASE + 0x2d*4) 178 #define MEMCON SFR_RW (SFR3_BASE + 0x2e*4) 179 #define CLKCON3 SFR_RW (SFR3_BASE + 0x2f*4) 180 #define CLKGAT1 SFR_RW (SFR3_BASE + 0x3f*4) 181 182 #define PWMCON SFR_RW (SFR4_BASE + 0x20*4) 183 #define PWMPRCON SFR_RW (SFR4_BASE + 0x21*4) 184 #define PWM01DUTY SFR_RW (SFR4_BASE + 0x22*4) 185 #define PWM23DUTY SFR_RW (SFR4_BASE + 0x23*4) 186 #define PWMCYCNUM SFR_RW (SFR4_BASE + 0x24*4) 187 #define PWMSTEP SFR_RW (SFR4_BASE + 0x25*4) 188 189 //0x00~0x1f reserve for CPU 190 #define PICCONCLR SFR_WO (SFR5_BASE + 0x0c*4) 191 #define PICCONSET SFR_WO (SFR5_BASE + 0x0d*4) 192 #define PICENCLR SFR_WO (SFR5_BASE + 0x0e*4) 193 #define PICENSET SFR_WO (SFR5_BASE + 0x0f*4) 194 195 #define PICCON SFR_RW (SFR5_BASE + 0x10*4) 196 #define PICEN SFR_RW (SFR5_BASE + 0x11*4) 197 #define PICPR SFR_RW (SFR5_BASE + 0x12*4) 198 #define PICADR SFR_RW (SFR5_BASE + 0x13*4) 199 #define PICPND SFR_RW (SFR5_BASE + 0x14*4) 200 #define EPICCON SFR_RW (SFR5_BASE + 0x1e*4) 201 #define EPC SFR_RW (SFR5_BASE + 0x1f*4) 202 203 #define SADCDAT0 SFR_RO (SFR5_BASE + 0x20*4) 204 #define SADCDAT1 SFR_RO (SFR5_BASE + 0x21*4) 205 #define SADCDAT2 SFR_RO (SFR5_BASE + 0x22*4) 206 #define SADCDAT3 SFR_RO (SFR5_BASE + 0x23*4) 207 #define SADCDAT4 SFR_RO (SFR5_BASE + 0x24*4) 208 #define SADCDAT5 SFR_RO (SFR5_BASE + 0x25*4) 209 #define SADCDAT6 SFR_RO (SFR5_BASE + 0x26*4) 210 #define SADCDAT7 SFR_RO (SFR5_BASE + 0x27*4) 211 #define SADCDAT8 SFR_RO (SFR5_BASE + 0x28*4) 212 #define SADCDAT9 SFR_RO (SFR5_BASE + 0x29*4) 213 #define SADCDAT10 SFR_RO (SFR5_BASE + 0x2a*4) 214 #define SADCDAT11 SFR_RO (SFR5_BASE + 0x2b*4) 215 #define SADCDAT12 SFR_RO (SFR5_BASE + 0x2c*4) 216 #define SADCDAT13 SFR_RO (SFR5_BASE + 0x2d*4) 217 #define SADCDAT14 SFR_RO (SFR5_BASE + 0x2e*4) 218 #define SADCDAT15 SFR_RO (SFR5_BASE + 0x2f*4) 219 220 #define AUANGCON1 SFR_RW (SFR1_BASE + 0x3d*4) 221 222 #define WKUPCON SFR_WO (SFR5_BASE + 0x39*4) 223 #define WKUPEDG SFR_WO (SFR5_BASE + 0x3a*4) 224 #define WKUPCPND SFR_WO (SFR5_BASE + 0x3b*4) 225 226 //------------------------- SFR Group6 ---------------------------------------// 227 #define GPIOASET SFR_RW (SFR6_BASE + 0x00*4) 228 #define GPIOACLR SFR_RW (SFR6_BASE + 0x01*4) 229 #define GPIOA SFR_RW (SFR6_BASE + 0x02*4) 230 #define GPIOADIR SFR_RW (SFR6_BASE + 0x03*4) 231 #define GPIOADE SFR_RW (SFR6_BASE + 0x04*4) 232 #define GPIOAFEN SFR_RW (SFR6_BASE + 0x05*4) 233 #define GPIOADRV SFR_RW (SFR6_BASE + 0x06*4) 234 #define GPIOAPU SFR_RW (SFR6_BASE + 0x07*4) 235 #define GPIOAPD SFR_RW (SFR6_BASE + 0x08*4) 236 #define GPIOAPU200K SFR_RW (SFR6_BASE + 0x09*4) 237 #define GPIOAPD200K SFR_RW (SFR6_BASE + 0x0a*4) 238 #define GPIOAPU300 SFR_RW (SFR6_BASE + 0x0b*4) 239 #define GPIOAPD300 SFR_RW (SFR6_BASE + 0x0c*4) 240 241 #define GPIOBSET SFR_RW (SFR6_BASE + 0x10*4) 242 #define GPIOBCLR SFR_RW (SFR6_BASE + 0x11*4) 243 #define GPIOB SFR_RW (SFR6_BASE + 0x12*4) 244 #define GPIOBDIR SFR_RW (SFR6_BASE + 0x13*4) 245 #define GPIOBDE SFR_RW (SFR6_BASE + 0x14*4) 246 #define GPIOBFEN SFR_RW (SFR6_BASE + 0x15*4) 247 #define GPIOBDRV SFR_RW (SFR6_BASE + 0x16*4) 248 #define GPIOBPU SFR_RW (SFR6_BASE + 0x17*4) 249 #define GPIOBPD SFR_RW (SFR6_BASE + 0x18*4) 250 #define GPIOBPU200K SFR_RW (SFR6_BASE + 0x19*4) 251 #define GPIOBPD200K SFR_RW (SFR6_BASE + 0x1a*4) 252 #define GPIOBPU300 SFR_RW (SFR6_BASE + 0x1b*4) 253 #define GPIOBPD300 SFR_RW (SFR6_BASE + 0x1c*4) 254 255 #define GPIOESET SFR_RW (SFR6_BASE + 0x20*4) 256 #define GPIOECLR SFR_RW (SFR6_BASE + 0x21*4) 257 #define GPIOE SFR_RW (SFR6_BASE + 0x22*4) 258 #define GPIOEDIR SFR_RW (SFR6_BASE + 0x23*4) 259 #define GPIOEDE SFR_RW (SFR6_BASE + 0x24*4) 260 #define GPIOEFEN SFR_RW (SFR6_BASE + 0x25*4) 261 #define GPIOEDRV SFR_RW (SFR6_BASE + 0x26*4) 262 #define GPIOEPU SFR_RW (SFR6_BASE + 0x27*4) 263 #define GPIOEPD SFR_RW (SFR6_BASE + 0x28*4) 264 #define GPIOEPU200K SFR_RW (SFR6_BASE + 0x29*4) 265 #define GPIOEPD200K SFR_RW (SFR6_BASE + 0x2a*4) 266 #define GPIOEPU300 SFR_RW (SFR6_BASE + 0x2b*4) 267 #define GPIOEPD300 SFR_RW (SFR6_BASE + 0x2c*4) 268 269 #define GPIOFSET SFR_RW (SFR6_BASE + 0x30*4) 270 #define GPIOFCLR SFR_RW (SFR6_BASE + 0x31*4) 271 #define GPIOF SFR_RW (SFR6_BASE + 0x32*4) 272 #define GPIOFDIR SFR_RW (SFR6_BASE + 0x33*4) 273 #define GPIOFDE SFR_RW (SFR6_BASE + 0x34*4) 274 #define GPIOFFEN SFR_RW (SFR6_BASE + 0x35*4) 275 #define GPIOFDRV SFR_RW (SFR6_BASE + 0x36*4) 276 #define GPIOFPU SFR_RW (SFR6_BASE + 0x37*4) 277 #define GPIOFPD SFR_RW (SFR6_BASE + 0x38*4) 278 #define GPIOFPU200K SFR_RW (SFR6_BASE + 0x39*4) 279 #define GPIOFPD200K SFR_RW (SFR6_BASE + 0x3a*4) 280 #define GPIOFPU300 SFR_RW (SFR6_BASE + 0x3b*4) 281 #define GPIOFPD300 SFR_RW (SFR6_BASE + 0x3c*4) 282 283 #define GPIOGSET SFR_RW (SFR7_BASE + 0x00*4) 284 #define GPIOGCLR SFR_RW (SFR7_BASE + 0x01*4) 285 #define GPIOG SFR_RW (SFR7_BASE + 0x02*4) 286 #define GPIOGDIR SFR_RW (SFR7_BASE + 0x03*4) 287 #define GPIOGDE SFR_RW (SFR7_BASE + 0x04*4) 288 #define GPIOGFEN SFR_RW (SFR7_BASE + 0x05*4) 289 #define GPIOGDRV SFR_RW (SFR7_BASE + 0x06*4) 290 #define GPIOGPU SFR_RW (SFR7_BASE + 0x07*4) 291 #define GPIOGPD SFR_RW (SFR7_BASE + 0x08*4) 292 #define GPIOGPU200K SFR_RW (SFR7_BASE + 0x09*4) 293 #define GPIOGPD200K SFR_RW (SFR7_BASE + 0x0a*4) 294 #define GPIOGPU300 SFR_RW (SFR7_BASE + 0x0b*4) 295 #define GPIOGPD300 SFR_RW (SFR7_BASE + 0x0c*4) 296 297 #define IRRXCON SFR_RW (SFR8_BASE + 0x1b*4) 298 #define IRRXDAT SFR_RW (SFR8_BASE + 0x1c*4) 299 #define IRRXCPND SFR_WO (SFR8_BASE + 0x1d*4) 300 #define IRRXERR0 SFR_WO (SFR8_BASE + 0x1e*4) 301 #define IRRXERR1 SFR_WO (SFR8_BASE + 0x1f*4) 302 303 #define USERKEY SFR_RW (SFR8_BASE + 0x20*4) 304 #define PROTCON1 SFR_RW (SFR8_BASE + 0x21*4) 305 #define FMAMFDTCON SFR_WO (SFR8_BASE + 0x29*4) 306 307 #define TMR3CON SFR_RW (SFR9_BASE + 0x00*4) 308 #define TMR3CPND SFR_WO (SFR9_BASE + 0x01*4) 309 #define TMR3CNT SFR_RW (SFR9_BASE + 0x02*4) 310 #define TMR3PR SFR_RW (SFR9_BASE + 0x03*4) 311 #define TMR3CPT SFR_RO (SFR9_BASE + 0x04*4) 312 #define TMR3DUTY0 SFR_WO (SFR9_BASE + 0x05*4) 313 #define TMR3DUTY1 SFR_WO (SFR9_BASE + 0x06*4) 314 #define TMR3DUTY2 SFR_WO (SFR9_BASE + 0x07*4) 315 #define TMR4CON SFR_RW (SFR9_BASE + 0x08*4) 316 #define TMR4CPND SFR_WO (SFR9_BASE + 0x09*4) 317 #define TMR4CNT SFR_RW (SFR9_BASE + 0x0a*4) 318 #define TMR4PR SFR_RW (SFR9_BASE + 0x0b*4) 319 #define TMR4CPT SFR_RO (SFR9_BASE + 0x0c*4) 320 #define TMR4DUTY0 SFR_WO (SFR9_BASE + 0x0d*4) 321 #define TMR4DUTY1 SFR_WO (SFR9_BASE + 0x0e*4) 322 #define TMR4DUTY2 SFR_WO (SFR9_BASE + 0x0f*4) 323 324 #define TMR5CON SFR_RW (SFR9_BASE + 0x10*4) 325 #define TMR5CPND SFR_WO (SFR9_BASE + 0x11*4) 326 #define TMR5CNT SFR_RW (SFR9_BASE + 0x12*4) 327 #define TMR5PR SFR_RW (SFR9_BASE + 0x13*4) 328 #define TMR5CPT SFR_RO (SFR9_BASE + 0x14*4) 329 #define TMR5DUTY0 SFR_WO (SFR9_BASE + 0x15*4) 330 #define TMR5DUTY1 SFR_WO (SFR9_BASE + 0x16*4) 331 #define TMR5DUTY2 SFR_WO (SFR9_BASE + 0x17*4) 332 #define UART2CON SFR_RW (SFR9_BASE + 0x18*4) 333 #define UART2CPND SFR_WO (SFR9_BASE + 0x19*4) 334 #define UART2BAUD SFR_RW (SFR9_BASE + 0x1a*4) 335 #define UART2DATA SFR_RW (SFR9_BASE + 0x1b*4) 336 #define PORTINTEDG SFR_RW (SFR9_BASE + 0x1e*4) 337 #define PORTINTEN SFR_RW (SFR9_BASE + 0x1f*4) 338 339 #define SPI1CON SFR_RW (SFR9_BASE + 0x20*4) 340 #define SPI1BUF SFR_RW (SFR9_BASE + 0x21*4) 341 #define SPI1BAUD SFR_RW (SFR9_BASE + 0x22*4) 342 #define SPI1CPND SFR_RW (SFR9_BASE + 0x23*4) 343 #define SPI1DMACNT SFR_RW (SFR9_BASE + 0x24*4) 344 #define SPI1DMAADR SFR_RW (SFR9_BASE + 0x25*4) 345 346 #endif 347