1 /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
2  *
3  * Redistribution and use in source and binary forms, with or without
4  * modification, are permitted provided that the following conditions are met:
5  * 1. Redistributions of source code must retain the above copyright
6  * notice, this list of conditions and the following disclaimer.
7  * 2. Redistributions in binary form must reproduce the above copyright
8  * notice, this list of conditions and the following disclaimer in the
9  * documentation and/or other materials provided with the distribution.
10  *
11  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
12  * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
15  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
16  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
17  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
23  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  */
25 
26 /*
27  * Copyright (c) 2006-2025, RT-Thread Development Team
28  *
29  * SPDX-License-Identifier: Apache-2.0
30  */
31 
32 #ifndef DRV_GPIO_H__
33 #define DRV_GPIO_H__
34 
35 #include "board.h"
36 
37 #define GPIO_IRQ_MAX_NUM            (64)
38 #define GPIO_MAX_NUM                (64+8)
39 #define IRQN_GPIO0_INTERRUPT        K230_IRQ_GPIO0_0
40 
41 /* k230 gpio register table */
42 #define DATA_OUTPUT         0x0
43 #define DIRECTION           0x04
44 #define DATA_SOURCE         0x08
45 #define INT_ENABLE          0x30
46 #define INT_MASK            0x34
47 #define INT_TYPE_LEVEL      0x38
48 #define INT_POLARITY        0x3c
49 #define INT_STATUS          0x40
50 #define INT_STATUS_RAW      0x44
51 #define INT_DEBOUNCE        0x48
52 #define INT_CLEAR           0x4c
53 #define DATA_INPUT          0x50
54 #define VER_ID_CODE         0x64
55 #define INT_BOTHEDGE        0x68
56 
57 #define DATA_INPUT_STRIDE   0x04 /* register stride 32 bits */
58 #define DATA_OUTPUT_STRIDE  0x0c /* register stride 3*32 bits */
59 #define DIRECTION_STRIDE    0x0c /* register stride 3*32 bits, */
60 
61 #define KD_GPIO_HIGH                1
62 #define KD_GPIO_LOW                 0
63 #define KD_GPIO_IRQ_DISABLE      0x00
64 #define KD_GPIO_IRQ_ENABLE       0x01
65 
66 /* ioctl */
67 
68 #define KD_GPIO_DM_OUTPUT           _IOW('G', 0, int)
69 #define KD_GPIO_DM_INPUT            _IOW('G', 1, int)
70 #define KD_GPIO_DM_INPUT_PULL_UP    _IOW('G', 2, int)
71 #define KD_GPIO_DM_INPUT_PULL_DOWN  _IOW('G', 3, int)
72 #define KD_GPIO_WRITE_LOW           _IOW('G', 4, int)
73 #define KD_GPIO_WRITE_HIGH          _IOW('G', 5, int)
74 
75 #define KD_GPIO_PE_RISING           _IOW('G', 7, int)
76 #define KD_GPIO_PE_FALLING          _IOW('G', 8, int)
77 #define KD_GPIO_PE_BOTH             _IOW('G', 9, int)
78 #define KD_GPIO_PE_HIGH             _IOW('G', 10, int)
79 #define KD_GPIO_PE_LOW              _IOW('G', 11, int)
80 
81 #define KD_GPIO_READ_VALUE          _IOW('G', 12, int)
82 
83 #define KD_GPIO_SET_MODE            _IOW('G', 20, int)
84 #define KD_GPIO_GET_MODE            _IOWR('G', 21, int)
85 #define KD_GPIO_SET_VALUE           _IOW('G', 22, int)
86 #define KD_GPIO_GET_VALUE           _IOWR('G', 23, int)
87 #define KD_GPIO_SET_IRQ             _IOW('G', 24, int)
88 #define KD_GPIO_GET_IRQ             _IOWR('G', 25, int)
89 
90 typedef enum _gpio_pin_edge
91 {
92     GPIO_PE_RISING,
93     GPIO_PE_FALLING,
94     GPIO_PE_BOTH,
95     GPIO_PE_HIGH,
96     GPIO_PE_LOW,
97 } gpio_pin_edge_t;
98 
99 typedef enum _gpio_drive_mode
100 {
101     GPIO_DM_OUTPUT,
102     GPIO_DM_INPUT,
103     GPIO_DM_INPUT_PULL_UP,
104     GPIO_DM_INPUT_PULL_DOWN,
105 } gpio_drive_mode_t;
106 
107 typedef enum _gpio_pin_value
108 {
109     GPIO_PV_LOW,
110     GPIO_PV_HIGH
111 } gpio_pin_value_t;
112 
113 typedef struct {
114     rt_uint16_t pin;
115     rt_uint16_t value;
116 } gpio_cfg_t;
117 
118 typedef struct {
119     rt_uint16_t pin;
120     rt_uint8_t enable;
121     rt_uint8_t mode;
122     rt_uint16_t debounce;
123     rt_uint8_t signo;
124     void *sigval;
125 } gpio_irqcfg_t;
126 
127 rt_err_t kd_pin_irq_enable(rt_base_t pin, rt_uint32_t enabled);
128 rt_err_t kd_pin_detach_irq(rt_int32_t pin);
129 rt_err_t kd_pin_attach_irq(rt_int32_t pin,rt_uint32_t mode, void (*hdr)(void *args), void *args);
130 rt_err_t kd_pin_write(rt_base_t pin, rt_base_t value);
131 rt_err_t kd_pin_mode(rt_base_t pin, rt_base_t mode);
132 int kd_pin_read(rt_base_t pin);
133 
134 #endif