1 /** 2 ****************************************************************************** 3 * @file dac_reg.h 4 * @version V1.0 5 * @date 2022-08-05 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_DAC_H__ 37 #define __HARDWARE_DAC_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 /* gpip base */ 46 #define GPIP_GPDAC_CONFIG_OFFSET (0x40) /* gpdac_config */ 47 #define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44) /* gpdac_dma_config */ 48 #define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48) /* gpdac_dma_wdata */ 49 #define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C) /* gpdac_tx_fifo_status */ 50 /* glb base */ 51 #if defined(BL702) 52 #define GLB_GPDAC_CTRL_OFFSET (0x308) /* gpdac_ctrl */ 53 #define GLB_GPDAC_ACTRL_OFFSET (0x30C) /* gpdac_actrl */ 54 #define GLB_GPDAC_BCTRL_OFFSET (0x310) /* gpdac_bctrl */ 55 #define GLB_GPDAC_DATA_OFFSET (0x314) /* gpdac_data */ 56 #else 57 #define GLB_GPDAC_CTRL_OFFSET (0x120) /* gpdac_ctrl */ 58 #define GLB_GPDAC_ACTRL_OFFSET (0x124) /* gpdac_actrl */ 59 #define GLB_GPDAC_BCTRL_OFFSET (0x128) /* gpdac_bctrl */ 60 #define GLB_GPDAC_DATA_OFFSET (0x12C) /* gpdac_data */ 61 #endif 62 /* Register Bitfield definitions *****************************************************/ 63 64 /* 0x40 : gpdac_config */ 65 #define GPIP_GPDAC_EN (1 << 0U) 66 #if defined(BL702) 67 #define GPIP_GPDAC_EN2 (1 << 1U) 68 #define GPIP_DSM_MODE_SHIFT (4U) 69 #define GPIP_DSM_MODE_MASK (0x3 << GPIP_DSM_MODE_SHIFT) 70 #endif 71 #define GPIP_GPDAC_MODE_SHIFT (8U) 72 #define GPIP_GPDAC_MODE_MASK (0x7 << GPIP_GPDAC_MODE_SHIFT) 73 #define GPIP_GPDAC_CH_A_SEL_SHIFT (16U) 74 #define GPIP_GPDAC_CH_A_SEL_MASK (0xf << GPIP_GPDAC_CH_A_SEL_SHIFT) 75 #define GPIP_GPDAC_CH_B_SEL_SHIFT (20U) 76 #define GPIP_GPDAC_CH_B_SEL_MASK (0xf << GPIP_GPDAC_CH_B_SEL_SHIFT) 77 78 /* 0x44 : gpdac_dma_config */ 79 #define GPIP_GPDAC_DMA_TX_EN (1 << 0U) 80 #if defined(BL616) || defined(BL628) || defined(BL606P) || defined(BL808) 81 #define GPIP_GPDAC_DMA_INV_MSB (1 << 1U) 82 #endif 83 #define GPIP_GPDAC_DMA_FORMAT_SHIFT (4U) 84 #define GPIP_GPDAC_DMA_FORMAT_MASK (0x3 << GPIP_GPDAC_DMA_FORMAT_SHIFT) 85 86 /* 0x48 : gpdac_dma_wdata */ 87 #define GPIP_GPDAC_DMA_WDATA_SHIFT (0U) 88 #define GPIP_GPDAC_DMA_WDATA_MASK (0xffffffff << GPIP_GPDAC_DMA_WDATA_SHIFT) 89 90 /* 0x4C : gpdac_tx_fifo_status */ 91 #define GPIP_TX_FIFO_EMPTY (1 << 0U) 92 #define GPIP_TX_FIFO_FULL (1 << 1U) 93 #define GPIP_TX_CS_SHIFT (2U) 94 #define GPIP_TX_CS_MASK (0x3 << GPIP_TX_CS_SHIFT) 95 #define GPIP_TXFIFORDPTR_SHIFT (4U) 96 #define GPIP_TXFIFORDPTR_MASK (0x7 << GPIP_TXFIFORDPTR_SHIFT) 97 #define GPIP_TXFIFOWRPTR_SHIFT (8U) 98 #define GPIP_TXFIFOWRPTR_MASK (0x3 << GPIP_TXFIFOWRPTR_SHIFT) 99 100 /* 0x308 : gpdac_ctrl */ 101 #define GLB_GPDACA_RSTN_ANA (1 << 0U) 102 #define GLB_GPDACB_RSTN_ANA (1 << 1U) 103 #define GLB_GPDAC_TEST_EN (1 << 7U) 104 #define GLB_GPDAC_REF_SEL (1 << 8U) 105 #define GLB_GPDAC_TEST_SEL_SHIFT (9U) 106 #define GLB_GPDAC_TEST_SEL_MASK (0x7 << GLB_GPDAC_TEST_SEL_SHIFT) 107 #if defined(BL616) || defined(BL628) || defined(BL606P) || defined(BL808) 108 #define GLB_GPDAC_ANA_CLK_SEL (1 << 12U) 109 #define GLB_GPDAC_DAT_CHA_SEL (1 << 13U) 110 #define GLB_GPDAC_DAT_CHB_SEL (1 << 14U) 111 #endif 112 #define GLB_GPDAC_RESERVED_SHIFT (24U) 113 #define GLB_GPDAC_RESERVED_MASK (0xff << GLB_GPDAC_RESERVED_SHIFT) 114 115 /* 0x30C : gpdac_actrl */ 116 #define GLB_GPDAC_A_EN (1 << 0U) 117 #define GLB_GPDAC_IOA_EN (1 << 1U) 118 #define GLB_GPDAC_A_RNG_SHIFT (18U) 119 #define GLB_GPDAC_A_RNG_MASK (0x3 << GLB_GPDAC_A_RNG_SHIFT) 120 #define GLB_GPDAC_A_OUTMUX_SHIFT (20U) 121 #define GLB_GPDAC_A_OUTMUX_MASK (0x7 << GLB_GPDAC_A_OUTMUX_SHIFT) 122 123 /* 0x310 : gpdac_bctrl */ 124 #define GLB_GPDAC_B_EN (1 << 0U) 125 #define GLB_GPDAC_IOB_EN (1 << 1U) 126 #define GLB_GPDAC_B_RNG_SHIFT (18U) 127 #define GLB_GPDAC_B_RNG_MASK (0x3 << GLB_GPDAC_B_RNG_SHIFT) 128 #define GLB_GPDAC_B_OUTMUX_SHIFT (20U) 129 #define GLB_GPDAC_B_OUTMUX_MASK (0x7 << GLB_GPDAC_B_OUTMUX_SHIFT) 130 131 /* 0x314 : gpdac_data */ 132 #if defined(BL702) || defined(BL602) || defined(BL606P) || defined(BL808) 133 #define GLB_GPDAC_B_DATA_SHIFT (0U) 134 #define GLB_GPDAC_B_DATA_MASK (0x3ff << GLB_GPDAC_B_DATA_SHIFT) 135 #define GLB_GPDAC_A_DATA_SHIFT (16U) 136 #define GLB_GPDAC_A_DATA_MASK (0x3ff << GLB_GPDAC_A_DATA_SHIFT) 137 #elif defined(BL616) || defined(BL628) 138 #define GLB_GPDAC_B_DATA_SHIFT (0U) 139 #define GLB_GPDAC_B_DATA_MASK (0x1fff << GLB_GPDAC_B_DATA_SHIFT) 140 #define GLB_GPDAC_A_DATA_SHIFT (16U) 141 #define GLB_GPDAC_A_DATA_MASK (0x1fff << GLB_GPDAC_A_DATA_SHIFT) 142 #endif 143 144 #endif /* __HARDWARE_DAC_H__ */ 145