1 #ifndef __ASM9260T_REGS_H__ 2 #define __ASM9260T_REGS_H__ 3 //////////////////////////////////////////////////////////////////////////////// 4 5 typedef volatile unsigned char *VP8; 6 typedef volatile unsigned short *VP16; 7 typedef volatile unsigned long *VP32; 8 9 #define __I volatile const /*!< Defines 'read only' permissions */ 10 #define __O volatile /*!< Defines 'write only' permissions */ 11 #define __IO volatile /*!< Defines 'read / write' permissions */ 12 13 #define outb(v, r) do{*((VP8)(r))=(v);}while(0) 14 #define outw(v, r) do{*((VP16)(r))=(v);}while(0) 15 #define outl(v, r) do{*((VP32)(r))=(v);}while(0) 16 17 #define inb(r) (*((VP8)(r))) 18 #define inw(r) (*((VP16)(r))) 19 #define inl(r) (*((VP32)(r))) 20 21 #define REG_VAL(r) (((unsigned long)(r))+0x00) 22 #define REG_SET(r) (((unsigned long)(r))+0x04) 23 #define REG_CLR(r) (((unsigned long)(r))+0x08) 24 #define REG_TOG(r) (((unsigned long)(r))+0x0C) 25 26 //////////////////////////////////////////////////////////////////////////////// 27 // SYSTEM CONFIG 28 #define HW_PRESETCTRL0 0x80040000 29 #define HW_PRESETCTRL1 0x80040010 30 #define HW_AHBCLKCTRL0 0x80040020 31 #define HW_AHBCLKCTRL1 0x80040030 32 #define HW_SYSTCKCAL 0x80040040 33 #define HW_SYSPLLCTRL 0x80040100 34 #define HW_SYSPLLSTAT 0x80040104 35 #define HW_SYSRSTSTAT 0x80040110 36 #define HW_MAINCLKSEL 0x80040120 37 #define HW_MAINCLKUEN 0x80040124 38 #define HW_UARTCLKSEL 0x80040128 39 #define HW_UARTCLKUEN 0x8004012C 40 #define HW_I2S0CLKSEL 0x80040130 41 #define HW_I2S0CLKUEN 0x80040134 42 #define HW_I2S1CLKSEL 0x80040138 43 #define HW_I2S1CLKUEN 0x8004013C 44 #define HW_USBCLKSEL 0x80040140 45 #define HW_USBCLKUEN 0x80040144 46 #define HW_WDTCLKSEL 0x80040160 47 #define HW_WDTCLKUEN 0x80040164 48 #define HW_OUTCLKSEL 0x80040170 49 #define HW_OUTCLKUEN 0x80040174 50 #define HW_CPUCLKDIV 0x8004017C 51 #define HW_SYSAHBCLKDIV 0x80040180 52 #define HW_I2S1_MCLKDIV 0x80040188 53 #define HW_I2S1_SCLKDIV 0x8004018C 54 #define HW_I2S0_MCLKDIV 0x80040190 55 #define HW_I2S0_SCLKDIV 0x80040194 56 #define HW_UART0CLKDIV 0x80040198 57 #define HW_UART1CLKDIV 0x8004019C 58 #define HW_UART2CLKDIV 0x800401A0 59 #define HW_UART3CLKDIV 0x800401A4 60 #define HW_UART4CLKDIV 0x800401A8 61 #define HW_UART5CLKDIV 0x800401AC 62 #define HW_UART6CLKDIV 0x800401B0 63 #define HW_UART7CLKDIV 0x800401B4 64 #define HW_UART8CLKDIV 0x800401B8 65 #define HW_UART9CLKDIV 0x800401BC 66 #define HW_SPI0CLKDIV 0x800401C0 67 #define HW_SPI1CLKDIV 0x800401C4 68 #define HW_QUADSPI0CLKDIV 0x800401C8 69 #define HW_SSP0CLKDIV 0x800401D0 70 #define HW_NANDCLKDIV 0x800401D4 71 #define HW_TRACECLKDIV 0x800401E0 72 #define HW_CAMMCLKDIV 0x800401E8 73 #define HW_WDTCLKDIV 0x800401EC 74 #define HW_USBCLKDIV 0x800401F0 75 #define HW_OUTCLKDIV 0x800401F4 76 #define HW_MACCLKDIV 0x800401F8 77 #define HW_LCDCLKDIV 0x800401FC 78 #define HW_ADCCLKDIV 0x80040200 79 #define HW_PDRUNCFG 0x80040238 80 #define HW_MATRIXPRI0 0x80040300 81 #define HW_MATRIXPRI1 0x80040304 82 #define HW_MATRIXPRI2 0x80040308 83 #define HW_MATRIXPRI3 0x8004030C 84 #define HW_MATRIXPRI4 0x80040310 85 #define HW_MATRIXPRI5 0x80040314 86 #define HW_MATRIXPRI6 0x80040318 87 #define HW_MATRIXPRI7 0x8004031C 88 #define HW_MATRIXPRI8 0x80040320 89 #define HW_MATRIXPRI9 0x80040324 90 #define HW_MATRIXPRI10 0x80040328 91 #define HW_MATRIXPRI11 0x8004032C 92 #define HW_MATRIXPRI12 0x80040330 93 #define HW_MATRIXPRI13 0x80040334 94 #define HW_MATRIXPRI14 0x80040338 95 #define HW_MATRIXPRI15 0x8004033C 96 #define HW_EMI_CTRL 0x8004034C 97 #define HW_RISC_CTRL 0x80040350 98 #define HW_DMA_CTRL 0x80040354 99 #define HW_MACPHY_SEL 0x80040360 100 #define HW_USB_CTRL 0x80040368 101 #define HW_ANA_CTRL 0x80040370 102 #define HW_USB0_TEST 0x80040380 103 #define HW_USB1_TEST 0x80040390 104 #define HW_USB0_RSTPARA 0x800403A0 105 #define HW_USB1_RSTPARA 0x800403B0 106 #define HW_DEVICEID 0x80040400 107 #define HW_PCON_ADDR 0x80040500 108 109 //////////////////////////////////////////////////////////////////////////////// 110 // EMI 111 #define HW_EMI_SCONR 0x80700000 112 #define HW_EMI_STMG0R 0x80700004 113 #define HW_EMI_STMG1R 0x80700008 114 #define HW_EMI_SCTLR 0x8070000C 115 #define HW_EMI_SREFR 0x80700010 116 #define HW_EMI_SCSLR0_LOW 0x80700014 117 #define HW_EMI_SCSLR1_LOW 0x80700018 118 #define HW_EMI_SCSLR2_LOW 0x8070001c 119 #define HW_EMI_SCSLR3_LOW 0x80700020 120 #define HW_EMI_SCSLR4_LOW 0x80700024 121 #define HW_EMI_SCSLR5_LOW 0x80700028 122 #define HW_EMI_SCSLR6_LOW 0x8070002c 123 #define HW_EMI_SCSLR7_LOW 0x80700030 124 125 #define HW_EMI_SMSKR0 0x80700054 126 #define HW_EMI_SMSKR1 0x80700058 127 #define HW_EMI_SMSKR2 0x8070005c 128 #define HW_EMI_SMSKR3 0x80700060 129 #define HW_EMI_SMSKR4 0x80700064 130 #define HW_EMI_SMSKR5 0x80700068 131 #define HW_EMI_SMSKR6 0x8070006c 132 #define HW_EMI_SMSKR7 0x80700070 133 134 #define HW_EMI_CSALIAS0_LOW 0x80700074 135 #define HW_EMI_CSALIAS1_LOW 0x80700078 136 137 #define HW_EMI_CSREMAP0_LOW 0x80700084 138 #define HW_EMI_CSREMAP1_LOW 0x80700088 139 140 #define HW_EMI_SMTMGR_SET0 0x80700094 141 #define HW_EMI_SMTMGR_SET1 0x80700098 142 #define HW_EMI_SMTMGR_SET2 0x8070009c 143 144 #define HW_EMI_FLASH_TRPDR 0x807000a0 145 #define HW_EMI_SMCTLR 0x807000a4 146 #define HW_EMI_EXN_MODE_REG 0x807000ac 147 148 //////////////////////////////////////////////////////////////////////////////// 149 // IOCON 150 #define HW_IOCON_PIO_BASE 0x80044000 151 #define HW_IOCON_SCKLOC 0x800442c0 152 #define HW_IOCON(port,pin) (HW_IOCON_PIO_BASE|(((port)<<5)|((pin)<<2))) 153 154 //////////////////////////////////////////////////////////////////////////////// 155 // GPIO 156 #define HW_GPIO_DATA_BASE 0x50000000 157 158 #define HW_GPIO_DMA_CTRL 0x50000010 159 #define HW_GPIO_DMA_DATA 0x50000020 160 #define HW_GPIO_DMA_PADCTRL0 0x50000030 161 #define HW_GPIO_DMA_PADCTRL1 0x50000040 162 #define HW_GPIO_DMA_PADCTRL2 0x50000050 163 #define HW_GPIO_DMA_PADCTRL3 0x50000060 164 #define HW_GPIO_DMA_CTRL1 0x50000070 165 #define HW_GPIO_DMA_CTRL2 0x50000080 166 #define HW_GPIO_DMA_CTRL3 0x50000090 167 #define HW_GPIO_DMA_CTRL4 0x500000a0 168 169 #define HW_GPIO_DATA0 0x50000000 170 #define HW_GPIO_DATA1 0x50010000 171 #define HW_GPIO_DATA2 0x50020000 172 #define HW_GPIO_DATA3 0x50030000 173 #define HW_GPIO_DATA4 0x50040000 174 175 #define HW_GPIO_DIR0 0x50008000 176 #define HW_GPIO_DIR1 0x50018000 177 #define HW_GPIO_DIR2 0x50028000 178 #define HW_GPIO_DIR3 0x50038000 179 #define HW_GPIO_DIR4 0x50048000 180 181 #define HW_GPIO_IS0 0x50008010 182 #define HW_GPIO_IS1 0x50018010 183 #define HW_GPIO_IS2 0x50028010 184 #define HW_GPIO_IS3 0x50038010 185 #define HW_GPIO_IS4 0x50048010 186 187 #define HW_GPIO_IBE0 0x50008020 188 #define HW_GPIO_IBE1 0x50018020 189 #define HW_GPIO_IBE2 0x50028020 190 #define HW_GPIO_IBE3 0x50038020 191 #define HW_GPIO_IBE4 0x50048020 192 193 #define HW_GPIO_IEV0 0x50008030 194 #define HW_GPIO_IEV1 0x50018030 195 #define HW_GPIO_IEV2 0x50028030 196 #define HW_GPIO_IEV3 0x50038030 197 #define HW_GPIO_IEV4 0x50048030 198 199 #define HW_GPIO_IE0 0x50008040 200 #define HW_GPIO_IE1 0x50018040 201 #define HW_GPIO_IE2 0x50028040 202 #define HW_GPIO_IE3 0x50038040 203 #define HW_GPIO_IE4 0x50048040 204 205 #define HW_GPIO_RIS0 0x50008050 206 #define HW_GPIO_RIS1 0x50018050 207 #define HW_GPIO_RIS2 0x50028050 208 #define HW_GPIO_RIS3 0x50038050 209 #define HW_GPIO_RIS4 0x50048050 210 211 #define HW_GPIO_MIS0 0x50008060 212 #define HW_GPIO_MIS1 0x50018060 213 #define HW_GPIO_MIS2 0x50028060 214 #define HW_GPIO_MIS3 0x50038060 215 #define HW_GPIO_MIS4 0x50048060 216 217 #define HW_GPIO_IC0 0x50008070 218 #define HW_GPIO_IC1 0x50018070 219 #define HW_GPIO_IC2 0x50028070 220 #define HW_GPIO_IC3 0x50038070 221 #define HW_GPIO_IC4 0x50048070 222 223 #define HW_GPIO_DATAMASK0 0x50008080 224 #define HW_GPIO_DATAMASK1 0x50018080 225 #define HW_GPIO_DATAMASK2 0x50028080 226 #define HW_GPIO_DATAMASK3 0x50038080 227 #define HW_GPIO_DATAMASK4 0x50048080 228 229 //////////////////////////////////////////////////////////////////////////////// 230 // Quad-SPI0 231 #define QSPI0_BASE_ADDRESS 0x80068000 232 #define HW_QSPI0_CTRL0 0x80068000 233 #define HW_QSPI0_CTRL1 0x80068010 234 #define HW_QSPI0_CMD 0x80068020 235 #define HW_QSPI0_TIMING 0x80068030 236 #define HW_QSPI0_DATA 0x80068040 237 #define HW_QSPI0_STATUS 0x80068050 238 #define HW_QSPI0_DEBUG0 0x80068060 239 #define HW_QSPI0_XFER 0x80068070 240 241 ///////////////////////////////////////////////////////// 242 //DMA0 243 #define HW_DMA0_SAR0 0x80100000 244 #define HW_DMA0_DAR0 0x80100008 245 #define HW_DMA0_LLP0 0x80100010 246 #define HW_DMA0_CTL0 0x80100018 247 #define HW_DMA0_SSTAT0 0x80100020 248 #define HW_DMA0_DSTAT0 0x80100028 249 #define HW_DMA0_SSTATAR0 0x80100030 250 #define HW_DMA0_DSTATAR0 0x80100038 251 #define HW_DMA0_CFG0 0x80100040 252 #define HW_DMA0_SGR0 0x80100048 253 #define HW_DMA0_DSR0 0x80100050 254 255 #define HW_DMA0_SAR1 0x80100058 256 #define HW_DMA0_DAR1 0x80100060 257 #define HW_DMA0_LLP1 0x80100068 258 #define HW_DMA0_CTL1 0x80100070 259 #define HW_DMA0_SSTAT1 0x80100078 260 #define HW_DMA0_DSTAT1 0x80100080 261 #define HW_DMA0_SSTATAR1 0x80100088 262 #define HW_DMA0_DSTATAR1 0x80100090 263 #define HW_DMA0_CFG1 0x80100098 264 #define HW_DMA0_SGR1 0x801000a0 265 #define HW_DMA0_DSR1 0x801000a8 266 267 #define HW_DMA0_SAR2 0x801000b0 268 #define HW_DMA0_DAR2 0x801000b8 269 #define HW_DMA0_LLP2 0x801000c0 270 #define HW_DMA0_CTL2 0x801000c8 271 #define HW_DMA0_SSTAT2 0x801000d0 272 #define HW_DMA0_DSTAT2 0x801000d8 273 #define HW_DMA0_SSTATAR2 0x801000e0 274 #define HW_DMA0_DSTATAR2 0x801000e8 275 #define HW_DMA0_CFG2 0x801000f0 276 #define HW_DMA0_SGR2 0x801000f8 277 #define HW_DMA0_DSR2 0x80100100 278 279 #define HW_DMA0_SAR3 0x80100108 280 #define HW_DMA0_DAR3 0x80100110 281 #define HW_DMA0_LLP3 0x80100118 282 #define HW_DMA0_CTL3 0x80100120 283 #define HW_DMA0_SSTAT3 0x80100128 284 #define HW_DMA0_DSTAT3 0x80100130 285 #define HW_DMA0_SSTATAR3 0x80100138 286 #define HW_DMA0_DSTATAR3 0x80100140 287 #define HW_DMA0_CFG3 0x80100148 288 #define HW_DMA0_SGR3 0x80100150 289 #define HW_DMA0_DSR3 0x80100158 290 291 #define HW_DMA0_SAR4 0x80100160 292 #define HW_DMA0_DAR4 0x80100168 293 #define HW_DMA0_LLP4 0x80100170 294 #define HW_DMA0_CTL4 0x80100178 295 #define HW_DMA0_SSTAT4 0x80100180 296 #define HW_DMA0_DSTAT4 0x80100188 297 #define HW_DMA0_SSTATAR4 0x80100190 298 #define HW_DMA0_DSTATAR4 0x80100198 299 #define HW_DMA0_CFG4 0x801001a0 300 #define HW_DMA0_SGR4 0x801001a8 301 #define HW_DMA0_DSR4 0x801001b0 302 303 #define HW_DMA0_SAR5 0x801001b8 304 #define HW_DMA0_DAR5 0x801001c0 305 #define HW_DMA0_LLP5 0x801001c8 306 #define HW_DMA0_CTL5 0x801001d0 307 #define HW_DMA0_SSTAT5 0x801001d8 308 #define HW_DMA0_DSTAT5 0x801001e0 309 #define HW_DMA0_SSTATAR5 0x801001e8 310 #define HW_DMA0_DSTATAR5 0x801001f0 311 #define HW_DMA0_CFG5 0x801001f8 312 #define HW_DMA0_SGR5 0x80100200 313 #define HW_DMA0_DSR5 0x80100208 314 315 #define HW_DMA0_SAR6 0x80100210 316 #define HW_DMA0_DAR6 0x80100218 317 #define HW_DMA0_LLP6 0x80100220 318 #define HW_DMA0_CTL6 0x80100228 319 #define HW_DMA0_SSTAT6 0x80100230 320 #define HW_DMA0_DSTAT6 0x80100238 321 #define HW_DMA0_SSTATAR6 0x80100240 322 #define HW_DMA0_DSTATAR6 0x80100248 323 #define HW_DMA0_CFG6 0x80100250 324 #define HW_DMA0_SGR6 0x80100258 325 #define HW_DMA0_DSR6 0x80100260 326 327 #define HW_DMA0_SAR7 0x80100268 328 #define HW_DMA0_DAR7 0x80100270 329 #define HW_DMA0_LLP7 0x80100278 330 #define HW_DMA0_CTL7 0x80100280 331 #define HW_DMA0_SSTAT7 0x80100288 332 #define HW_DMA0_DSTAT7 0x80100290 333 #define HW_DMA0_SSTATAR7 0x80100298 334 #define HW_DMA0_DSTATAR7 0x801002a0 335 #define HW_DMA0_CFG7 0x801002a8 336 #define HW_DMA0_SGR7 0x801002b0 337 #define HW_DMA0_DSR7 0x801002b8 338 339 #define HW_DMA0_RawTFR 0x801002c0 340 #define HW_DMA0_RawBLOCK 0x801002c8 341 #define HW_DMA0_RawSRCTRAN 0x801002d0 342 #define HW_DMA0_RawDSTTRAN 0x801002d8 343 #define HW_DMA0_RawERR 0x801002e0 344 345 #define HW_DMA0_StatusTFR 0x801002e8 346 #define HW_DMA0_StatusBLOCK 0x801002f0 347 #define HW_DMA0_StatusSRCTRAN 0x801002f8 348 #define HW_DMA0_StatusDSTTRAN 0x80100300 349 #define HW_DMA0_StatusERR 0x80100308 350 351 #define HW_DMA0_MaskTFR 0x80100310 352 #define HW_DMA0_MaskBLOCK 0x80100318 353 #define HW_DMA0_MaskSRCTRAN 0x80100320 354 #define HW_DMA0_MaskDSTTRAN 0x80100328 355 #define HW_DMA0_MaskERR 0x80100330 356 357 #define HW_DMA0_ClearTFR 0x80100338 358 #define HW_DMA0_ClearBLOCK 0x80100340 359 #define HW_DMA0_ClearSRCTRAN 0x80100348 360 #define HW_DMA0_ClearDSTTRAN 0x80100350 361 #define HW_DMA0_ClearERR 0x80100358 362 363 #define HW_DMA0_STATUSINT 0x80100360 364 365 #define HW_DMA0_ReqSrcReg 0x80100368 366 #define HW_DMA0_ReqDstReg 0x80100370 367 #define HW_DMA0_SglReqSrcReg 0x80100378 368 #define HW_DMA0_SglReqDstReg 0x80100380 369 #define HW_DMA0_LstSrcReg 0x80100388 370 #define HW_DMA0_LstDstReg 0x80100390 371 372 #define HW_DMA0_DMACFGREG 0x80100398 373 #define HW_DMA0_CHENREG 0x801003a0 374 375 //////////////////////////////////////////////////////////////////////////////// 376 // DMA1 377 #define HW_DMA1_SAR0 0x80200000 378 #define HW_DMA1_DAR0 0x80200008 379 #define HW_DMA1_LLP0 0x80200010 380 #define HW_DMA1_CTL0 0x80200018 381 #define HW_DMA1_SSTAT0 0x80200020 382 #define HW_DMA1_DSTAT0 0x80200028 383 #define HW_DMA1_SSTATAR0 0x80200030 384 #define HW_DMA1_DSTATAR0 0x80200038 385 #define HW_DMA1_CFG0 0x80200040 386 #define HW_DMA1_SGR0 0x80200048 387 #define HW_DMA1_DSR0 0x80200050 388 389 #define HW_DMA1_SAR1 0x80200058 390 #define HW_DMA1_DAR1 0x80200060 391 #define HW_DMA1_LLP1 0x80200068 392 #define HW_DMA1_CTL1 0x80200070 393 #define HW_DMA1_SSTAT1 0x80200078 394 #define HW_DMA1_DSTAT1 0x80200080 395 #define HW_DMA1_SSTATAR1 0x80200088 396 #define HW_DMA1_DSTATAR1 0x80200090 397 #define HW_DMA1_CFG1 0x80200098 398 #define HW_DMA1_SGR1 0x802000a0 399 #define HW_DMA1_DSR1 0x802000a8 400 401 #define HW_DMA1_SAR2 0x802000b0 402 #define HW_DMA1_DAR2 0x802000b8 403 #define HW_DMA1_LLP2 0x802000c0 404 #define HW_DMA1_CTL2 0x802000c8 405 #define HW_DMA1_SSTAT2 0x802000d0 406 #define HW_DMA1_DSTAT2 0x802000d8 407 #define HW_DMA1_SSTATAR2 0x802000e0 408 #define HW_DMA1_DSTATAR2 0x802000e8 409 #define HW_DMA1_CFG2 0x802000f0 410 #define HW_DMA1_SGR2 0x802000f8 411 #define HW_DMA1_DSR2 0x80200100 412 413 #define HW_DMA1_SAR3 0x80200108 414 #define HW_DMA1_DAR3 0x80200110 415 #define HW_DMA1_LLP3 0x80200118 416 #define HW_DMA1_CTL3 0x80200120 417 #define HW_DMA1_SSTAT3 0x80200128 418 #define HW_DMA1_DSTAT3 0x80200130 419 #define HW_DMA1_SSTATAR3 0x80200138 420 #define HW_DMA1_DSTATAR3 0x80200140 421 #define HW_DMA1_CFG3 0x80200148 422 #define HW_DMA1_SGR3 0x80200150 423 #define HW_DMA1_DSR3 0x80200158 424 425 #define HW_DMA1_SAR4 0x80200160 426 #define HW_DMA1_DAR4 0x80200168 427 #define HW_DMA1_LLP4 0x80200170 428 #define HW_DMA1_CTL4 0x80200178 429 #define HW_DMA1_SSTAT4 0x80200180 430 #define HW_DMA1_DSTAT4 0x80200188 431 #define HW_DMA1_SSTATAR4 0x80200190 432 #define HW_DMA1_DSTATAR4 0x80200198 433 #define HW_DMA1_CFG4 0x802001a0 434 #define HW_DMA1_SGR4 0x802001a8 435 #define HW_DMA1_DSR4 0x802001b0 436 437 #define HW_DMA1_SAR5 0x802001b8 438 #define HW_DMA1_DAR5 0x802001c0 439 #define HW_DMA1_LLP5 0x802001c8 440 #define HW_DMA1_CTL5 0x802001d0 441 #define HW_DMA1_SSTAT5 0x802001d8 442 #define HW_DMA1_DSTAT5 0x802001e0 443 #define HW_DMA1_SSTATAR5 0x802001e8 444 #define HW_DMA1_DSTATAR5 0x802001f0 445 #define HW_DMA1_CFG5 0x802001f8 446 #define HW_DMA1_SGR5 0x80200200 447 #define HW_DMA1_DSR5 0x80200208 448 449 #define HW_DMA1_SAR6 0x80200210 450 #define HW_DMA1_DAR6 0x80200218 451 #define HW_DMA1_LLP6 0x80200220 452 #define HW_DMA1_CTL6 0x80200228 453 #define HW_DMA1_SSTAT6 0x80200230 454 #define HW_DMA1_DSTAT6 0x80200238 455 #define HW_DMA1_SSTATAR6 0x80200240 456 #define HW_DMA1_DSTATAR6 0x80200248 457 #define HW_DMA1_CFG6 0x80200250 458 #define HW_DMA1_SGR6 0x80200258 459 #define HW_DMA1_DSR6 0x80200260 460 461 #define HW_DMA1_SAR7 0x80200268 462 #define HW_DMA1_DAR7 0x80200270 463 #define HW_DMA1_LLP7 0x80200278 464 #define HW_DMA1_CTL7 0x80200280 465 #define HW_DMA1_SSTAT7 0x80200288 466 #define HW_DMA1_DSTAT7 0x80200290 467 #define HW_DMA1_SSTATAR7 0x80200298 468 #define HW_DMA1_DSTATAR7 0x802002a0 469 #define HW_DMA1_CFG7 0x802002a8 470 #define HW_DMA1_SGR7 0x802002b0 471 #define HW_DMA1_DSR7 0x802002b8 472 473 #define HW_DMA1_RawTFR 0x802002c0 474 #define HW_DMA1_RawBLOCK 0x802002c8 475 #define HW_DMA1_RawSRCTRAN 0x802002d0 476 #define HW_DMA1_RawDSTTRAN 0x802002d8 477 #define HW_DMA1_RawERR 0x802002e0 478 479 #define HW_DMA1_StatusTFR 0x802002e8 480 #define HW_DMA1_StatusBLOCK 0x802002f0 481 #define HW_DMA1_StatusSRCTRAN 0x802002f8 482 #define HW_DMA1_StatusDSTTRAN 0x80200300 483 #define HW_DMA1_StatusERR 0x80200308 484 485 #define HW_DMA1_MaskTFR 0x80200310 486 #define HW_DMA1_MaskBLOCK 0x80200318 487 #define HW_DMA1_MaskSRCTRAN 0x80200320 488 #define HW_DMA1_MaskDSTTRAN 0x80200328 489 #define HW_DMA1_MaskERR 0x80200330 490 491 #define HW_DMA1_ClearTFR 0x80200338 492 #define HW_DMA1_ClearBLOCK 0x80200340 493 #define HW_DMA1_ClearSRCTRAN 0x80200348 494 #define HW_DMA1_ClearDSTTRAN 0x80200350 495 #define HW_DMA1_ClearERR 0x80200358 496 497 #define HW_DMA1_STATUSINT 0x80200360 498 499 #define HW_DMA1_ReqSrcReg 0x80200368 500 #define HW_DMA1_ReqDstReg 0x80200370 501 #define HW_DMA1_SglReqSrcReg 0x80200378 502 #define HW_DMA1_SglReqDstReg 0x80200380 503 #define HW_DMA1_LstSrcReg 0x80200388 504 #define HW_DMA1_LstDstReg 0x80200390 505 506 #define HW_DMA1_DMACFGREG 0x80200398 507 #define HW_DMA1_CHENREG 0x802003a0 508 509 //////////////////////////////////////////////////////////////////////////////// 510 // ICOLL 511 #define HW_ICOLL_VECTOR 0x80054000 512 #define HW_ICOLL_LEVELACK 0x80054010 513 #define HW_ICOLL_CTRL 0x80054020 514 #define HW_ICOLL_STAT 0x80054030 515 #define HW_ICOLL_RAW0 0x80054040 516 #define HW_ICOLL_RAW1 0x80054050 517 #define HW_ICOLL_PRIORITY0 0x80054060 518 #define HW_ICOLL_PRIORITY1 0x80054070 519 #define HW_ICOLL_PRIORITY2 0x80054080 520 #define HW_ICOLL_PRIORITY3 0x80054090 521 #define HW_ICOLL_PRIORITY4 0x800540A0 522 #define HW_ICOLL_PRIORITY5 0x800540B0 523 #define HW_ICOLL_PRIORITY6 0x800540C0 524 #define HW_ICOLL_PRIORITY7 0x800540D0 525 #define HW_ICOLL_PRIORITY8 0x800540E0 526 #define HW_ICOLL_PRIORITY9 0x800540F0 527 #define HW_ICOLL_PRIORITY10 0x80054100 528 #define HW_ICOLL_PRIORITY11 0x80054110 529 #define HW_ICOLL_PRIORITY12 0x80054120 530 #define HW_ICOLL_PRIORITY13 0x80054130 531 #define HW_ICOLL_PRIORITY14 0x80054140 532 #define HW_ICOLL_PRIORITY15 0x80054150 533 #define HW_ICOLL_VBASE 0x80054160 534 #define HW_ICOLL_DEBUG 0x80054170 535 #define HW_ICOLL_DBGREAD0 0x80054180 536 #define HW_ICOLL_DBGREAD1 0x80054190 537 #define HW_ICOLL_DBGFLAG 0x800541A0 538 #define HW_ICOLL_DBGREQUEST0 0x800541B0 539 #define HW_ICOLL_DBGREQUEST1 0x800541C0 540 #define HW_ICOLL_CLEAR0 0x800541D0 541 #define HW_ICOLL_CLEAR1 0x800541E0 542 #define HW_ICOLL_UNDEF_VECTOR 0x800541F0 543 544 //////////////////////////////////////////////////////////////////////////////// 545 // TIMER0 546 #define HW_TIMER0_IR 0x80088000 547 #define HW_TIMER0_TCR 0x80088010 548 #define HW_TIMER0_DIR 0x80088020 549 #define HW_TIMER0_TC0 0x80088030 550 #define HW_TIMER0_TC1 0x80088040 551 #define HW_TIMER0_TC2 0x80088050 552 #define HW_TIMER0_TC3 0x80088060 553 #define HW_TIMER0_PR 0x80088070 554 #define HW_TIMER0_PC 0x80088080 555 #define HW_TIMER0_MCR 0x80088090 556 #define HW_TIMER0_MR0 0x800880a0 557 #define HW_TIMER0_MR1 0x800880b0 558 #define HW_TIMER0_MR2 0x800880C0 559 #define HW_TIMER0_MR3 0x800880D0 560 #define HW_TIMER0_CCR 0x800880E0 561 #define HW_TIMER0_CR0 0x800880F0 562 #define HW_TIMER0_CR1 0x80088100 563 #define HW_TIMER0_CR2 0x80088110 564 #define HW_TIMER0_CR3 0x80088120 565 #define HW_TIMER0_EMR 0x80088130 566 #define HW_TIMER0_PWMTH0 0x80088140 567 #define HW_TIMER0_PWMTH1 0x80088150 568 #define HW_TIMER0_PWMTH2 0x80088160 569 #define HW_TIMER0_PWMTH3 0x80088170 570 #define HW_TIMER0_CTCR 0x80088180 571 #define HW_TIMER0_PWMC 0x80088190 572 573 //////////////////////////////////////////////////////////////////////////////// 574 // USART 575 576 typedef struct { 577 __IO unsigned long CTRL0[4]; 578 __IO unsigned long CTRL1[4]; 579 __IO unsigned long CTRL2[4]; 580 __IO unsigned long LINECTRL[4]; 581 __IO unsigned long INTR[4]; 582 __IO unsigned long DATA[4]; 583 __IO unsigned long STAT[4]; 584 __I unsigned long DEBUG[4]; 585 __IO unsigned long ILPR[4]; 586 __IO unsigned long RS485CTRL[4]; 587 __IO unsigned long RS485ADRMATCH[4]; 588 __IO unsigned long RS485DLY[4]; 589 __IO unsigned long AUTOBAUD[4]; 590 __IO unsigned long CTRL3[4]; 591 } ASM_USART_TypeDef; 592 593 #define UART0_BASE 0x80000000 594 #define UART1_BASE 0x80004000 595 #define UART2_BASE 0x80008000 596 #define UART3_BASE 0x8000C000 597 #define UART4_BASE 0x80010000 598 #define UART5_BASE 0x80014000 599 #define UART6_BASE 0x80018000 600 #define UART7_BASE 0x8001C000 601 #define UART8_BASE 0x80020000 602 #define UART9_BASE 0x80024000 603 604 //////////////////////////////////////////////////////////////////////////////// 605 // MAC 606 #define HW_ETH_BASE_ADDR 0x80500000 607 #define HW_ETH_MACCR (HW_ETH_BASE_ADDR + 0x0000) 608 #define HW_ETH_MACFFR (HW_ETH_BASE_ADDR + 0x0004) 609 #define HW_ETH_MACHTHR (HW_ETH_BASE_ADDR + 0x0008) 610 #define HW_ETH_MACHTLR (HW_ETH_BASE_ADDR + 0x000C) 611 #define HW_ETH_MACMIIAR (HW_ETH_BASE_ADDR + 0x0010) 612 #define HW_ETH_MACMIIDR (HW_ETH_BASE_ADDR + 0x0014) 613 #define HW_ETH_MACFCR (HW_ETH_BASE_ADDR + 0x0018) 614 #define HW_ETH_MACVLANTR (HW_ETH_BASE_ADDR + 0x001C) 615 #define HW_ETH_MACVR (HW_ETH_BASE_ADDR + 0x0020) 616 #define HW_ETH_MACRWUFFR (HW_ETH_BASE_ADDR + 0x0028) 617 #define HW_ETH_MACPMTCSR (HW_ETH_BASE_ADDR + 0x002C) 618 #define HW_ETH_MACDBGR (HW_ETH_BASE_ADDR + 0x0034) 619 #define HW_ETH_MACISR (HW_ETH_BASE_ADDR + 0x0038) 620 #define HW_ETH_MACIMR (HW_ETH_BASE_ADDR + 0x003C) 621 #define HW_ETH_MACA0HR (HW_ETH_BASE_ADDR + 0x0040) 622 #define HW_ETH_MACA0LR (HW_ETH_BASE_ADDR + 0x0044) 623 #define HW_ETH_MACA1HR (HW_ETH_BASE_ADDR + 0x0048) 624 #define HW_ETH_MACA1LR (HW_ETH_BASE_ADDR + 0x004C) 625 #define HW_ETH_MACA2HR (HW_ETH_BASE_ADDR + 0x0050) 626 #define HW_ETH_MACA2LR (HW_ETH_BASE_ADDR + 0x0054) 627 #define HW_ETH_MACA3HR (HW_ETH_BASE_ADDR + 0x0058) 628 #define HW_ETH_MACA3LR (HW_ETH_BASE_ADDR + 0x005C) 629 #define HW_ETH_MACA4HR (HW_ETH_BASE_ADDR + 0x0060) 630 #define HW_ETH_MACA4LR (HW_ETH_BASE_ADDR + 0x0064) 631 #define HW_ETH_MMCCR (HW_ETH_BASE_ADDR + 0x0100) 632 #define HW_ETH_MMCRIR (HW_ETH_BASE_ADDR + 0x0104) 633 #define HW_ETH_MMCTIR (HW_ETH_BASE_ADDR + 0x0108) 634 #define HW_ETH_MMCRIMR (HW_ETH_BASE_ADDR + 0x010C) 635 #define HW_ETH_MMCTIMR (HW_ETH_BASE_ADDR + 0x0110) 636 #define HW_ETH_MMCTGFSCCR (HW_ETH_BASE_ADDR + 0x014C) 637 #define HW_ETH_MMCTGFMSCCR (HW_ETH_BASE_ADDR + 0x0150) 638 #define HW_ETH_MMCTGFCR (HW_ETH_BASE_ADDR + 0x0168) 639 #define HW_ETH_MMCRFCECR (HW_ETH_BASE_ADDR + 0x0194) 640 #define HW_ETH_MMCRFAECR (HW_ETH_BASE_ADDR + 0x0198) 641 #define HW_ETH_MMCRGUFCR (HW_ETH_BASE_ADDR + 0x01C4) 642 #define HW_ETH_PTPTSCR (HW_ETH_BASE_ADDR + 0x0700) 643 #define HW_ETH_PTPSSIR (HW_ETH_BASE_ADDR + 0x0704) 644 #define HW_ETH_PTPTSHR (HW_ETH_BASE_ADDR + 0x0708) 645 #define HW_ETH_PTPTSLR (HW_ETH_BASE_ADDR + 0x070C) 646 #define HW_ETH_PTPTSHUR (HW_ETH_BASE_ADDR + 0x0710) 647 #define HW_ETH_PTPTSLUR (HW_ETH_BASE_ADDR + 0x0714) 648 #define HW_ETH_PTPTSAR (HW_ETH_BASE_ADDR + 0x0718) 649 #define HW_ETH_PTPTTHR (HW_ETH_BASE_ADDR + 0x071C) 650 #define HW_ETH_PTPTTLR (HW_ETH_BASE_ADDR + 0x0720) 651 #define HW_ETH_PTPTSSR (HW_ETH_BASE_ADDR + 0x0728) 652 #define HW_ETH_PTPPPSCR (HW_ETH_BASE_ADDR + 0x072C) 653 #define HW_ETH_DMABMR (HW_ETH_BASE_ADDR + 0x1000) 654 #define HW_ETH_DMATPDR (HW_ETH_BASE_ADDR + 0x1004) 655 #define HW_ETH_DMARPDR (HW_ETH_BASE_ADDR + 0x1008) 656 #define HW_ETH_DMARDLAR (HW_ETH_BASE_ADDR + 0x100C) 657 #define HW_ETH_DMATDLAR (HW_ETH_BASE_ADDR + 0x1010) 658 #define HW_ETH_DMASR (HW_ETH_BASE_ADDR + 0x1014) 659 #define HW_ETH_DMAOMR (HW_ETH_BASE_ADDR + 0x1018) 660 #define HW_ETH_DMAIER (HW_ETH_BASE_ADDR + 0x101C) 661 #define HW_ETH_DMAMFBOCR (HW_ETH_BASE_ADDR + 0x1020) 662 #define HW_ETH_DMARSWTR (HW_ETH_BASE_ADDR + 0x1024) 663 #define HW_ETH_DMACHTDR (HW_ETH_BASE_ADDR + 0x1048) 664 #define HW_ETH_DMACHRDR (HW_ETH_BASE_ADDR + 0x104C) 665 #define HW_ETH_DMACHTBAR (HW_ETH_BASE_ADDR + 0x1050) 666 #define HW_ETH_DMACHRBAR (HW_ETH_BASE_ADDR + 0x1054) 667 668 //////////////////////////////////////////////////////////////////////////////// 669 #endif /* __ASM9260T_REGS_H__ */ 670 671