1 /** 2 ********************************************************************************* 3 * 4 * @file ald_i2c.h 5 * @brief Header file of I2C driver 6 * 7 * @version V1.0 8 * @date 15 Nov 2019 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 30 Jun 2020 AE Team The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 #ifndef __ALD_I2C_H__ 34 #define __ALD_I2C_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include "utils.h" 41 #include "ald_dma.h" 42 #include "ald_cmu.h" 43 #include <string.h> 44 45 /** @addtogroup ES32FXXX_ALD 46 * @{ 47 */ 48 49 /** @addtogroup I2C 50 * @{ 51 */ 52 53 /** @defgroup I2C_Public_Types I2C Public Types 54 * @{ 55 */ 56 /** 57 * @brief I2C Error Code 58 */ 59 typedef enum { 60 I2C_ERROR_NONE = 0x0U, /**< No error */ 61 I2C_ERROR_BERR = 0x1U, /**< Berr error */ 62 I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ 63 I2C_ERROR_RUD = 0x4U, /**< Rx underflow error */ 64 I2C_ERROR_AF = 0x8U, /**< Af error */ 65 I2C_ERROR_ROV = 0x10U, /**< Rx overflow error */ 66 I2C_ERROR_RF = 0x20U, /**< Rx full error */ 67 I2C_ERROR_TUD = 0x40U, /**< Tx underflow error */ 68 I2C_ERROR_TOV = 0x80U, /**< Tx overflow error */ 69 I2C_ERROR_TE = 0x100U, /**< Tx empty error */ 70 I2C_ERROR_DMA = 0x200U, /**< Dma error */ 71 I2C_ERROR_TIMEOUT = 0x400U, /**< Timeout error */ 72 } i2c_error_t; 73 74 /** 75 * @brief I2C state structure definition 76 */ 77 typedef enum { 78 I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ 79 I2C_STATE_READY = 0x20U, /**< Peripheral Initialized and ready for use */ 80 I2C_STATE_BUSY = 0x24U, /**< An internal process is ongoing */ 81 I2C_STATE_BUSY_TX = 0x21U, /**< Data Transmission process is ongoing */ 82 I2C_STATE_BUSY_RX = 0x22U, /**< Data Reception process is ongoing */ 83 I2C_STATE_TIMEOUT = 0xA0U, /**< timeout state */ 84 I2C_STATE_ERROR = 0xE0U, /**< Error */ 85 } i2c_state_t; 86 87 /** 88 * @brief I2C Addressing Mode 89 */ 90 typedef enum { 91 I2C_ADDR_7BIT = 0x0U, /**< 7 bit address */ 92 I2C_ADDR_10BIT = 0x1U, /**< 10 bit address */ 93 } i2c_addr_t; 94 95 /** 96 * @brief I2C Dual Addressing Mode 97 */ 98 typedef enum { 99 I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ 100 I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ 101 } i2c_dual_addr_t; 102 103 /** 104 * @brief I2C General Call Addressing mode 105 */ 106 typedef enum { 107 I2C_GENERALCALL_DISABLE = 0x0U, /**< general call address is disable */ 108 I2C_GENERALCALL_ENABLE = 0x1U, /**< general call address is enable */ 109 } i2c_general_addr_t; 110 111 /** 112 * @brief I2C Nostretch Mode 113 */ 114 typedef enum { 115 I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ 116 I2C_NOSTRETCH_ENABLE = 0x1U, /**< Nostretch enable */ 117 } i2c_nostretch_t; 118 119 /** 120 * @brief I2C Memory Address Size 121 */ 122 typedef enum { 123 I2C_MEMADD_SIZE_8BIT = 0x8U, /**< 8 bit memory address size */ 124 I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ 125 } i2c_addr_size_t; 126 127 /** 128 * @brief I2C mode structure definition 129 */ 130 typedef enum { 131 I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ 132 I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ 133 I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ 134 I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ 135 } i2c_mode_t; 136 137 /** 138 * @brief I2C Clock 139 */ 140 typedef enum { 141 I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ 142 I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ 143 I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U, /**< Extreme mode clock */ 144 } i2c_clock_t; 145 146 /** 147 * @brief I2C OAR2 Register 148 */ 149 typedef enum { 150 I2C_OAR2_ENDUAL = (1U << 0), /**< ENDUAL BIT */ 151 I2C_OAR2_ADD2 = (1U << 1) /**< ADD2 BIT */ 152 } i2c_oar2_t; 153 154 /** 155 * @brief I2C CON1 Register 156 */ 157 typedef enum { 158 I2C_CON1_PE = (1U << 0), /**< Peripheral enable BIT */ 159 I2C_CON1_TXDMA = (1U << 14), /**< Transmit DMA BIT */ 160 I2C_CON1_RXDMA = (1U << 15), /**< Receive DMA BIT */ 161 I2C_CON1_SBC = (1U << 16), /**< Receive DMA BIT */ 162 I2C_CON1_NOSTRETCH = (1U << 17), /**< Slave bytes control BIT */ 163 I2C_CON1_GCEN = (1U << 19), /**< General call BIT */ 164 I2C_CON1_SMBHEN = (1U << 20), /**< SMBus slave device enable BIT */ 165 I2C_CON1_SMBDEN = (1U << 21), /**< SMBus master device enable BIT */ 166 I2C_CON1_ALERTEN = (1U << 22), /**< SMBus alert device enable BIT */ 167 I2C_CON1_PECEN = (1U << 23), /**< PEC enable BIT */ 168 } i2c_con1_t; 169 170 /** 171 * @brief I2C CON2 Register 172 */ 173 typedef enum { 174 I2C_CON2_RD_WRN = (1U << 10), /**< Master R/W control BIT */ 175 I2C_CON2_ADD10 = (1U << 11), /**< 10bit address control BIT */ 176 I2C_CON2_HEAD10R = (1U << 12), /**< 10bit address master Receive control BIT */ 177 I2C_CON2_START = (1U << 13), /**< Master start singal control BIT */ 178 I2C_CON2_STOP = (1U << 14), /**< Master stop singal control BIT */ 179 I2C_CON2_NACK = (1U << 15), /**< Master Nack control BIT */ 180 I2C_CON2_RELOAD = (1U << 24), /**< Master communication reload control BIT */ 181 I2C_CON2_AUTOEND = (1U << 25), /**< Master Autoend control BIT */ 182 I2C_CON2_PECBYTE = (1U << 26), /**< PEC control BIT */ 183 I2C_CON2_HOLDACK = (1U << 28), /**< Hold ack control BIT */ 184 } i2c_con2_t; 185 186 /** 187 * @brief I2C ADDR1 Register 188 */ 189 typedef enum { 190 I2C_OA1MODE = (1U << 10), /**< Addr1 bits choose BIT */ 191 I2C_OA1EN = (1U << 15), /**< Addr1 enable BIT */ 192 } i2c_addr1_t; 193 194 /** 195 * @brief I2C ADDR2 Register 196 */ 197 typedef enum { 198 I2C_OA2EN = (1U << 15), /**< Addr2 enable BIT */ 199 } i2c_addr2_t; 200 201 /** 202 * @brief I2C TIMEOUTR Register 203 */ 204 typedef enum { 205 I2C_TIMEOUTR_TIDLE = (1U << 12), /**< SCL idle check enable BIT */ 206 I2C_TIMEOUTR_TIMEOUTEN = (1U << 15), /**< Timeout enable BIT */ 207 } i2c_timoutr_t; 208 209 /** 210 * @brief I2C peripherals module 211 */ 212 typedef enum { 213 I2C_MODULE_MASTER = (1U << 0), /**< Master module */ 214 I2C_MODULE_SLAVE = (1U << 1) /**< Slave module */ 215 } i2c_module_t; 216 217 /** 218 * @brief I2C STAT Register 219 */ 220 typedef enum { 221 I2C_STAT_TXE = (1U << 0), /**< Transmit FIFO empty flag */ 222 I2C_STAT_TXF = (1U << 1), /**< Transmit FIFO full flag */ 223 I2C_STAT_TXOV = (1U << 2), /**< Transmit FIFO overrun flag */ 224 I2C_STAT_TXUD = (1U << 3), /**< Transmit FIFO underrun flag*/ 225 I2C_STAT_THTH = (1U << 4), /**< Transmit FIFO threshold flag */ 226 I2C_STAT_RXE = (1U << 5), /**< Receive FIFO empty flag*/ 227 I2C_STAT_RXF = (1U << 6), /**< Receive FIFO full flag*/ 228 I2C_STAT_RXOV = (1U << 7), /**< Receive FIFO overrun flag */ 229 I2C_STAT_RXUD = (1U << 8), /**< Receive FIFO underrun flag */ 230 I2C_STAT_RXTH = (1U << 9), /**< Receive FIFO threshold flag */ 231 I2C_STAT_TC = (1U << 10), /**< Transmit completed flag */ 232 I2C_STAT_TCR = (1U << 11), /**< Transmit and reload completed flag */ 233 I2C_STAT_BUSY = (1U << 15), /**< Bus status busy flag */ 234 I2C_STAT_DIR = (1U << 16), /**< Slave R/W flag */ 235 } i2c_stat_t; 236 237 /** 238 * @brief Interrupt Configuration Definition 239 */ 240 typedef enum { 241 I2C_IT_TXE = (1U << 0), /**< Transmit FIFO empty interrupt */ 242 I2C_IT_TXOV = (1U << 2), /**< Transmit FIFO overrun interrupt */ 243 I2C_IT_TXUD = (1U << 3), /**< Transmit FIFO underrun interrupt*/ 244 I2C_IT_TXTH = (1U << 4), /**< Transmit FIFO threshold interrupt */ 245 I2C_IT_RXF = (1U << 6), /**< Receive FIFO full interrupt*/ 246 I2C_IT_RXOV = (1U << 7), /**< Receive FIFO overrun interrupt */ 247 I2C_IT_RXUD = (1U << 8), /**< Receive FIFO underrun interrupt */ 248 I2C_IT_RXTH = (1U << 9), /**< Receive FIFO threshold interrupt */ 249 I2C_IT_TC = (1U << 10), /**< Transmit completed interrupt */ 250 I2C_IT_TCR = (1U << 11), /**< Transmit and reload completed interrupt */ 251 I2C_IT_ADDR = (1U << 12), /**< Address matching interrupt */ 252 I2C_IT_NACK = (1U << 13), /**< NACK interrupt */ 253 I2C_IT_STOP = (1U << 14), /**< Stop detection interrupt */ 254 I2C_IT_BERR = (1U << 16), /**< Bus error interrupt */ 255 I2C_IT_ARLO = (1U << 17), /**< Arbitration loss interrupt */ 256 I2C_IT_PECE = (1U << 18), /**< PEC error interrupt */ 257 I2C_IT_TOUT = (1U << 19), /**< Timeout interrupt */ 258 I2C_IT_ALERT = (1U << 20), /**< SMBus Alert interrupt */ 259 } i2c_interrupt_t; 260 261 /** 262 * @brief I2C TRISE Register 263 */ 264 typedef enum { 265 I2C_TRISE_TRISE = 0x3FU, /**< TRISE BITS */ 266 } i2c_trise_t; 267 268 /** 269 * @brief I2C Configuration Structure definition 270 */ 271 typedef struct { 272 i2c_module_t module; /**< Specifies the communication module */ 273 uint32_t clk_speed; /**< Specifies the clock frequency */ 274 uint32_t own_addr1; /**< Specifies the first device own address */ 275 i2c_addr_t addr_mode; /**< Specifies addressing mode */ 276 i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ 277 uint32_t own_addr2; /**< Specifies the second device own address */ 278 i2c_general_addr_t general_call;/**< Specifies if general call mode is selected */ 279 i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ 280 } i2c_init_t; 281 282 /** 283 * @brief I2C handle Structure definition 284 */ 285 typedef struct i2c_handle_s { 286 I2C_TypeDef *perh; /**< I2C registers base address */ 287 i2c_init_t init; /**< I2C communication parameters */ 288 uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ 289 uint16_t xfer_size; /**< I2C transfer size */ 290 __IO uint16_t xfer_count; /**< I2C transfer counter */ 291 292 dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ 293 dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ 294 295 lock_state_t lock; /**< I2C locking object */ 296 __IO i2c_state_t state; /**< I2C communication state */ 297 __IO i2c_mode_t mode; /**< I2C communication mode */ 298 __IO uint32_t error_code; /**< I2C Error code */ 299 300 void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ 301 void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ 302 void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ 303 void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ 304 void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ 305 void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ 306 void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ 307 } i2c_handle_t; 308 309 /** 310 * @} 311 */ 312 313 /** @defgroup I2C_Public_Macro I2C Public Macros 314 * @{ 315 */ 316 #define I2C_FLAG_MASK (0xFFFFFFFFU) 317 #define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) 318 #define I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y))) 319 #define I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y))) 320 #define I2C_CLEAR_IT(x, y) (SET_BIT((x)->perh->ICR, (y))) 321 #define I2C_GET_IT_FLAG(x, y) (READ_BIT((x)->perh->RIF, (y))) 322 #define I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET) 323 #define I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET) 324 #define I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK)) 325 #define I2C_SLAVE_GET_DIR(x) (READ_BIT(((x)->perh->STAT), I2C_STAT_DIR_MSK)) 326 #define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) 327 #define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) 328 #define I2C_RST_TXFIFO(x) (SET_BIT((x)->perh->FCON, I2C_FCON_TXFRST_MSK)) 329 #define I2C_RST_RXFIFO(x) (SET_BIT((x)->perh->FCON, I2C_FCON_RXFRST_MSK)) 330 /** 331 * @} 332 */ 333 334 /** @defgroup I2C_Private_Macro I2C Private Macros 335 * @{ 336 */ 337 #define IS_I2C_TYPE(x) (((x) == I2C0) || ((x) == I2C1)) 338 #define IS_I2C_MODULE(x) (((x) == I2C_MODULE_MASTER) || ((x) == I2C_MODULE_SLAVE)) 339 #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_7BIT) || \ 340 ((ADDRESS) == I2C_ADDR_10BIT)) 341 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDR_DISABLE) || \ 342 ((ADDRESS) == I2C_DUALADDR_ENABLE)) 343 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ 344 ((CALL) == I2C_GENERALCALL_ENABLE)) 345 #define IS_I2C_MEMADD_size(size) (((size) == I2C_MEMADD_SIZE_8BIT) || \ 346 ((size) == I2C_MEMADD_SIZE_16BIT)) 347 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ 348 ((STRETCH) == I2C_NOSTRETCH_ENABLE)) 349 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_EXTREME_FAST_MODE_MAX_CLK) ) 350 #define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__) / 1000000) 351 #define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) &\ 352 (uint16_t)(0xFF00))) >> 8))) 353 #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) 354 #define IS_I2C_IT(x) (((x) == I2C_IT_TXE) || \ 355 ((x) == I2C_IT_TXOV) || \ 356 ((x) == I2C_IT_TXUD) || \ 357 ((x) == I2C_IT_TXTH) || \ 358 ((x) == I2C_IT_RXF) || \ 359 ((x) == I2C_IT_RXOV) || \ 360 ((x) == I2C_IT_RXUD) || \ 361 ((x) == I2C_IT_RXTH) || \ 362 ((x) == I2C_IT_TC) || \ 363 ((x) == I2C_IT_TCR) || \ 364 ((x) == I2C_IT_ADDR) || \ 365 ((x) == I2C_IT_NACK) || \ 366 ((x) == I2C_IT_STOP) || \ 367 ((x) == I2C_IT_BERR) || \ 368 ((x) == I2C_IT_ARLO) || \ 369 ((x) == I2C_IT_PECE) || \ 370 ((x) == I2C_IT_TOUT) || \ 371 ((x) == I2C_IT_ALERT)) 372 /** 373 * @} 374 */ 375 376 /** @addtogroup I2C_Public_Functions 377 * @{ 378 */ 379 380 /** @addtogroup I2C_Public_Functions_Group1 Initialization and de-initialization functions 381 * @{ 382 */ 383 ald_status_t ald_i2c_init(i2c_handle_t *hperh); 384 ald_status_t ald_i2c_reset(i2c_handle_t *hperh); 385 386 /** 387 * @} 388 */ 389 390 /** @addtogroup I2C_Public_Functions_Group2 Input and Output operation functions 391 * @{ 392 */ 393 /** Blocking mode: Polling */ 394 ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, 395 uint8_t *buf, uint32_t size, uint32_t timeout); 396 ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, 397 uint8_t *buf, uint32_t size, uint32_t timeout); 398 ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); 399 ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); 400 ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 401 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); 402 ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 403 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); 404 405 /** Non-Blocking mode: Interrupt */ 406 ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); 407 ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); 408 ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size); 409 ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size); 410 ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 411 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); 412 ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 413 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); 414 415 416 /** Non-Blocking mode: DMA */ 417 ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, 418 uint8_t *buf, uint8_t size, uint8_t channel); 419 ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, 420 uint8_t *buf, uint8_t size, uint8_t channel); 421 ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel); 422 ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel); 423 ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, 424 uint8_t *buf, uint8_t size, uint8_t channel); 425 ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 426 i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel); 427 428 /** 429 * @} 430 */ 431 432 /** @addtogroup I2C_Public_Functions_Group3 Peripheral state and Errors functions 433 * @{ 434 */ 435 i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh); 436 uint32_t ald_i2c_get_error(i2c_handle_t *hperh); 437 void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag); 438 flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag); 439 flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag); 440 it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); 441 /** 442 * @} 443 */ 444 445 /** @addtogroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks 446 * @{ 447 */ 448 void ald_i2c_ev_irq_handler(i2c_handle_t *hperh); 449 void ald_i2c_er_irq_handler(i2c_handle_t *hperh); 450 void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); 451 /** 452 * @} 453 */ 454 455 /** 456 * @} 457 */ 458 459 /** 460 * @} 461 */ 462 463 /** 464 * @} 465 */ 466 #ifdef __cplusplus 467 } 468 #endif 469 470 #endif /* __ALD_I2C_H__ */ 471