1 /* 2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /****************************************************************************** 18 * @file dw_iic.h 19 * @brief header File for IIC Driver 20 * @version V1.0 21 * @date 02. June 2017 22 ******************************************************************************/ 23 #ifndef __DW_IIC_H 24 #define __DW_IIC_H 25 #include "soc.h" 26 27 /* 28 * Define the speed of I2C 29 */ 30 typedef enum { 31 DW_IIC_STANDARDSPEED = 1, 32 DW_IIC_FASTSPEED = 2, 33 DW_IIC_HIGHSPEED = 3 34 } DWENUM_IIC_SPEED; 35 36 enum i2c_state_e { 37 IIC_STATE_NONE = 0, /* Send start + (first part of) address. */ 38 IIC_STATE_DATASEND, /* Send data. */ 39 IIC_STATE_WFDATA, /* Wait for data. */ 40 IIC_STATE_WFSTOPSENT, /* Wait for STOP to have been transmitted. */ 41 IIC_STATE_DONE, /* Transfer completed successfully. */ 42 IIC_STATE_ERROR /* Transfer error. */ 43 }; 44 /* 45 * Define the interrupt type of I2C 46 */ 47 typedef enum { 48 DW_IIC_RX_UNDER = 0, 49 DW_IIC_RX_OVER = 1, 50 DW_IIC_RX_FULL = 2, 51 DW_IIC_TX_OVER = 3, 52 DW_IIC_TX_EMPTY = 4, 53 DW_IIC_RD_REQ = 5, 54 DW_IIC_TX_ABRT = 6, 55 DW_IIC_RX_DONE = 7, 56 DW_IIC_ACTIVITY = 8, 57 DW_IIC_STOP_DET = 9, 58 DW_IIC_START_DET = 10, 59 DW_IIC_GEN_CALL = 11 60 } DWENUM_IIC_INTERRUPT_TYPE; 61 62 /* 63 * I2C register bit definitions 64 */ 65 #define DW_IIC_DISABLE 0 66 #define DW_IIC_ENABLE 1 67 #define DW_IIC_FIFO_MAX_LV 0x8 68 #define DW_IIC_TXFIFO_LV 0x2 69 #define DW_IIC_RXFIFO_LV 0x0 70 71 #define DW_IIC_RXFIFO_FULL (0x1 << 4) 72 #define DW_IIC_RXFIFO_NOT_EMPTY (0x1 << 3) 73 #define DW_IIC_TXFIFO_EMPTY (0x1 << 2) 74 #define DW_IIC_TXFIFO_NOT_FULL (0x1 << 1) 75 #define DW_IIC_STATUS_ACTIVITY 0x1 76 77 #define DW_IIC_CON_DEFAUL 0x23 78 79 typedef struct { 80 __IOM uint32_t IC_CON; /* Offset: 0x000 (R/W) Receive buffer register */ 81 __IOM uint32_t IC_TAR; /* Offset: 0x004 (R/W) Transmission hold register */ 82 __IOM uint32_t IC_SAR; /* Offset: 0x008 (R/W) Clock frequency division low section register */ 83 __IOM uint32_t IC_HS_MADDR; /* Offset: 0x00c (R/W) Clock frequency division high section register */ 84 __IOM uint32_t IC_DATA_CMD; /* Offset: 0x010 (R/W) Interrupt enable register */ 85 __IOM uint32_t IC_SS_SCL_HCNT; /* Offset: 0x014 (R/W) Interrupt indicia register */ 86 __IOM uint32_t IC_SS_SCL_LCNT; /* Offset: 0x018 (R/W) Transmission control register */ 87 __IOM uint32_t IC_FS_SCL_HCNT; /* Offset: 0x01c (R/W) Modem control register */ 88 __IOM uint32_t IC_FS_SCL_LCNT; /* Offset: 0x020 (R/W) Transmission state register */ 89 __IOM uint32_t IC_HS_SCL_HCNT; /* Offset: 0x024 (R/W) Transmission state register */ 90 __IOM uint32_t IC_HS_SCL_LCNT; /* Offset: 0x028 (R/W) Transmission state register */ 91 __IOM uint32_t IC_INTR_STAT; /* Offset: 0x02c (R) Transmission state register */ 92 __IOM uint32_t IC_INTR_MASK; /* Offset: 0x030 (R/W) Transmission state register */ 93 __IOM uint32_t IC_RAW_INTR_STAT; /* Offset: 0x034 (R) Transmission state register */ 94 __IOM uint32_t IC_RX_TL; /* Offset: 0x038 (R/W) Transmission state register */ 95 __IOM uint32_t IC_TX_TL; /* Offset: 0x03c (R/W) Transmission state register */ 96 __IOM uint32_t IC_CLR_INTR; /* Offset: 0x040 (R) Transmission state register */ 97 __IOM uint32_t IC_CLR_RX_UNDER; /* Offset: 0x044 (R) Transmission state register */ 98 __IOM uint32_t IC_CLR_RX_OVER; /* Offset: 0x048 (R) Transmission state register */ 99 __IOM uint32_t IC_CLR_TX_OVER; /* Offset: 0x04c (R) Transmission state register */ 100 __IOM uint32_t IC_CLR_RD_REQ; /* Offset: 0x050 (R) Transmission state register */ 101 __IOM uint32_t IC_CLR_TX_ABRT; /* Offset: 0x054 (R) Transmission state register */ 102 __IOM uint32_t IC_CLR_RX_DONE; /* Offset: 0x058 (R) Transmission state register */ 103 __IOM uint32_t IC_CLR_ACTIVITY; /* Offset: 0x05c (R) Transmission state register */ 104 __IOM uint32_t IC_CLR_STOP_DET; /* Offset: 0x060 (R) Transmission state register */ 105 __IOM uint32_t IC_CLR_START_DET; /* Offset: 0x064 (R) Transmission state register */ 106 __IOM uint32_t IC_CLR_GEN_CALL; /* Offset: 0x068 (R) Transmission state register */ 107 __IOM uint32_t IC_ENABLE; /* Offset: 0x06c (R/W) Transmission state register */ 108 __IOM uint32_t IC_STATUS; /* Offset: 0x070 (R) Transmission state register */ 109 __IOM uint32_t IC_TXFLR; /* Offset: 0x074 (R) Transmission state register */ 110 __IOM uint32_t IC_RXFLR; /* Offset: 0x078 (R) Transmission state register */ 111 uint32_t RESERVED; /* Offset: 0x014 (R/ ) Transmission state register */ 112 __IOM uint32_t IC_TX_ABRT_SOURCE; /* Offset: 0x080 (R/W) Transmission state register */ 113 __IOM uint32_t IC_SAR1; /* Offset: 0x084 (R/W) Transmission state register */ 114 __IOM uint32_t IC_DMA_CR; /* Offset: 0x088 (R/W) Transmission state register */ 115 __IOM uint32_t IC_DMA_TDLR; /* Offset: 0x08c (R/W) Transmission state register */ 116 __IOM uint32_t IC_DMA_RDLR; /* Offset: 0x090 (R/W) Transmission state register */ 117 __IOM uint32_t IC_SAR2; /* Offset: 0x094 (R/W) Transmission state register */ 118 __IOM uint32_t IC_SAR3; /* Offset: 0x098 (R/W) Transmission state register */ 119 __IOM uint32_t IC_MULTI_SLAVE; /* Offset: 0x09c (R/W) Transmission state register */ 120 __IOM uint32_t IC_GEN_CALL_EN; /* Offset: 0x0a0 (R/W) Transmission state register */ 121 } dw_iic_reg_t; 122 123 #endif /* __DW_IIC_H */ 124