1 /** 2 ****************************************************************************** 3 * @file mfxstm32l152.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the 6 * mfxstm32l152.c IO expander driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 37 /* Define to prevent recursive inclusion -------------------------------------*/ 38 #ifndef __MFXSTM32L152_H 39 #define __MFXSTM32L152_H 40 41 #include "board.h" 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 /** @addtogroup BSP 48 * @{ 49 */ 50 51 /** @addtogroup Component 52 * @{ 53 */ 54 55 /** @defgroup MFXSTM32L152 56 * @{ 57 */ 58 59 /** 60 * @brief GPIO: IO Pins definition 61 */ 62 #define MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001) 63 #define MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002) 64 #define MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004) 65 #define MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008) 66 #define MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010) 67 #define MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020) 68 #define MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040) 69 #define MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080) 70 71 #define MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100) 72 #define MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200) 73 #define MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400) 74 #define MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800) 75 #define MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000) 76 #define MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000) 77 #define MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000) 78 #define MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000) 79 80 #define MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000) 81 #define MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000) 82 #define MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000) 83 #define MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000) 84 #define MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000) 85 #define MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000) 86 #define MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000) 87 #define MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000) 88 89 #define MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16 90 #define MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17 91 #define MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18 92 #define MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19 93 #define MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20 94 #define MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21 95 #define MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22 96 #define MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23 97 98 #define MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF) 99 #define IO_PIN_ALL MFXSTM32L152_GPIO_PINS_ALL 100 /** 101 * @brief IO Bit SET and Bit RESET enumeration 102 */ 103 typedef enum 104 { 105 IO_PIN_RESET = 0, 106 IO_PIN_SET 107 }IO_PinState; 108 109 typedef enum 110 { 111 IO_MODE_INPUT = 0, /* input floating */ 112 IO_MODE_OUTPUT, /* output Push Pull */ 113 IO_MODE_IT_RISING_EDGE, /* float input - irq detect on rising edge */ 114 IO_MODE_IT_FALLING_EDGE, /* float input - irq detect on falling edge */ 115 IO_MODE_IT_LOW_LEVEL, /* float input - irq detect on low level */ 116 IO_MODE_IT_HIGH_LEVEL, /* float input - irq detect on high level */ 117 /* following modes only available on MFX*/ 118 IO_MODE_ANALOG, /* analog mode */ 119 IO_MODE_OFF, /* when pin isn't used*/ 120 IO_MODE_INPUT_PU, /* input with internal pull up resistor */ 121 IO_MODE_INPUT_PD, /* input with internal pull down resistor */ 122 IO_MODE_OUTPUT_OD, /* Open Drain output without internal resistor */ 123 IO_MODE_OUTPUT_OD_PU, /* Open Drain output with internal pullup resistor */ 124 IO_MODE_OUTPUT_OD_PD, /* Open Drain output with internal pulldown resistor */ 125 IO_MODE_OUTPUT_PP, /* PushPull output without internal resistor */ 126 IO_MODE_OUTPUT_PP_PU, /* PushPull output with internal pullup resistor */ 127 IO_MODE_OUTPUT_PP_PD, /* PushPull output with internal pulldown resistor */ 128 IO_MODE_IT_RISING_EDGE_PU, /* push up resistor input - irq on rising edge */ 129 IO_MODE_IT_RISING_EDGE_PD, /* push dw resistor input - irq on rising edge */ 130 IO_MODE_IT_FALLING_EDGE_PU, /* push up resistor input - irq on falling edge */ 131 IO_MODE_IT_FALLING_EDGE_PD, /* push dw resistor input - irq on falling edge */ 132 IO_MODE_IT_LOW_LEVEL_PU, /* push up resistor input - irq detect on low level */ 133 IO_MODE_IT_LOW_LEVEL_PD, /* push dw resistor input - irq detect on low level */ 134 IO_MODE_IT_HIGH_LEVEL_PU, /* push up resistor input - irq detect on high level */ 135 IO_MODE_IT_HIGH_LEVEL_PD, /* push dw resistor input - irq detect on high level */ 136 137 }IO_ModeTypedef; 138 139 /** @defgroup IO_Driver_structure IO Driver structure 140 * @{ 141 */ 142 typedef struct 143 { 144 void (*Init)(uint16_t); 145 uint16_t (*ReadID)(uint16_t); 146 void (*Reset)(uint16_t); 147 148 void (*Start)(uint16_t, uint32_t); 149 uint8_t (*Config)(uint16_t, uint32_t, IO_ModeTypedef); 150 void (*WritePin)(uint16_t, uint32_t, uint8_t); 151 uint32_t (*ReadPin)(uint16_t, uint32_t); 152 153 void (*EnableIT)(uint16_t); 154 void (*DisableIT)(uint16_t); 155 uint32_t (*ITStatus)(uint16_t, uint32_t); 156 void (*ClearIT)(uint16_t, uint32_t); 157 158 }IO_DrvTypeDef; 159 160 typedef struct 161 { 162 uint16_t AmpliGain; /*!< Specifies ampli gain value 163 */ 164 uint16_t VddMin; /*!< Specifies minimum MCU VDD can reach to protect MCU from reset 165 */ 166 uint16_t Shunt0Value; /*!< Specifies value of Shunt 0 if existing 167 */ 168 uint16_t Shunt1Value; /*!< Specifies value of Shunt 1 if existing 169 */ 170 uint16_t Shunt2Value; /*!< Specifies value of Shunt 2 if existing 171 */ 172 uint16_t Shunt3Value; /*!< Specifies value of Shunt 3 if existing 173 */ 174 uint16_t Shunt4Value; /*!< Specifies value of Shunt 4 if existing 175 */ 176 uint16_t Shunt0StabDelay; /*!< Specifies delay of Shunt 0 stabilization if existing 177 */ 178 uint16_t Shunt1StabDelay; /*!< Specifies delay of Shunt 1 stabilization if existing 179 */ 180 uint16_t Shunt2StabDelay; /*!< Specifies delay of Shunt 2 stabilization if existing 181 */ 182 uint16_t Shunt3StabDelay; /*!< Specifies delay of Shunt 3 stabilization if existing 183 */ 184 uint16_t Shunt4StabDelay; /*!< Specifies delay of Shunt 4 stabilization if existing 185 */ 186 uint8_t ShuntNbOnBoard; /*!< Specifies number of shunts that are present on board 187 This parameter can be a value of @ref IDD_shunt_number */ 188 uint8_t ShuntNbUsed; /*!< Specifies number of shunts used for measurement 189 This parameter can be a value of @ref IDD_shunt_number */ 190 uint8_t VrefMeasurement; /*!< Specifies if Vref is automatically measured before each Idd measurement 191 This parameter can be a value of @ref IDD_Vref_Measurement */ 192 uint8_t Calibration; /*!< Specifies if calibration is done before each Idd measurement 193 */ 194 uint8_t PreDelayUnit; /*!< Specifies Pre delay unit 195 This parameter can be a value of @ref IDD_PreDelay */ 196 uint8_t PreDelayValue; /*!< Specifies Pre delay value in selected unit 197 */ 198 uint8_t MeasureNb; /*!< Specifies number of Measure to be performed 199 This parameter can be a value between 1 and 256 */ 200 uint8_t DeltaDelayUnit; /*!< Specifies Delta delay unit 201 This parameter can be a value of @ref IDD_DeltaDelay */ 202 uint8_t DeltaDelayValue; /*!< Specifies Delta delay between 2 measures 203 value can be between 1 and 128 */ 204 }IDD_ConfigTypeDef; 205 /** 206 * @} 207 */ 208 209 /** @defgroup IDD_Driver_structure IDD Driver structure 210 * @{ 211 */ 212 typedef struct 213 { 214 void (*Init)(uint16_t); 215 void (*DeInit)(uint16_t); 216 uint16_t (*ReadID)(uint16_t); 217 void (*Reset)(uint16_t); 218 void (*LowPower)(uint16_t); 219 void (*WakeUp)(uint16_t); 220 void (*Start)(uint16_t); 221 void (*Config)(uint16_t,IDD_ConfigTypeDef); 222 void (*GetValue)(uint16_t, uint32_t *); 223 void (*EnableIT)(uint16_t); 224 void (*ClearIT)(uint16_t); 225 uint8_t (*GetITStatus)(uint16_t); 226 void (*DisableIT)(uint16_t); 227 void (*ErrorEnableIT)(uint16_t); 228 void (*ErrorClearIT)(uint16_t); 229 uint8_t (*ErrorGetITStatus)(uint16_t); 230 void (*ErrorDisableIT)(uint16_t); 231 uint8_t (*ErrorGetSrc)(uint16_t); 232 uint8_t (*ErrorGetCode)(uint16_t); 233 }IDD_DrvTypeDef; 234 235 typedef struct 236 { 237 void (*Init)(uint16_t); 238 uint16_t (*ReadID)(uint16_t); 239 void (*Reset)(uint16_t); 240 void (*Start)(uint16_t); 241 uint8_t (*DetectTouch)(uint16_t); 242 void (*GetXY)(uint16_t, uint16_t*, uint16_t*); 243 void (*EnableIT)(uint16_t); 244 void (*ClearIT)(uint16_t); 245 uint8_t (*GetITStatus)(uint16_t); 246 void (*DisableIT)(uint16_t); 247 }TS_DrvTypeDef; 248 249 /* Exported types ------------------------------------------------------------*/ 250 251 /** @defgroup MFXSTM32L152_Exported_Types 252 * @{ 253 */ 254 typedef struct 255 { 256 uint8_t SYS_CTRL; 257 uint8_t ERROR_SRC; 258 uint8_t ERROR_MSG; 259 uint8_t IRQ_OUT; 260 uint8_t IRQ_SRC_EN; 261 uint8_t IRQ_PENDING; 262 uint8_t IDD_CTRL; 263 uint8_t IDD_PRE_DELAY; 264 uint8_t IDD_SHUNT0_MSB; 265 uint8_t IDD_SHUNT0_LSB; 266 uint8_t IDD_SHUNT1_MSB; 267 uint8_t IDD_SHUNT1_LSB; 268 uint8_t IDD_SHUNT2_MSB; 269 uint8_t IDD_SHUNT2_LSB; 270 uint8_t IDD_SHUNT3_MSB; 271 uint8_t IDD_SHUNT3_LSB; 272 uint8_t IDD_SHUNT4_MSB; 273 uint8_t IDD_SHUNT4_LSB; 274 uint8_t IDD_GAIN_MSB; 275 uint8_t IDD_GAIN_LSB; 276 uint8_t IDD_VDD_MIN_MSB; 277 uint8_t IDD_VDD_MIN_LSB; 278 uint8_t IDD_VALUE_MSB; 279 uint8_t IDD_VALUE_MID; 280 uint8_t IDD_VALUE_LSB; 281 uint8_t IDD_CAL_OFFSET_MSB; 282 uint8_t IDD_CAL_OFFSET_LSB; 283 uint8_t IDD_SHUNT_USED; 284 }IDD_dbgTypeDef; 285 286 /** 287 * @} 288 */ 289 290 /* Exported constants --------------------------------------------------------*/ 291 292 /** @defgroup MFXSTM32L152_Exported_Constants 293 * @{ 294 */ 295 296 /** 297 * @brief MFX COMMON defines 298 */ 299 300 /** 301 * @brief Register address: chip IDs (R) 302 */ 303 #define MFXSTM32L152_REG_ADR_ID ((uint8_t)0x00) 304 /** 305 * @brief Register address: chip FW_VERSION (R) 306 */ 307 #define MFXSTM32L152_REG_ADR_FW_VERSION_MSB ((uint8_t)0x01) 308 #define MFXSTM32L152_REG_ADR_FW_VERSION_LSB ((uint8_t)0x00) 309 /** 310 * @brief Register address: System Control Register (R/W) 311 */ 312 #define MFXSTM32L152_REG_ADR_SYS_CTRL ((uint8_t)0x40) 313 /** 314 * @brief Register address: Vdd monitoring (R) 315 */ 316 #define MFXSTM32L152_REG_ADR_VDD_REF_MSB ((uint8_t)0x06) 317 #define MFXSTM32L152_REG_ADR_VDD_REF_LSB ((uint8_t)0x07) 318 /** 319 * @brief Register address: Error source 320 */ 321 #define MFXSTM32L152_REG_ADR_ERROR_SRC ((uint8_t)0x03) 322 /** 323 * @brief Register address: Error Message 324 */ 325 #define MFXSTM32L152_REG_ADR_ERROR_MSG ((uint8_t)0x04) 326 327 /** 328 * @brief Reg Addr IRQs: to config the pin that informs Main MCU that MFX events appear 329 */ 330 #define MFXSTM32L152_REG_ADR_MFX_IRQ_OUT ((uint8_t)0x41) 331 /** 332 * @brief Reg Addr IRQs: to select the events which activate the MFXSTM32L152_IRQ_OUT signal 333 */ 334 #define MFXSTM32L152_REG_ADR_IRQ_SRC_EN ((uint8_t)0x42) 335 /** 336 * @brief Reg Addr IRQs: the Main MCU must read the IRQ_PENDING register to know the interrupt reason 337 */ 338 #define MFXSTM32L152_REG_ADR_IRQ_PENDING ((uint8_t)0x08) 339 /** 340 * @brief Reg Addr IRQs: the Main MCU must acknowledge it thanks to a writing access to the IRQ_ACK register 341 */ 342 #define MFXSTM32L152_REG_ADR_IRQ_ACK ((uint8_t)0x44) 343 344 /** 345 * @brief MFXSTM32L152_REG_ADR_ID choices 346 */ 347 #define MFXSTM32L152_ID_1 ((uint8_t)0x7B) 348 #define MFXSTM32L152_ID_2 ((uint8_t)0x79) 349 350 /** 351 * @brief MFXSTM32L152_REG_ADR_SYS_CTRL choices 352 */ 353 #define MFXSTM32L152_SWRST ((uint8_t)0x80) 354 #define MFXSTM32L152_STANDBY ((uint8_t)0x40) 355 #define MFXSTM32L152_ALTERNATE_GPIO_EN ((uint8_t)0x08) /* by the way if IDD and TS are enabled they take automatically the AF pins*/ 356 #define MFXSTM32L152_IDD_EN ((uint8_t)0x04) 357 #define MFXSTM32L152_TS_EN ((uint8_t)0x02) 358 #define MFXSTM32L152_GPIO_EN ((uint8_t)0x01) 359 360 /** 361 * @brief MFXSTM32L152_REG_ADR_ERROR_SRC choices 362 */ 363 #define MFXSTM32L152_IDD_ERROR_SRC ((uint8_t)0x04) /* Error raised by Idd */ 364 #define MFXSTM32L152_TS_ERROR_SRC ((uint8_t)0x02) /* Error raised by Touch Screen */ 365 #define MFXSTM32L152_GPIO_ERROR_SRC ((uint8_t)0x01) /* Error raised by Gpio */ 366 367 /** 368 * @brief MFXSTM32L152_REG_ADR_MFX_IRQ_OUT choices 369 */ 370 #define MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN ((uint8_t)0x00) 371 #define MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL ((uint8_t)0x01) 372 #define MFXSTM32L152_OUT_PIN_POLARITY_LOW ((uint8_t)0x00) 373 #define MFXSTM32L152_OUT_PIN_POLARITY_HIGH ((uint8_t)0x02) 374 375 /** 376 * @brief REG_ADR_IRQ_SRC_EN, REG_ADR_IRQ_PENDING & REG_ADR_IRQ_ACK choices 377 */ 378 #define MFXSTM32L152_IRQ_TS_OVF ((uint8_t)0x80) /* TouchScreen FIFO Overflow irq*/ 379 #define MFXSTM32L152_IRQ_TS_FULL ((uint8_t)0x40) /* TouchScreen FIFO Full irq*/ 380 #define MFXSTM32L152_IRQ_TS_TH ((uint8_t)0x20) /* TouchScreen FIFO threshold triggered irq*/ 381 #define MFXSTM32L152_IRQ_TS_NE ((uint8_t)0x10) /* TouchScreen FIFO Not Empty irq*/ 382 #define MFXSTM32L152_IRQ_TS_DET ((uint8_t)0x08) /* TouchScreen Detect irq*/ 383 #define MFXSTM32L152_IRQ_ERROR ((uint8_t)0x04) /* Error message from MFXSTM32L152 firmware irq */ 384 #define MFXSTM32L152_IRQ_IDD ((uint8_t)0x02) /* IDD function irq */ 385 #define MFXSTM32L152_IRQ_GPIO ((uint8_t)0x01) /* General GPIO irq (only for SRC_EN and PENDING) */ 386 #define MFXSTM32L152_IRQ_ALL ((uint8_t)0xFF) /* All global interrupts */ 387 #define MFXSTM32L152_IRQ_TS (MFXSTM32L152_IRQ_TS_DET | MFXSTM32L152_IRQ_TS_NE | MFXSTM32L152_IRQ_TS_TH | MFXSTM32L152_IRQ_TS_FULL | MFXSTM32L152_IRQ_TS_OVF ) 388 389 390 /** 391 * @brief GPIO: 24 programmable input/output called MFXSTM32L152_GPIO[23:0] are provided 392 */ 393 394 /** 395 * @brief Reg addr: GPIO DIRECTION (R/W): GPIO pins direction: (0) input, (1) output. 396 */ 397 #define MFXSTM32L152_REG_ADR_GPIO_DIR1 ((uint8_t)0x60) /* gpio [0:7] */ 398 #define MFXSTM32L152_REG_ADR_GPIO_DIR2 ((uint8_t)0x61) /* gpio [8:15] */ 399 #define MFXSTM32L152_REG_ADR_GPIO_DIR3 ((uint8_t)0x62) /* agpio [0:7] */ 400 /** 401 * @brief Reg addr: GPIO TYPE (R/W): If GPIO in output: (0) output push pull, (1) output open drain. 402 * If GPIO in input: (0) input without pull resistor, (1) input with pull resistor. 403 */ 404 #define MFXSTM32L152_REG_ADR_GPIO_TYPE1 ((uint8_t)0x64) /* gpio [0:7] */ 405 #define MFXSTM32L152_REG_ADR_GPIO_TYPE2 ((uint8_t)0x65) /* gpio [8:15] */ 406 #define MFXSTM32L152_REG_ADR_GPIO_TYPE3 ((uint8_t)0x66) /* agpio [0:7] */ 407 /** 408 * @brief Reg addr: GPIO PULL_UP_PULL_DOWN (R/W): discussion open with Jean Claude 409 */ 410 #define MFXSTM32L152_REG_ADR_GPIO_PUPD1 ((uint8_t)0x68) /* gpio [0:7] */ 411 #define MFXSTM32L152_REG_ADR_GPIO_PUPD2 ((uint8_t)0x69) /* gpio [8:15] */ 412 #define MFXSTM32L152_REG_ADR_GPIO_PUPD3 ((uint8_t)0x6A) /* agpio [0:7] */ 413 /** 414 * @brief Reg addr: GPIO SET (W): When GPIO is in output mode, write (1) puts the corresponding GPO in High level. 415 */ 416 #define MFXSTM32L152_REG_ADR_GPO_SET1 ((uint8_t)0x6C) /* gpio [0:7] */ 417 #define MFXSTM32L152_REG_ADR_GPO_SET2 ((uint8_t)0x6D) /* gpio [8:15] */ 418 #define MFXSTM32L152_REG_ADR_GPO_SET3 ((uint8_t)0x6E) /* agpio [0:7] */ 419 /** 420 * @brief Reg addr: GPIO CLEAR (W): When GPIO is in output mode, write (1) puts the corresponding GPO in Low level. 421 */ 422 #define MFXSTM32L152_REG_ADR_GPO_CLR1 ((uint8_t)0x70) /* gpio [0:7] */ 423 #define MFXSTM32L152_REG_ADR_GPO_CLR2 ((uint8_t)0x71) /* gpio [8:15] */ 424 #define MFXSTM32L152_REG_ADR_GPO_CLR3 ((uint8_t)0x72) /* agpio [0:7] */ 425 /** 426 * @brief Reg addr: GPIO STATE (R): Give state of the GPIO pin. 427 */ 428 #define MFXSTM32L152_REG_ADR_GPIO_STATE1 ((uint8_t)0x10) /* gpio [0:7] */ 429 #define MFXSTM32L152_REG_ADR_GPIO_STATE2 ((uint8_t)0x11) /* gpio [8:15] */ 430 #define MFXSTM32L152_REG_ADR_GPIO_STATE3 ((uint8_t)0x12) /* agpio [0:7] */ 431 432 /** 433 * @brief GPIO IRQ_GPIs 434 */ 435 /* GPIOs can INDIVIDUALLY generate interruption to the Main MCU thanks to the MFXSTM32L152_IRQ_OUT signal */ 436 /* the general MFXSTM32L152_IRQ_GPIO_SRC_EN shall be enabled too */ 437 /** 438 * @brief GPIO IRQ_GPI_SRC1/2/3 (R/W): registers enable or not the feature to generate irq 439 */ 440 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1 ((uint8_t)0x48) /* gpio [0:7] */ 441 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC2 ((uint8_t)0x49) /* gpio [8:15] */ 442 #define MFXSTM32L152_REG_ADR_IRQ_GPI_SRC3 ((uint8_t)0x4A) /* agpio [0:7] */ 443 /** 444 * @brief GPIO IRQ_GPI_EVT1/2/3 (R/W): Irq generated on level (0) or edge (1). 445 */ 446 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1 ((uint8_t)0x4C) /* gpio [0:7] */ 447 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT2 ((uint8_t)0x4D) /* gpio [8:15] */ 448 #define MFXSTM32L152_REG_ADR_IRQ_GPI_EVT3 ((uint8_t)0x4E) /* agpio [0:7] */ 449 /** 450 * @brief GPIO IRQ_GPI_TYPE1/2/3 (R/W): Irq generated on (0) : Low level or Falling edge. (1) : High level or Rising edge. 451 */ 452 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1 ((uint8_t)0x50) /* gpio [0:7] */ 453 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE2 ((uint8_t)0x51) /* gpio [8:15] */ 454 #define MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE3 ((uint8_t)0x52) /* agpio [0:7] */ 455 /** 456 * @brief GPIO IRQ_GPI_PENDING1/2/3 (R): irq occurs 457 */ 458 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1 ((uint8_t)0x0C) /* gpio [0:7] */ 459 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2 ((uint8_t)0x0D) /* gpio [8:15] */ 460 #define MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3 ((uint8_t)0x0E) /* agpio [0:7] */ 461 /** 462 * @brief GPIO IRQ_GPI_ACK1/2/3 (W): Write (1) to acknowledge IRQ event 463 */ 464 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1 ((uint8_t)0x54) /* gpio [0:7] */ 465 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2 ((uint8_t)0x55) /* gpio [8:15] */ 466 #define MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3 ((uint8_t)0x56) /* agpio [0:7] */ 467 468 469 /** 470 * @brief GPIO: IO Pins definition 471 */ 472 #define MFXSTM32L152_GPIO_PIN_0 ((uint32_t)0x0001) 473 #define MFXSTM32L152_GPIO_PIN_1 ((uint32_t)0x0002) 474 #define MFXSTM32L152_GPIO_PIN_2 ((uint32_t)0x0004) 475 #define MFXSTM32L152_GPIO_PIN_3 ((uint32_t)0x0008) 476 #define MFXSTM32L152_GPIO_PIN_4 ((uint32_t)0x0010) 477 #define MFXSTM32L152_GPIO_PIN_5 ((uint32_t)0x0020) 478 #define MFXSTM32L152_GPIO_PIN_6 ((uint32_t)0x0040) 479 #define MFXSTM32L152_GPIO_PIN_7 ((uint32_t)0x0080) 480 481 #define MFXSTM32L152_GPIO_PIN_8 ((uint32_t)0x0100) 482 #define MFXSTM32L152_GPIO_PIN_9 ((uint32_t)0x0200) 483 #define MFXSTM32L152_GPIO_PIN_10 ((uint32_t)0x0400) 484 #define MFXSTM32L152_GPIO_PIN_11 ((uint32_t)0x0800) 485 #define MFXSTM32L152_GPIO_PIN_12 ((uint32_t)0x1000) 486 #define MFXSTM32L152_GPIO_PIN_13 ((uint32_t)0x2000) 487 #define MFXSTM32L152_GPIO_PIN_14 ((uint32_t)0x4000) 488 #define MFXSTM32L152_GPIO_PIN_15 ((uint32_t)0x8000) 489 490 #define MFXSTM32L152_GPIO_PIN_16 ((uint32_t)0x010000) 491 #define MFXSTM32L152_GPIO_PIN_17 ((uint32_t)0x020000) 492 #define MFXSTM32L152_GPIO_PIN_18 ((uint32_t)0x040000) 493 #define MFXSTM32L152_GPIO_PIN_19 ((uint32_t)0x080000) 494 #define MFXSTM32L152_GPIO_PIN_20 ((uint32_t)0x100000) 495 #define MFXSTM32L152_GPIO_PIN_21 ((uint32_t)0x200000) 496 #define MFXSTM32L152_GPIO_PIN_22 ((uint32_t)0x400000) 497 #define MFXSTM32L152_GPIO_PIN_23 ((uint32_t)0x800000) 498 499 #define MFXSTM32L152_AGPIO_PIN_0 MFXSTM32L152_GPIO_PIN_16 500 #define MFXSTM32L152_AGPIO_PIN_1 MFXSTM32L152_GPIO_PIN_17 501 #define MFXSTM32L152_AGPIO_PIN_2 MFXSTM32L152_GPIO_PIN_18 502 #define MFXSTM32L152_AGPIO_PIN_3 MFXSTM32L152_GPIO_PIN_19 503 #define MFXSTM32L152_AGPIO_PIN_4 MFXSTM32L152_GPIO_PIN_20 504 #define MFXSTM32L152_AGPIO_PIN_5 MFXSTM32L152_GPIO_PIN_21 505 #define MFXSTM32L152_AGPIO_PIN_6 MFXSTM32L152_GPIO_PIN_22 506 #define MFXSTM32L152_AGPIO_PIN_7 MFXSTM32L152_GPIO_PIN_23 507 508 #define MFXSTM32L152_GPIO_PINS_ALL ((uint32_t)0xFFFFFF) 509 510 /** 511 * @brief GPIO: constant 512 */ 513 #define MFXSTM32L152_GPIO_DIR_IN ((uint8_t)0x0) 514 #define MFXSTM32L152_GPIO_DIR_OUT ((uint8_t)0x1) 515 #define MFXSTM32L152_IRQ_GPI_EVT_LEVEL ((uint8_t)0x0) 516 #define MFXSTM32L152_IRQ_GPI_EVT_EDGE ((uint8_t)0x1) 517 #define MFXSTM32L152_IRQ_GPI_TYPE_LLFE ((uint8_t)0x0) /* Low Level Falling Edge */ 518 #define MFXSTM32L152_IRQ_GPI_TYPE_HLRE ((uint8_t)0x1) /*High Level Raising Edge */ 519 #define MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR ((uint8_t)0x0) 520 #define MFXSTM32L152_GPI_WITH_PULL_RESISTOR ((uint8_t)0x1) 521 #define MFXSTM32L152_GPO_PUSH_PULL ((uint8_t)0x0) 522 #define MFXSTM32L152_GPO_OPEN_DRAIN ((uint8_t)0x1) 523 #define MFXSTM32L152_GPIO_PULL_DOWN ((uint8_t)0x0) 524 #define MFXSTM32L152_GPIO_PULL_UP ((uint8_t)0x1) 525 526 527 /** 528 * @brief TOUCH SCREEN Registers 529 */ 530 531 /** 532 * @brief Touch Screen Registers 533 */ 534 #define MFXSTM32L152_TS_SETTLING ((uint8_t)0xA0) 535 #define MFXSTM32L152_TS_TOUCH_DET_DELAY ((uint8_t)0xA1) 536 #define MFXSTM32L152_TS_AVE ((uint8_t)0xA2) 537 #define MFXSTM32L152_TS_TRACK ((uint8_t)0xA3) 538 #define MFXSTM32L152_TS_FIFO_TH ((uint8_t)0xA4) 539 #define MFXSTM32L152_TS_FIFO_STA ((uint8_t)0x20) 540 #define MFXSTM32L152_TS_FIFO_LEVEL ((uint8_t)0x21) 541 #define MFXSTM32L152_TS_XY_DATA ((uint8_t)0x24) 542 543 /** 544 * @brief TS registers masks 545 */ 546 #define MFXSTM32L152_TS_CTRL_STATUS ((uint8_t)0x08) 547 #define MFXSTM32L152_TS_CLEAR_FIFO ((uint8_t)0x80) 548 549 550 /** 551 * @brief Register address: Idd control register (R/W) 552 */ 553 #define MFXSTM32L152_REG_ADR_IDD_CTRL ((uint8_t)0x80) 554 555 /** 556 * @brief Register address: Idd pre delay register (R/W) 557 */ 558 #define MFXSTM32L152_REG_ADR_IDD_PRE_DELAY ((uint8_t)0x81) 559 560 /** 561 * @brief Register address: Idd Shunt registers (R/W) 562 */ 563 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB ((uint8_t)0x82) 564 #define MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB ((uint8_t)0x83) 565 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB ((uint8_t)0x84) 566 #define MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB ((uint8_t)0x85) 567 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB ((uint8_t)0x86) 568 #define MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB ((uint8_t)0x87) 569 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB ((uint8_t)0x88) 570 #define MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB ((uint8_t)0x89) 571 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB ((uint8_t)0x8A) 572 #define MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB ((uint8_t)0x8B) 573 574 /** 575 * @brief Register address: Idd ampli gain register (R/W) 576 */ 577 #define MFXSTM32L152_REG_ADR_IDD_GAIN_MSB ((uint8_t)0x8C) 578 #define MFXSTM32L152_REG_ADR_IDD_GAIN_LSB ((uint8_t)0x8D) 579 580 /** 581 * @brief Register address: Idd VDD min register (R/W) 582 */ 583 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB ((uint8_t)0x8E) 584 #define MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB ((uint8_t)0x8F) 585 586 /** 587 * @brief Register address: Idd value register (R) 588 */ 589 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MSB ((uint8_t)0x14) 590 #define MFXSTM32L152_REG_ADR_IDD_VALUE_MID ((uint8_t)0x15) 591 #define MFXSTM32L152_REG_ADR_IDD_VALUE_LSB ((uint8_t)0x16) 592 593 /** 594 * @brief Register address: Idd calibration offset register (R) 595 */ 596 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_MSB ((uint8_t)0x18) 597 #define MFXSTM32L152_REG_ADR_IDD_CAL_OFFSET_LSB ((uint8_t)0x19) 598 599 /** 600 * @brief Register address: Idd shunt used offset register (R) 601 */ 602 #define MFXSTM32L152_REG_ADR_IDD_SHUNT_USED ((uint8_t)0x1A) 603 604 /** 605 * @brief Register address: shunt stabilisation delay registers (R/W) 606 */ 607 #define MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION ((uint8_t)0x90) 608 #define MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION ((uint8_t)0x91) 609 #define MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION ((uint8_t)0x92) 610 #define MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION ((uint8_t)0x93) 611 #define MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION ((uint8_t)0x94) 612 613 /** 614 * @brief Register address: Idd number of measurements register (R/W) 615 */ 616 #define MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS ((uint8_t)0x96) 617 618 /** 619 * @brief Register address: Idd delta delay between 2 measurements register (R/W) 620 */ 621 #define MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY ((uint8_t)0x97) 622 623 /** 624 * @brief Register address: Idd number of shunt on board register (R/W) 625 */ 626 #define MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD ((uint8_t)0x98) 627 628 629 630 /** @defgroup IDD_Control_Register_Defines IDD Control Register Defines 631 * @{ 632 */ 633 /** 634 * @brief IDD control register masks 635 */ 636 #define MFXSTM32L152_IDD_CTRL_REQ ((uint8_t)0x01) 637 #define MFXSTM32L152_IDD_CTRL_SHUNT_NB ((uint8_t)0x0E) 638 #define MFXSTM32L152_IDD_CTRL_VREF_DIS ((uint8_t)0x40) 639 #define MFXSTM32L152_IDD_CTRL_CAL_DIS ((uint8_t)0x80) 640 641 /** 642 * @brief IDD Shunt Number 643 */ 644 #define MFXSTM32L152_IDD_SHUNT_NB_1 ((uint8_t) 0x01) 645 #define MFXSTM32L152_IDD_SHUNT_NB_2 ((uint8_t) 0x02) 646 #define MFXSTM32L152_IDD_SHUNT_NB_3 ((uint8_t) 0x03) 647 #define MFXSTM32L152_IDD_SHUNT_NB_4 ((uint8_t) 0x04) 648 #define MFXSTM32L152_IDD_SHUNT_NB_5 ((uint8_t) 0x05) 649 650 /** 651 * @brief Vref Measurement 652 */ 653 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_ENABLE ((uint8_t) 0x00) 654 #define MFXSTM32L152_IDD_VREF_AUTO_MEASUREMENT_DISABLE ((uint8_t) 0x70) 655 656 /** 657 * @brief IDD Calibration 658 */ 659 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_ENABLE ((uint8_t) 0x00) 660 #define MFXSTM32L152_IDD_AUTO_CALIBRATION_DISABLE ((uint8_t) 0x80) 661 /** 662 * @} 663 */ 664 665 /** @defgroup IDD_PreDelay_Defines IDD PreDelay Defines 666 * @{ 667 */ 668 /** 669 * @brief IDD PreDelay masks 670 */ 671 #define MFXSTM32L152_IDD_PREDELAY_UNIT ((uint8_t) 0x80) 672 #define MFXSTM32L152_IDD_PREDELAY_VALUE ((uint8_t) 0x7F) 673 674 675 /** 676 * @brief IDD PreDelay unit 677 */ 678 #define MFXSTM32L152_IDD_PREDELAY_0_5_MS ((uint8_t) 0x00) 679 #define MFXSTM32L152_IDD_PREDELAY_20_MS ((uint8_t) 0x80) 680 /** 681 * @} 682 */ 683 684 /** @defgroup IDD_DeltaDelay_Defines IDD Delta DElay Defines 685 * @{ 686 */ 687 /** 688 * @brief IDD Delta Delay masks 689 */ 690 #define MFXSTM32L152_IDD_DELTADELAY_UNIT ((uint8_t) 0x80) 691 #define MFXSTM32L152_IDD_DELTADELAY_VALUE ((uint8_t) 0x7F) 692 693 694 /** 695 * @brief IDD Delta Delay unit 696 */ 697 #define MFXSTM32L152_IDD_DELTADELAY_0_5_MS ((uint8_t) 0x00) 698 #define MFXSTM32L152_IDD_DELTADELAY_20_MS ((uint8_t) 0x80) 699 700 701 /** 702 * @} 703 */ 704 705 /** 706 * @} 707 */ 708 709 710 /* Exported macro ------------------------------------------------------------*/ 711 712 /** @defgroup MFXSTM32L152_Exported_Macros 713 * @{ 714 */ 715 716 /** 717 * @} 718 */ 719 720 /* Exported functions --------------------------------------------------------*/ 721 722 /** @defgroup MFXSTM32L152_Exported_Functions 723 * @{ 724 */ 725 726 /** 727 * @brief MFXSTM32L152 Control functions 728 */ 729 void mfxstm32l152_Init(uint16_t DeviceAddr); 730 void mfxstm32l152_DeInit(uint16_t DeviceAddr); 731 void mfxstm32l152_Reset(uint16_t DeviceAddr); 732 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr); 733 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr); 734 void mfxstm32l152_LowPower(uint16_t DeviceAddr); 735 void mfxstm32l152_WakeUp(uint16_t DeviceAddr); 736 737 void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source); 738 void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source); 739 uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source); 740 void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source); 741 742 void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity); 743 void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type); 744 745 746 /** 747 * @brief MFXSTM32L152 IO functionalities functions 748 */ 749 void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin); 750 uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode); 751 void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState); 752 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin); 753 void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr); 754 void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr); 755 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin); 756 void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin); 757 758 void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction); 759 void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr); 760 void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr); 761 void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type); 762 void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt); 763 void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin); 764 void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin); 765 766 /** 767 * @brief MFXSTM32L152 Touch screen functionalities functions 768 */ 769 void mfxstm32l152_TS_Start(uint16_t DeviceAddr); 770 uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr); 771 void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y); 772 void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr); 773 void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr); 774 uint8_t mfxstm32l152_TS_ITStatus (uint16_t DeviceAddr); 775 void mfxstm32l152_TS_ClearIT (uint16_t DeviceAddr); 776 777 /** 778 * @brief MFXSTM32L152 IDD current measurement functionalities functions 779 */ 780 void mfxstm32l152_IDD_Start(uint16_t DeviceAddr); 781 void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig); 782 void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit); 783 void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue); 784 uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr); 785 void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr); 786 void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr); 787 uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr); 788 void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr); 789 790 /** 791 * @brief MFXSTM32L152 Error management functions 792 */ 793 uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr); 794 uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr); 795 void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr); 796 void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr); 797 uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr); 798 void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr); 799 800 uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr); 801 void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value); 802 803 804 805 /** 806 * @brief iobus prototypes (they should be defined in common/stm32_iobus.h) 807 */ 808 void MFX_IO_Init(void); 809 void MFX_IO_DeInit(void); 810 void MFX_IO_ITConfig (void); 811 void MFX_IO_EnableWakeupPin(void); 812 void MFX_IO_Wakeup(void); 813 void MFX_IO_Delay(uint32_t delay); 814 void MFX_IO_Write(uint16_t addr, uint8_t reg, uint8_t value); 815 uint8_t MFX_IO_Read(uint16_t addr, uint8_t reg); 816 uint16_t MFX_IO_ReadMultiple(uint16_t addr, uint8_t reg, uint8_t *buffer, uint16_t length); 817 818 /** 819 * @} 820 */ 821 822 /* Touch screen driver structure */ 823 extern TS_DrvTypeDef mfxstm32l152_ts_drv; 824 825 /* IO driver structure */ 826 extern IO_DrvTypeDef mfxstm32l152_io_drv; 827 828 /* IDD driver structure */ 829 extern IDD_DrvTypeDef mfxstm32l152_idd_drv; 830 831 832 #ifdef __cplusplus 833 } 834 #endif 835 #endif /* __MFXSTM32L152_H */ 836 837 838 /** 839 * @} 840 */ 841 842 /** 843 * @} 844 */ 845 846 /** 847 * @} 848 */ 849 850 /** 851 * @} 852 */ 853 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 854