1 /*
2  * ===========================================================================================
3  *
4  *       Filename:  sunxi_hal_spi.h
5  *
6  *    Description:  SPI HAL definition.
7  *
8  *        Version:  Melis3.0
9  *         Create:  2020-04-08 11:11:56
10  *       Revision:  none
11  *       Compiler:  GCC:version 9.2.1
12  *
13  *         Author:  bantao@allwinnertech.com
14  *   Organization:  SWC-BPD
15  *  Last Modified:  2020-04-08 16:02:11
16  *
17  * ===========================================================================================
18  */
19 
20 #ifndef SUNXI_IR_RX_H
21 #define SUNXI_IR_RX_H
22 
23 #ifdef __cplusplus
24 extern "C"
25 {
26 #endif
27 
28 #include "sunxi_hal_common.h"
29 #include <hal_gpio.h>
30 #include <hal_sem.h>
31 #include <hal_clk.h>
32 
33 
34 #define SUNXI_IRADC_PBASE         0X07040000 /* 0x34 */
35 
36 #define SUNXI_IRQ_IRADC                 155
37 
38 #define IRADC_PIN    GPIO_PH0
39 #define IR_MUXSEL 4
40 #define IR_DRVSEL 2
41 
42 
43 /* Registers */
44 #define IR_CTRL_REG     (0x00)  /* IR Control */
45 #define IR_RXCFG_REG        (0x10)  /* Rx Config */
46 #define IR_RXDAT_REG        (0x20)  /* Rx Data */
47 #define IR_RXINTE_REG       (0x2C)  /* Rx Interrupt Enable */
48 #define IR_RXINTS_REG       (0x30)  /* Rx Interrupt Status */
49 #define IR_SPLCFG_REG       (0x34)  /* IR Sample Config */
50 
51 #define IR_FIFO_SIZE        (64)    /* 64Bytes */
52 
53 #define IR_SIMPLE_UNIT      (21000)     /* simple in ns */
54 #define IR_CLK          (24000000)  /* 24Mhz */
55 #define IR_SAMPLE_DEV       (0x3<<0)    /* 24MHz/512 =46875Hz (~21us) */
56 
57 /* Active Threshold (0+1)*128clock*21us = 2.6ms */
58 #define IR_ACTIVE_T     ((0&0xff)<<16)
59 
60 /* Filter Threshold = 16*21us = 336us < 500us */
61 #define IR_RXFILT_VAL       (((16)&0x3f)<<2)
62 
63 /* Filter Threshold = 22*21us = 336us < 500us */
64 #define IR_RXFILT_VAL_RC5   (((22)&0x3f)<<2)
65 
66 /* Idle Threshold = (5+1)*128clock*21us = 16ms > 9ms */
67 #define IR_RXIDLE_VAL       (((5)&0xff)<<8)
68 
69 /* Active Threshold (0+1)*128clock*21us = 2.6ms */
70 #define IR_ACTIVE_T_SAMPLE  ((16&0xff)<<16)
71 
72 #define IR_ACTIVE_T_C       (1<<23)     /* Active Threshold */
73 #define IR_CIR_MODE     (0x3<<4)    /* CIR mode enable */
74 #define IR_ENTIRE_ENABLE    (0x3<<0)    /* IR entire enable */
75 #define IR_FIFO_20      (((20)-1)<<8)
76 #define IR_IRQ_STATUS       ((0x1<<4)|0x3)
77 #define IR_BOTH_PULSE       (0x1 << 6)
78 #define IR_LOW_PULSE        (0x2 << 6)
79 #define IR_HIGH_PULSE       (0x3 << 6)
80 
81 /*Bit Definition of IR_RXINTS_REG Register*/
82 #define IR_RXINTS_RXOF      (0x1<<0)    /* Rx FIFO Overflow */
83 #define IR_RXINTS_RXPE      (0x1<<1)    /* Rx Packet End */
84 #define IR_RXINTS_RXDA      (0x1<<4)    /* Rx FIFO Data Available */
85 
86 
87 enum ir_mode {
88     CIR_MODE_ENABLE,
89     IR_MODULE_ENABLE,
90     IR_BOTH_PULSE_MODE, /* new feature to avoid noisy */
91     IR_LOW_PULSE_MODE,
92     IR_HIGH_PULSE_MODE,
93 };
94 
95 enum ir_sample_config {
96     IR_SAMPLE_REG_CLEAR,
97     IR_CLK_SAMPLE,
98     IR_FILTER_TH_NEC,
99     IR_FILTER_TH_RC5,
100     IR_IDLE_TH,
101     IR_ACTIVE_TH,
102     IR_ACTIVE_TH_SAMPLE,
103 };
104 
105 enum ir_irq_config {
106     IR_IRQ_STATUS_CLEAR,
107     IR_IRQ_ENABLE,
108     IR_IRQ_FIFO_SIZE,
109 };
110 
111 typedef enum
112 {
113     IR_PIN_ERR = -3,
114     IR_CLK_ERR = -2,
115     IR_IRQ_ERR = -1,
116     IR_OK = 0,
117 } hal_ir_status_t;
118 
119 typedef int (*ir_callback_t)(uint32_t data_type, uint32_t data);
120 
121 typedef struct sunxi_ir
122 {
123     uint16_t irq_num;
124     uint32_t reg_base;
125 
126     gpio_pin_t pin;
127     uint8_t pin_mux;
128     uint8_t pin_drv;
129 
130     ir_callback_t callback;
131 } hal_ir_t;
132 
133 int hal_ir_register_callback(ir_callback_t callback);
134 int hal_ir_init(void);
135 
136 #ifdef __cplusplus
137 }
138 #endif
139 
140 
141 #endif
142