1 /* 2 * Copyright (c) 2022, sakumisu 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef __USB_FSDEV_REG_H__ 7 #define __USB_FSDEV_REG_H__ 8 9 #define __IO volatile /*!< Defines 'read / write' permissions */ 10 /** 11 * @brief Universal Serial Bus Full Speed Device 12 */ 13 14 typedef struct 15 { 16 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ 17 __IO uint16_t RESERVED0; /*!< Reserved */ 18 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ 19 __IO uint16_t RESERVED1; /*!< Reserved */ 20 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ 21 __IO uint16_t RESERVED2; /*!< Reserved */ 22 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ 23 __IO uint16_t RESERVED3; /*!< Reserved */ 24 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ 25 __IO uint16_t RESERVED4; /*!< Reserved */ 26 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ 27 __IO uint16_t RESERVED5; /*!< Reserved */ 28 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ 29 __IO uint16_t RESERVED6; /*!< Reserved */ 30 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ 31 __IO uint16_t RESERVED7[17]; /*!< Reserved */ 32 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ 33 __IO uint16_t RESERVED8; /*!< Reserved */ 34 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ 35 __IO uint16_t RESERVED9; /*!< Reserved */ 36 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ 37 __IO uint16_t RESERVEDA; /*!< Reserved */ 38 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ 39 __IO uint16_t RESERVEDB; /*!< Reserved */ 40 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ 41 __IO uint16_t RESERVEDC; /*!< Reserved */ 42 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ 43 __IO uint16_t RESERVEDD; /*!< Reserved */ 44 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ 45 __IO uint16_t RESERVEDE; /*!< Reserved */ 46 } USB_TypeDef; 47 48 /******************************************************************************/ 49 /* */ 50 /* USB Device FS */ 51 /* */ 52 /******************************************************************************/ 53 54 /*!< Endpoint-specific registers */ 55 #define USB_EP0R USB_BASE /*!< Endpoint 0 register address */ 56 #define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */ 57 #define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */ 58 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */ 59 #define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */ 60 #define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */ 61 #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ 62 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ 63 64 /* bit positions */ 65 #define USB_EP_CTR_RX_Pos (15U) 66 #define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ 67 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ 68 #define USB_EP_DTOG_RX_Pos (14U) 69 #define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ 70 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ 71 #define USB_EPRX_STAT_Pos (12U) 72 #define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ 73 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ 74 #define USB_EP_SETUP_Pos (11U) 75 #define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */ 76 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ 77 #define USB_EP_T_FIELD_Pos (9U) 78 #define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ 79 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ 80 #define USB_EP_KIND_Pos (8U) 81 #define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */ 82 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ 83 #define USB_EP_CTR_TX_Pos (7U) 84 #define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ 85 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ 86 #define USB_EP_DTOG_TX_Pos (6U) 87 #define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ 88 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ 89 #define USB_EPTX_STAT_Pos (4U) 90 #define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ 91 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ 92 #define USB_EPADDR_FIELD_Pos (0U) 93 #define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ 94 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ 95 96 /* EndPoint REGister MASK (no toggle fields) */ 97 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) 98 /*!< EP_TYPE[1:0] EndPoint TYPE */ 99 #define USB_EP_TYPE_MASK_Pos (9U) 100 #define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ 101 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ 102 #define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */ 103 #define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */ 104 #define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */ 105 #define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */ 106 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) 107 108 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ 109 /*!< STAT_TX[1:0] STATus for TX transfer */ 110 #define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */ 111 #define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */ 112 #define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */ 113 #define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */ 114 #define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */ 115 #define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */ 116 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) 117 /*!< STAT_RX[1:0] STATus for RX transfer */ 118 #define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */ 119 #define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */ 120 #define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */ 121 #define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */ 122 #define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */ 123 #define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */ 124 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) 125 126 /******************* Bit definition for USB_EP0R register *******************/ 127 #define USB_EP0R_EA_Pos (0U) 128 #define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */ 129 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */ 130 131 #define USB_EP0R_STAT_TX_Pos (4U) 132 #define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ 133 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 134 #define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ 135 #define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ 136 137 #define USB_EP0R_DTOG_TX_Pos (6U) 138 #define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ 139 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 140 #define USB_EP0R_CTR_TX_Pos (7U) 141 #define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ 142 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 143 #define USB_EP0R_EP_KIND_Pos (8U) 144 #define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ 145 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */ 146 147 #define USB_EP0R_EP_TYPE_Pos (9U) 148 #define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ 149 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 150 #define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ 151 #define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ 152 153 #define USB_EP0R_SETUP_Pos (11U) 154 #define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ 155 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */ 156 157 #define USB_EP0R_STAT_RX_Pos (12U) 158 #define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ 159 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 160 #define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ 161 #define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ 162 163 #define USB_EP0R_DTOG_RX_Pos (14U) 164 #define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ 165 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 166 #define USB_EP0R_CTR_RX_Pos (15U) 167 #define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ 168 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */ 169 170 /******************* Bit definition for USB_EP1R register *******************/ 171 #define USB_EP1R_EA_Pos (0U) 172 #define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */ 173 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */ 174 175 #define USB_EP1R_STAT_TX_Pos (4U) 176 #define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ 177 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 178 #define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ 179 #define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ 180 181 #define USB_EP1R_DTOG_TX_Pos (6U) 182 #define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ 183 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 184 #define USB_EP1R_CTR_TX_Pos (7U) 185 #define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ 186 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 187 #define USB_EP1R_EP_KIND_Pos (8U) 188 #define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ 189 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */ 190 191 #define USB_EP1R_EP_TYPE_Pos (9U) 192 #define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ 193 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 194 #define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ 195 #define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ 196 197 #define USB_EP1R_SETUP_Pos (11U) 198 #define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ 199 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */ 200 201 #define USB_EP1R_STAT_RX_Pos (12U) 202 #define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ 203 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 204 #define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ 205 #define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ 206 207 #define USB_EP1R_DTOG_RX_Pos (14U) 208 #define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ 209 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 210 #define USB_EP1R_CTR_RX_Pos (15U) 211 #define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ 212 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */ 213 214 /******************* Bit definition for USB_EP2R register *******************/ 215 #define USB_EP2R_EA_Pos (0U) 216 #define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */ 217 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */ 218 219 #define USB_EP2R_STAT_TX_Pos (4U) 220 #define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ 221 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 222 #define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ 223 #define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ 224 225 #define USB_EP2R_DTOG_TX_Pos (6U) 226 #define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ 227 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 228 #define USB_EP2R_CTR_TX_Pos (7U) 229 #define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ 230 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 231 #define USB_EP2R_EP_KIND_Pos (8U) 232 #define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ 233 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */ 234 235 #define USB_EP2R_EP_TYPE_Pos (9U) 236 #define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ 237 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 238 #define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ 239 #define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ 240 241 #define USB_EP2R_SETUP_Pos (11U) 242 #define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ 243 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */ 244 245 #define USB_EP2R_STAT_RX_Pos (12U) 246 #define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ 247 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 248 #define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ 249 #define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ 250 251 #define USB_EP2R_DTOG_RX_Pos (14U) 252 #define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ 253 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 254 #define USB_EP2R_CTR_RX_Pos (15U) 255 #define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ 256 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */ 257 258 /******************* Bit definition for USB_EP3R register *******************/ 259 #define USB_EP3R_EA_Pos (0U) 260 #define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */ 261 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */ 262 263 #define USB_EP3R_STAT_TX_Pos (4U) 264 #define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ 265 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 266 #define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ 267 #define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ 268 269 #define USB_EP3R_DTOG_TX_Pos (6U) 270 #define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ 271 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 272 #define USB_EP3R_CTR_TX_Pos (7U) 273 #define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ 274 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 275 #define USB_EP3R_EP_KIND_Pos (8U) 276 #define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ 277 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */ 278 279 #define USB_EP3R_EP_TYPE_Pos (9U) 280 #define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ 281 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 282 #define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ 283 #define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ 284 285 #define USB_EP3R_SETUP_Pos (11U) 286 #define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ 287 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */ 288 289 #define USB_EP3R_STAT_RX_Pos (12U) 290 #define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ 291 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 292 #define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ 293 #define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ 294 295 #define USB_EP3R_DTOG_RX_Pos (14U) 296 #define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ 297 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 298 #define USB_EP3R_CTR_RX_Pos (15U) 299 #define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ 300 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */ 301 302 /******************* Bit definition for USB_EP4R register *******************/ 303 #define USB_EP4R_EA_Pos (0U) 304 #define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */ 305 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */ 306 307 #define USB_EP4R_STAT_TX_Pos (4U) 308 #define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ 309 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 310 #define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ 311 #define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ 312 313 #define USB_EP4R_DTOG_TX_Pos (6U) 314 #define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ 315 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 316 #define USB_EP4R_CTR_TX_Pos (7U) 317 #define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ 318 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 319 #define USB_EP4R_EP_KIND_Pos (8U) 320 #define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ 321 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */ 322 323 #define USB_EP4R_EP_TYPE_Pos (9U) 324 #define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ 325 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 326 #define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ 327 #define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ 328 329 #define USB_EP4R_SETUP_Pos (11U) 330 #define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ 331 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */ 332 333 #define USB_EP4R_STAT_RX_Pos (12U) 334 #define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ 335 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 336 #define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ 337 #define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ 338 339 #define USB_EP4R_DTOG_RX_Pos (14U) 340 #define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ 341 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 342 #define USB_EP4R_CTR_RX_Pos (15U) 343 #define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ 344 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */ 345 346 /******************* Bit definition for USB_EP5R register *******************/ 347 #define USB_EP5R_EA_Pos (0U) 348 #define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */ 349 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */ 350 351 #define USB_EP5R_STAT_TX_Pos (4U) 352 #define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ 353 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 354 #define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ 355 #define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ 356 357 #define USB_EP5R_DTOG_TX_Pos (6U) 358 #define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ 359 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 360 #define USB_EP5R_CTR_TX_Pos (7U) 361 #define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ 362 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 363 #define USB_EP5R_EP_KIND_Pos (8U) 364 #define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ 365 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */ 366 367 #define USB_EP5R_EP_TYPE_Pos (9U) 368 #define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ 369 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 370 #define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ 371 #define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ 372 373 #define USB_EP5R_SETUP_Pos (11U) 374 #define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ 375 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */ 376 377 #define USB_EP5R_STAT_RX_Pos (12U) 378 #define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ 379 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 380 #define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ 381 #define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ 382 383 #define USB_EP5R_DTOG_RX_Pos (14U) 384 #define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ 385 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 386 #define USB_EP5R_CTR_RX_Pos (15U) 387 #define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ 388 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */ 389 390 /******************* Bit definition for USB_EP6R register *******************/ 391 #define USB_EP6R_EA_Pos (0U) 392 #define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */ 393 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */ 394 395 #define USB_EP6R_STAT_TX_Pos (4U) 396 #define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ 397 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 398 #define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ 399 #define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ 400 401 #define USB_EP6R_DTOG_TX_Pos (6U) 402 #define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ 403 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 404 #define USB_EP6R_CTR_TX_Pos (7U) 405 #define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ 406 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 407 #define USB_EP6R_EP_KIND_Pos (8U) 408 #define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ 409 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */ 410 411 #define USB_EP6R_EP_TYPE_Pos (9U) 412 #define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ 413 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 414 #define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ 415 #define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ 416 417 #define USB_EP6R_SETUP_Pos (11U) 418 #define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ 419 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */ 420 421 #define USB_EP6R_STAT_RX_Pos (12U) 422 #define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ 423 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 424 #define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ 425 #define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ 426 427 #define USB_EP6R_DTOG_RX_Pos (14U) 428 #define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ 429 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 430 #define USB_EP6R_CTR_RX_Pos (15U) 431 #define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ 432 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */ 433 434 /******************* Bit definition for USB_EP7R register *******************/ 435 #define USB_EP7R_EA_Pos (0U) 436 #define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */ 437 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */ 438 439 #define USB_EP7R_STAT_TX_Pos (4U) 440 #define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ 441 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 442 #define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ 443 #define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ 444 445 #define USB_EP7R_DTOG_TX_Pos (6U) 446 #define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ 447 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 448 #define USB_EP7R_CTR_TX_Pos (7U) 449 #define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ 450 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 451 #define USB_EP7R_EP_KIND_Pos (8U) 452 #define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ 453 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */ 454 455 #define USB_EP7R_EP_TYPE_Pos (9U) 456 #define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ 457 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 458 #define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ 459 #define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ 460 461 #define USB_EP7R_SETUP_Pos (11U) 462 #define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ 463 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */ 464 465 #define USB_EP7R_STAT_RX_Pos (12U) 466 #define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ 467 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 468 #define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ 469 #define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ 470 471 #define USB_EP7R_DTOG_RX_Pos (14U) 472 #define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ 473 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 474 #define USB_EP7R_CTR_RX_Pos (15U) 475 #define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ 476 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */ 477 478 /*!< Common registers */ 479 /******************* Bit definition for USB_CNTR register *******************/ 480 #define USB_CNTR_FRES_Pos (0U) 481 #define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ 482 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */ 483 #define USB_CNTR_PDWN_Pos (1U) 484 #define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ 485 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */ 486 #define USB_CNTR_LP_MODE_Pos (2U) 487 #define USB_CNTR_LP_MODE_Msk (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */ 488 #define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */ 489 #define USB_CNTR_FSUSP_Pos (3U) 490 #define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ 491 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */ 492 #define USB_CNTR_RESUME_Pos (4U) 493 #define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ 494 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */ 495 #define USB_CNTR_ESOFM_Pos (8U) 496 #define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ 497 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */ 498 #define USB_CNTR_SOFM_Pos (9U) 499 #define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ 500 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */ 501 #define USB_CNTR_RESETM_Pos (10U) 502 #define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ 503 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */ 504 #define USB_CNTR_SUSPM_Pos (11U) 505 #define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ 506 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */ 507 #define USB_CNTR_WKUPM_Pos (12U) 508 #define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ 509 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */ 510 #define USB_CNTR_ERRM_Pos (13U) 511 #define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ 512 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */ 513 #define USB_CNTR_PMAOVRM_Pos (14U) 514 #define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ 515 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */ 516 #define USB_CNTR_CTRM_Pos (15U) 517 #define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ 518 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */ 519 520 /******************* Bit definition for USB_ISTR register *******************/ 521 #define USB_ISTR_EP_ID_Pos (0U) 522 #define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ 523 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */ 524 #define USB_ISTR_DIR_Pos (4U) 525 #define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ 526 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */ 527 #define USB_ISTR_ESOF_Pos (8U) 528 #define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ 529 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */ 530 #define USB_ISTR_SOF_Pos (9U) 531 #define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ 532 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */ 533 #define USB_ISTR_RESET_Pos (10U) 534 #define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ 535 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */ 536 #define USB_ISTR_SUSP_Pos (11U) 537 #define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ 538 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */ 539 #define USB_ISTR_WKUP_Pos (12U) 540 #define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ 541 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */ 542 #define USB_ISTR_ERR_Pos (13U) 543 #define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ 544 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */ 545 #define USB_ISTR_PMAOVR_Pos (14U) 546 #define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ 547 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */ 548 #define USB_ISTR_CTR_Pos (15U) 549 #define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ 550 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */ 551 552 /******************* Bit definition for USB_FNR register ********************/ 553 #define USB_FNR_FN_Pos (0U) 554 #define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */ 555 #define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */ 556 #define USB_FNR_LSOF_Pos (11U) 557 #define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ 558 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */ 559 #define USB_FNR_LCK_Pos (13U) 560 #define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */ 561 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */ 562 #define USB_FNR_RXDM_Pos (14U) 563 #define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ 564 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */ 565 #define USB_FNR_RXDP_Pos (15U) 566 #define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ 567 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */ 568 569 /****************** Bit definition for USB_DADDR register *******************/ 570 #define USB_DADDR_ADD_Pos (0U) 571 #define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ 572 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */ 573 #define USB_DADDR_ADD0_Pos (0U) 574 #define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ 575 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */ 576 #define USB_DADDR_ADD1_Pos (1U) 577 #define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ 578 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */ 579 #define USB_DADDR_ADD2_Pos (2U) 580 #define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ 581 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */ 582 #define USB_DADDR_ADD3_Pos (3U) 583 #define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ 584 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */ 585 #define USB_DADDR_ADD4_Pos (4U) 586 #define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ 587 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */ 588 #define USB_DADDR_ADD5_Pos (5U) 589 #define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ 590 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */ 591 #define USB_DADDR_ADD6_Pos (6U) 592 #define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ 593 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */ 594 595 #define USB_DADDR_EF_Pos (7U) 596 #define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */ 597 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */ 598 599 /****************** Bit definition for USB_BTABLE register ******************/ 600 #define USB_BTABLE_BTABLE_Pos (3U) 601 #define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ 602 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */ 603 604 /****************** Bits definition for USB_BCDR register *******************/ 605 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */ 606 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */ 607 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */ 608 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */ 609 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */ 610 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */ 611 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */ 612 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */ 613 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */ 614 615 /******************* Bit definition for LPMCSR register *********************/ 616 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */ 617 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/ 618 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */ 619 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */ 620 621 /*!< Buffer descriptor table */ 622 /***************** Bit definition for USB_ADDR0_TX register *****************/ 623 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) 624 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ 625 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ 626 627 /***************** Bit definition for USB_ADDR1_TX register *****************/ 628 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) 629 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ 630 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ 631 632 /***************** Bit definition for USB_ADDR2_TX register *****************/ 633 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) 634 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ 635 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ 636 637 /***************** Bit definition for USB_ADDR3_TX register *****************/ 638 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) 639 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ 640 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ 641 642 /***************** Bit definition for USB_ADDR4_TX register *****************/ 643 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) 644 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ 645 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ 646 647 /***************** Bit definition for USB_ADDR5_TX register *****************/ 648 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) 649 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ 650 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ 651 652 /***************** Bit definition for USB_ADDR6_TX register *****************/ 653 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) 654 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ 655 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ 656 657 /***************** Bit definition for USB_ADDR7_TX register *****************/ 658 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) 659 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ 660 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ 661 662 /*----------------------------------------------------------------------------*/ 663 664 /***************** Bit definition for USB_COUNT0_TX register ****************/ 665 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) 666 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ 667 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ 668 669 /***************** Bit definition for USB_COUNT1_TX register ****************/ 670 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) 671 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ 672 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ 673 674 /***************** Bit definition for USB_COUNT2_TX register ****************/ 675 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) 676 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ 677 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ 678 679 /***************** Bit definition for USB_COUNT3_TX register ****************/ 680 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) 681 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ 682 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ 683 684 /***************** Bit definition for USB_COUNT4_TX register ****************/ 685 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) 686 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ 687 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ 688 689 /***************** Bit definition for USB_COUNT5_TX register ****************/ 690 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) 691 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ 692 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ 693 694 /***************** Bit definition for USB_COUNT6_TX register ****************/ 695 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) 696 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ 697 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ 698 699 /***************** Bit definition for USB_COUNT7_TX register ****************/ 700 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) 701 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ 702 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ 703 704 /*----------------------------------------------------------------------------*/ 705 706 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 707 #define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */ 708 709 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 710 #define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */ 711 712 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 713 #define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */ 714 715 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 716 #define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */ 717 718 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 719 #define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */ 720 721 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 722 #define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */ 723 724 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 725 #define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */ 726 727 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 728 #define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */ 729 730 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 731 #define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */ 732 733 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 734 #define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */ 735 736 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 737 #define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */ 738 739 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 740 #define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */ 741 742 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 743 #define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */ 744 745 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 746 #define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */ 747 748 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 749 #define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */ 750 751 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 752 #define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */ 753 754 /*----------------------------------------------------------------------------*/ 755 756 /***************** Bit definition for USB_ADDR0_RX register *****************/ 757 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) 758 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ 759 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ 760 761 /***************** Bit definition for USB_ADDR1_RX register *****************/ 762 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) 763 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ 764 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ 765 766 /***************** Bit definition for USB_ADDR2_RX register *****************/ 767 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) 768 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ 769 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ 770 771 /***************** Bit definition for USB_ADDR3_RX register *****************/ 772 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) 773 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ 774 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ 775 776 /***************** Bit definition for USB_ADDR4_RX register *****************/ 777 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) 778 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ 779 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ 780 781 /***************** Bit definition for USB_ADDR5_RX register *****************/ 782 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) 783 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ 784 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ 785 786 /***************** Bit definition for USB_ADDR6_RX register *****************/ 787 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) 788 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ 789 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ 790 791 /***************** Bit definition for USB_ADDR7_RX register *****************/ 792 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) 793 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ 794 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ 795 796 /*----------------------------------------------------------------------------*/ 797 798 /***************** Bit definition for USB_COUNT0_RX register ****************/ 799 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) 800 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ 801 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ 802 803 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) 804 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 805 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 806 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 807 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 808 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 809 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 810 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 811 812 #define USB_COUNT0_RX_BLSIZE_Pos (15U) 813 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ 814 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ 815 816 /***************** Bit definition for USB_COUNT1_RX register ****************/ 817 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) 818 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ 819 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ 820 821 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) 822 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 823 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 824 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 825 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 826 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 827 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 828 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 829 830 #define USB_COUNT1_RX_BLSIZE_Pos (15U) 831 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ 832 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ 833 834 /***************** Bit definition for USB_COUNT2_RX register ****************/ 835 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) 836 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ 837 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ 838 839 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) 840 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 841 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 842 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 843 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 844 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 845 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 846 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 847 848 #define USB_COUNT2_RX_BLSIZE_Pos (15U) 849 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ 850 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ 851 852 /***************** Bit definition for USB_COUNT3_RX register ****************/ 853 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) 854 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ 855 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ 856 857 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) 858 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 859 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 860 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 861 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 862 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 863 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 864 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 865 866 #define USB_COUNT3_RX_BLSIZE_Pos (15U) 867 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ 868 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ 869 870 /***************** Bit definition for USB_COUNT4_RX register ****************/ 871 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) 872 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ 873 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ 874 875 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) 876 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 877 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 878 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 879 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 880 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 881 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 882 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 883 884 #define USB_COUNT4_RX_BLSIZE_Pos (15U) 885 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ 886 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ 887 888 /***************** Bit definition for USB_COUNT5_RX register ****************/ 889 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) 890 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ 891 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ 892 893 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) 894 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 895 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 896 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 897 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 898 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 899 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 900 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 901 902 #define USB_COUNT5_RX_BLSIZE_Pos (15U) 903 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ 904 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ 905 906 /***************** Bit definition for USB_COUNT6_RX register ****************/ 907 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) 908 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ 909 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ 910 911 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) 912 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 913 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 914 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 915 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 916 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 917 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 918 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 919 920 #define USB_COUNT6_RX_BLSIZE_Pos (15U) 921 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ 922 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ 923 924 /***************** Bit definition for USB_COUNT7_RX register ****************/ 925 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) 926 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ 927 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ 928 929 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) 930 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 931 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 932 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 933 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 934 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 935 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 936 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 937 938 #define USB_COUNT7_RX_BLSIZE_Pos (15U) 939 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ 940 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ 941 942 /*----------------------------------------------------------------------------*/ 943 944 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 945 #define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ 946 947 #define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 948 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ 949 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ 950 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ 951 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ 952 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ 953 954 #define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ 955 956 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 957 #define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ 958 959 #define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 960 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */ 961 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ 962 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ 963 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ 964 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ 965 966 #define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ 967 968 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 969 #define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ 970 971 #define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 972 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ 973 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ 974 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ 975 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ 976 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ 977 978 #define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ 979 980 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 981 #define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ 982 983 #define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 984 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ 985 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ 986 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ 987 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ 988 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ 989 990 #define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ 991 992 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 993 #define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ 994 995 #define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 996 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ 997 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ 998 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ 999 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ 1000 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ 1001 1002 #define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ 1003 1004 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 1005 #define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ 1006 1007 #define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 1008 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ 1009 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ 1010 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ 1011 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ 1012 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ 1013 1014 #define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ 1015 1016 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 1017 #define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ 1018 1019 #define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 1020 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ 1021 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ 1022 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ 1023 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ 1024 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ 1025 1026 #define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ 1027 1028 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 1029 #define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ 1030 1031 #define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 1032 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ 1033 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ 1034 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ 1035 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ 1036 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ 1037 1038 #define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ 1039 1040 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 1041 #define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ 1042 1043 #define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 1044 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ 1045 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ 1046 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ 1047 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ 1048 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ 1049 1050 #define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ 1051 1052 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 1053 #define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ 1054 1055 #define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 1056 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ 1057 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ 1058 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ 1059 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ 1060 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ 1061 1062 #define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ 1063 1064 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 1065 #define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ 1066 1067 #define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 1068 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ 1069 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ 1070 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ 1071 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ 1072 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ 1073 1074 #define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ 1075 1076 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 1077 #define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ 1078 1079 #define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 1080 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ 1081 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ 1082 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ 1083 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ 1084 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ 1085 1086 #define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ 1087 1088 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 1089 #define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ 1090 1091 #define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 1092 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ 1093 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ 1094 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ 1095 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ 1096 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ 1097 1098 #define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ 1099 1100 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 1101 #define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ 1102 1103 #define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 1104 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ 1105 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ 1106 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ 1107 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ 1108 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ 1109 1110 #define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ 1111 1112 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 1113 #define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ 1114 1115 #define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 1116 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ 1117 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ 1118 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ 1119 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ 1120 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ 1121 1122 #define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ 1123 1124 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 1125 #define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ 1126 1127 #define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 1128 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ 1129 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ 1130 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ 1131 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ 1132 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ 1133 1134 #define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ 1135 1136 /** 1137 * @} 1138 */ 1139 1140 #define BTABLE_ADDRESS 0x000U 1141 1142 #ifndef PMA_ACCESS 1143 #define PMA_ACCESS 2U 1144 #endif 1145 /******************** Bit definition for USB_COUNTn_RX register *************/ 1146 #define USB_CNTRX_NBLK_MSK (0x1FU << 10) 1147 #define USB_CNTRX_BLSIZE (0x1U << 15) 1148 1149 /* SetENDPOINT */ 1150 #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) 1151 1152 /* GetENDPOINT */ 1153 #define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) 1154 1155 /** 1156 * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) 1157 * @param USBx USB peripheral instance register address. 1158 * @param bEpNum Endpoint Number. 1159 * @param wType Endpoint Type. 1160 * @retval None 1161 */ 1162 #define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) 1163 1164 /** 1165 * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) 1166 * @param USBx USB peripheral instance register address. 1167 * @param bEpNum Endpoint Number. 1168 * @retval Endpoint Type 1169 */ 1170 #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) 1171 1172 /** 1173 * @brief free buffer used from the application realizing it to the line 1174 * toggles bit SW_BUF in the double buffered endpoint register 1175 * @param USBx USB device. 1176 * @param bEpNum, bDir 1177 * @retval None 1178 */ 1179 #define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \ 1180 do { \ 1181 if ((bDir) == 0U) \ 1182 { \ 1183 /* OUT double buffered endpoint */ \ 1184 PCD_TX_DTOG((USBx), (bEpNum)); \ 1185 } \ 1186 else if ((bDir) == 1U) \ 1187 { \ 1188 /* IN double buffered endpoint */ \ 1189 PCD_RX_DTOG((USBx), (bEpNum)); \ 1190 } \ 1191 } while(0) 1192 1193 /** 1194 * @brief sets the status for tx transfer (bits STAT_TX[1:0]). 1195 * @param USBx USB peripheral instance register address. 1196 * @param bEpNum Endpoint Number. 1197 * @param wState new state 1198 * @retval None 1199 */ 1200 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \ 1201 do { \ 1202 uint16_t _wRegVal; \ 1203 \ 1204 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ 1205 /* toggle first bit ? */ \ 1206 if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ 1207 { \ 1208 _wRegVal ^= USB_EPTX_DTOG1; \ 1209 } \ 1210 /* toggle second bit ? */ \ 1211 if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ 1212 { \ 1213 _wRegVal ^= USB_EPTX_DTOG2; \ 1214 } \ 1215 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 1216 } while(0) /* PCD_SET_EP_TX_STATUS */ 1217 1218 /** 1219 * @brief sets the status for rx transfer (bits STAT_TX[1:0]) 1220 * @param USBx USB peripheral instance register address. 1221 * @param bEpNum Endpoint Number. 1222 * @param wState new state 1223 * @retval None 1224 */ 1225 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \ 1226 do { \ 1227 uint16_t _wRegVal; \ 1228 \ 1229 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ 1230 /* toggle first bit ? */ \ 1231 if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ 1232 { \ 1233 _wRegVal ^= USB_EPRX_DTOG1; \ 1234 } \ 1235 /* toggle second bit ? */ \ 1236 if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ 1237 { \ 1238 _wRegVal ^= USB_EPRX_DTOG2; \ 1239 } \ 1240 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 1241 } while(0) /* PCD_SET_EP_RX_STATUS */ 1242 1243 /** 1244 * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) 1245 * @param USBx USB peripheral instance register address. 1246 * @param bEpNum Endpoint Number. 1247 * @param wStaterx new state. 1248 * @param wStatetx new state. 1249 * @retval None 1250 */ 1251 #define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \ 1252 do { \ 1253 uint16_t _wRegVal; \ 1254 \ 1255 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ 1256 /* toggle first bit ? */ \ 1257 if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \ 1258 { \ 1259 _wRegVal ^= USB_EPRX_DTOG1; \ 1260 } \ 1261 /* toggle second bit ? */ \ 1262 if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ 1263 { \ 1264 _wRegVal ^= USB_EPRX_DTOG2; \ 1265 } \ 1266 /* toggle first bit ? */ \ 1267 if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ 1268 { \ 1269 _wRegVal ^= USB_EPTX_DTOG1; \ 1270 } \ 1271 /* toggle second bit ? */ \ 1272 if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ 1273 { \ 1274 _wRegVal ^= USB_EPTX_DTOG2; \ 1275 } \ 1276 \ 1277 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 1278 } while(0) /* PCD_SET_EP_TXRX_STATUS */ 1279 1280 /** 1281 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] 1282 * /STAT_RX[1:0]) 1283 * @param USBx USB peripheral instance register address. 1284 * @param bEpNum Endpoint Number. 1285 * @retval status 1286 */ 1287 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) 1288 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) 1289 1290 /** 1291 * @brief sets directly the VALID tx/rx-status into the endpoint register 1292 * @param USBx USB peripheral instance register address. 1293 * @param bEpNum Endpoint Number. 1294 * @retval None 1295 */ 1296 #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) 1297 #define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) 1298 1299 /** 1300 * @brief checks stall condition in an endpoint. 1301 * @param USBx USB peripheral instance register address. 1302 * @param bEpNum Endpoint Number. 1303 * @retval TRUE = endpoint in stall condition. 1304 */ 1305 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL) 1306 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL) 1307 1308 /** 1309 * @brief set & clear EP_KIND bit. 1310 * @param USBx USB peripheral instance register address. 1311 * @param bEpNum Endpoint Number. 1312 * @retval None 1313 */ 1314 #define PCD_SET_EP_KIND(USBx, bEpNum) \ 1315 do { \ 1316 uint16_t _wRegVal; \ 1317 \ 1318 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ 1319 \ 1320 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ 1321 } while(0) /* PCD_SET_EP_KIND */ 1322 1323 #define PCD_CLEAR_EP_KIND(USBx, bEpNum) \ 1324 do { \ 1325 uint16_t _wRegVal; \ 1326 \ 1327 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ 1328 \ 1329 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 1330 } while(0) /* PCD_CLEAR_EP_KIND */ 1331 1332 /** 1333 * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. 1334 * @param USBx USB peripheral instance register address. 1335 * @param bEpNum Endpoint Number. 1336 * @retval None 1337 */ 1338 #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) 1339 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) 1340 1341 /** 1342 * @brief Sets/clears directly EP_KIND bit in the endpoint register. 1343 * @param USBx USB peripheral instance register address. 1344 * @param bEpNum Endpoint Number. 1345 * @retval None 1346 */ 1347 #define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) 1348 #define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) 1349 1350 /** 1351 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. 1352 * @param USBx USB peripheral instance register address. 1353 * @param bEpNum Endpoint Number. 1354 * @retval None 1355 */ 1356 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \ 1357 do { \ 1358 uint16_t _wRegVal; \ 1359 \ 1360 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ 1361 \ 1362 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ 1363 } while(0) /* PCD_CLEAR_RX_EP_CTR */ 1364 1365 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \ 1366 do { \ 1367 uint16_t _wRegVal; \ 1368 \ 1369 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ 1370 \ 1371 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \ 1372 } while(0) /* PCD_CLEAR_TX_EP_CTR */ 1373 1374 /** 1375 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. 1376 * @param USBx USB peripheral instance register address. 1377 * @param bEpNum Endpoint Number. 1378 * @retval None 1379 */ 1380 #define PCD_RX_DTOG(USBx, bEpNum) \ 1381 do { \ 1382 uint16_t _wEPVal; \ 1383 \ 1384 _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ 1385 \ 1386 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ 1387 } while(0) /* PCD_RX_DTOG */ 1388 1389 #define PCD_TX_DTOG(USBx, bEpNum) \ 1390 do { \ 1391 uint16_t _wEPVal; \ 1392 \ 1393 _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ 1394 \ 1395 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \ 1396 } while(0) /* PCD_TX_DTOG */ 1397 /** 1398 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. 1399 * @param USBx USB peripheral instance register address. 1400 * @param bEpNum Endpoint Number. 1401 * @retval None 1402 */ 1403 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \ 1404 do { \ 1405 uint16_t _wRegVal; \ 1406 \ 1407 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ 1408 \ 1409 if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\ 1410 { \ 1411 PCD_RX_DTOG((USBx), (bEpNum)); \ 1412 } \ 1413 } while(0) /* PCD_CLEAR_RX_DTOG */ 1414 1415 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \ 1416 do { \ 1417 uint16_t _wRegVal; \ 1418 \ 1419 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ 1420 \ 1421 if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\ 1422 { \ 1423 PCD_TX_DTOG((USBx), (bEpNum)); \ 1424 } \ 1425 } while(0) /* PCD_CLEAR_TX_DTOG */ 1426 1427 /** 1428 * @brief Sets address in an endpoint register. 1429 * @param USBx USB peripheral instance register address. 1430 * @param bEpNum Endpoint Number. 1431 * @param bAddr Address. 1432 * @retval None 1433 */ 1434 #define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \ 1435 do { \ 1436 uint16_t _wRegVal; \ 1437 \ 1438 _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ 1439 \ 1440 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ 1441 } while(0) /* PCD_SET_EP_ADDRESS */ 1442 1443 /** 1444 * @brief Gets address in an endpoint register. 1445 * @param USBx USB peripheral instance register address. 1446 * @param bEpNum Endpoint Number. 1447 * @retval None 1448 */ 1449 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) 1450 1451 #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) 1452 #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) 1453 1454 /** 1455 * @brief sets address of the tx/rx buffer. 1456 * @param USBx USB peripheral instance register address. 1457 * @param bEpNum Endpoint Number. 1458 * @param wAddr address to be set (must be word aligned). 1459 * @retval None 1460 */ 1461 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \ 1462 do { \ 1463 __IO uint16_t *_wRegVal; \ 1464 uint32_t _wRegBase = (uint32_t)USBx; \ 1465 \ 1466 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 1467 _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ 1468 *_wRegVal = ((wAddr) >> 1) << 1; \ 1469 } while(0) /* PCD_SET_EP_TX_ADDRESS */ 1470 1471 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \ 1472 do { \ 1473 __IO uint16_t *_wRegVal; \ 1474 uint32_t _wRegBase = (uint32_t)USBx; \ 1475 \ 1476 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 1477 _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ 1478 *_wRegVal = ((wAddr) >> 1) << 1; \ 1479 } while(0) /* PCD_SET_EP_RX_ADDRESS */ 1480 1481 /** 1482 * @brief Gets address of the tx/rx buffer. 1483 * @param USBx USB peripheral instance register address. 1484 * @param bEpNum Endpoint Number. 1485 * @retval address of the buffer. 1486 */ 1487 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) 1488 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) 1489 1490 /** 1491 * @brief Sets counter of rx buffer with no. of blocks. 1492 * @param pdwReg Register pointer 1493 * @param wCount Counter. 1494 * @param wNBlocks no. of Blocks. 1495 * @retval None 1496 */ 1497 #define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ 1498 do { \ 1499 (wNBlocks) = (wCount) >> 5; \ 1500 if (((wCount) & 0x1fU) == 0U) \ 1501 { \ 1502 (wNBlocks)--; \ 1503 } \ 1504 *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ 1505 } while(0) /* PCD_CALC_BLK32 */ 1506 1507 #define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ 1508 do { \ 1509 (wNBlocks) = (wCount) >> 1; \ 1510 if (((wCount) & 0x1U) != 0U) \ 1511 { \ 1512 (wNBlocks)++; \ 1513 } \ 1514 *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ 1515 } while(0) /* PCD_CALC_BLK2 */ 1516 1517 #define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ 1518 do { \ 1519 uint32_t wNBlocks; \ 1520 if ((wCount) == 0U) \ 1521 { \ 1522 *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ 1523 *(pdwReg) |= USB_CNTRX_BLSIZE; \ 1524 } \ 1525 else if((wCount) <= 62U) \ 1526 { \ 1527 PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ 1528 } \ 1529 else \ 1530 { \ 1531 PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ 1532 } \ 1533 } while(0) /* PCD_SET_EP_CNT_RX_REG */ 1534 1535 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \ 1536 do { \ 1537 uint32_t _wRegBase = (uint32_t)(USBx); \ 1538 __IO uint16_t *pdwReg; \ 1539 \ 1540 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 1541 pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ 1542 PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ 1543 } while(0) 1544 1545 /** 1546 * @brief sets counter for the tx/rx buffer. 1547 * @param USBx USB peripheral instance register address. 1548 * @param bEpNum Endpoint Number. 1549 * @param wCount Counter value. 1550 * @retval None 1551 */ 1552 #define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \ 1553 do { \ 1554 uint32_t _wRegBase = (uint32_t)(USBx); \ 1555 __IO uint16_t *_wRegVal; \ 1556 \ 1557 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 1558 _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ 1559 *_wRegVal = (uint16_t)(wCount); \ 1560 } while(0) 1561 1562 #define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \ 1563 do { \ 1564 uint32_t _wRegBase = (uint32_t)(USBx); \ 1565 __IO uint16_t *_wRegVal; \ 1566 \ 1567 _wRegBase += (uint32_t)(USBx)->BTABLE; \ 1568 _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ 1569 PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ 1570 } while(0) 1571 1572 /** 1573 * @brief gets counter of the tx buffer. 1574 * @param USBx USB peripheral instance register address. 1575 * @param bEpNum Endpoint Number. 1576 * @retval Counter value 1577 */ 1578 #define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) 1579 #define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) 1580 1581 /** 1582 * @brief Sets buffer 0/1 address in a double buffer endpoint. 1583 * @param USBx USB peripheral instance register address. 1584 * @param bEpNum Endpoint Number. 1585 * @param wBuf0Addr buffer 0 address. 1586 * @retval Counter value 1587 */ 1588 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \ 1589 do { \ 1590 PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ 1591 } while(0) /* PCD_SET_EP_DBUF0_ADDR */ 1592 1593 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \ 1594 do { \ 1595 PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ 1596 } while(0) /* PCD_SET_EP_DBUF1_ADDR */ 1597 1598 /** 1599 * @brief Sets addresses in a double buffer endpoint. 1600 * @param USBx USB peripheral instance register address. 1601 * @param bEpNum Endpoint Number. 1602 * @param wBuf0Addr: buffer 0 address. 1603 * @param wBuf1Addr = buffer 1 address. 1604 * @retval None 1605 */ 1606 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \ 1607 do { \ 1608 PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ 1609 PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ 1610 } while(0) /* PCD_SET_EP_DBUF_ADDR */ 1611 1612 /** 1613 * @brief Gets buffer 0/1 address of a double buffer endpoint. 1614 * @param USBx USB peripheral instance register address. 1615 * @param bEpNum Endpoint Number. 1616 * @retval None 1617 */ 1618 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) 1619 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) 1620 1621 /** 1622 * @brief Gets buffer 0/1 address of a double buffer endpoint. 1623 * @param USBx USB peripheral instance register address. 1624 * @param bEpNum Endpoint Number. 1625 * @param bDir endpoint dir EP_DBUF_OUT = OUT 1626 * EP_DBUF_IN = IN 1627 * @param wCount: Counter value 1628 * @retval None 1629 */ 1630 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \ 1631 do { \ 1632 if ((bDir) == 0U) \ 1633 /* OUT endpoint */ \ 1634 { \ 1635 PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \ 1636 } \ 1637 else \ 1638 { \ 1639 if ((bDir) == 1U) \ 1640 { \ 1641 /* IN endpoint */ \ 1642 PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \ 1643 } \ 1644 } \ 1645 } while(0) /* SetEPDblBuf0Count*/ 1646 1647 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \ 1648 do { \ 1649 uint32_t _wBase = (uint32_t)(USBx); \ 1650 __IO uint16_t *_wEPRegVal; \ 1651 \ 1652 if ((bDir) == 0U) \ 1653 { \ 1654 /* OUT endpoint */ \ 1655 PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \ 1656 } \ 1657 else \ 1658 { \ 1659 if ((bDir) == 1U) \ 1660 { \ 1661 /* IN endpoint */ \ 1662 _wBase += (uint32_t)(USBx)->BTABLE; \ 1663 _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ 1664 *_wEPRegVal = (uint16_t)(wCount); \ 1665 } \ 1666 } \ 1667 } while(0) /* SetEPDblBuf1Count */ 1668 1669 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \ 1670 do { \ 1671 PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ 1672 PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ 1673 } while(0) /* PCD_SET_EP_DBUF_CNT */ 1674 1675 /** 1676 * @brief Gets buffer 0/1 rx/tx counter for double buffering. 1677 * @param USBx USB peripheral instance register address. 1678 * @param bEpNum Endpoint Number. 1679 * @retval None 1680 */ 1681 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) 1682 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) 1683 1684 #endif