1 /** 2 ********************************************************************************* 3 * 4 * @file ald_ebi.h 5 * @brief Header file of EBI module driver. 6 * 7 * @version V1.0 8 * @date 20 Nov 2019 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 20 Nov 2019 AE Team The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 34 #ifndef __ALD_EBI_H__ 35 #define __ALD_EBI_H__ 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 #include "utils.h" 42 43 44 /** @addtogroup ES32FXXX_ALD 45 * @{ 46 */ 47 48 /** @addtogroup EBI 49 * @{ 50 */ 51 52 /** 53 * @defgroup EBI_Public_Macros EBI Public Macros 54 * @{ 55 */ 56 #define EBI_NOR_SRAM_TypeDef EBI_Bank1_TypeDef 57 #define EBI_NOR_SRAM_EXTENDED_TypeDef EBI_Bank1E_TypeDef 58 #define EBI_NAND_TypeDef EBI_Bank2_3_TypeDef 59 #define EBI_LCD_TypeDef EBI_Bank1_LCD_TypeDef 60 #define EBI_NOR_SRAM_DEVICE EBI_Bank1 61 #define EBI_NOR_SRAM_EXTENDED_DEVICE EBI_Bank1E 62 #define EBI_NAND_DEVICE EBI_Bank2_3 63 #define EBI_LCD_DEVICE EBI_Bank1_LCD 64 #define EBI_NAND_BANK2 0x00000010U 65 #define EBI_NAND_BANK3 0x00000100U 66 67 /* PCTRLR register clear mask */ 68 #define PCTRLR_CLEAR_MASK ((uint32_t)(EBI_PCTRLRx_WAITEN_MSK | EBI_PCTRLRx_MEMBKEN_MSK | \ 69 EBI_PCTRLRx_MEMTYP_MSK | EBI_PCTRLRx_DATBUSWID_MSK | \ 70 EBI_PCTRLRx_ECCEN_MSK | EBI_PCTRLRx_CRDLY_MSK | \ 71 EBI_PCTRLRx_ARDLY_MSK | EBI_PCTRLRx_ECCPSIZE_MSK)) 72 73 /* PMEMR register clear mask */ 74 #define PMEMR_CLEAR_MASK ((uint32_t)(EBI_PMEMRx_MEMSETUP_MSK | EBI_PMEMRx_MEMWAIT_MSK | \ 75 EBI_PMEMRx_MEMHOLD_MSK | EBI_PMEMRx_MEMHIZT_MSK)) 76 77 /* PATTR register clear mask */ 78 #define PATTR_CLEAR_MASK ((uint32_t)(EBI_PATTRx_ATTSETUP_MSK | EBI_PATTRx_ATTWAIT_MSK | \ 79 EBI_PATTRx_ATTHOLD_MSK | EBI_PATTRx_ATTHIZT_MSK)) 80 81 /* BCTRLR register clear mask */ 82 #define BCTRLR_CLEAR_MASK ((uint32_t)(EBI_BCTRLRx_FLASHACCEN_MSK | EBI_BCTRLRx_MUXEN_MSK | \ 83 EBI_BCTRLRx_MEMTYP_MSK | EBI_BCTRLRx_MEMWID_MSK | \ 84 EBI_BCTRLRx_BURSTEN_MSK | EBI_BCTRLRx_WAITPOL_MSK | \ 85 EBI_BCTRLRx_WRAPMODE_MSK | EBI_BCTRLRx_WAITCFG_MSK | \ 86 EBI_BCTRLRx_WREN_MSK | EBI_BCTRLRx_WAITEN_MSK | \ 87 EBI_BCTRLRx_EXTMODEN_MSK | EBI_BCTRLRx_ASYNCWAIT_MSK | \ 88 EBI_BCTRLRx_RWCBURSTEN_MSK)) 89 /* BTR register clear mask */ 90 #define BTR_CLEAR_MASK ((uint32_t)(EBI_BTRx_ADDATASETUP_MSK | EBI_BTRx_ADDHOLD_MSK | \ 91 EBI_BTRx_DATAHOLD_MSK | EBI_BTRx_BUSTURN_MSK | \ 92 EBI_BTRx_CLKDIV_MSK | EBI_BTRx_DATALAT_MSK | \ 93 EBI_BTRx_ACCMODE_MSK)) 94 95 /* BWRTR register clear mask */ 96 #define BWTR_CLEAR_MASK ((uint32_t)(EBI_BWRTRx_ADDATASETUP_MSK | EBI_BWRTRx_ADDHOLD_MSK | \ 97 EBI_BWRTRx_DATAHOLD_MSK | EBI_BWRTRx_BUSTURN_MSK | \ 98 EBI_BWRTRx_ACCMODE_MSK)) 99 100 #define LCDCTRL_CLEAR_MASK ((uint32_t)(EBI_LCDCTRLx_HSYNCPOL_POS | EBI_LCDCTRLx_VSYNCPOL_MSK | \ 101 EBI_LCDCTRLx_DENPOL_MSK | EBI_LCDCTRLx_LCDEN_MSK | \ 102 EBI_LCDCTRLx_LCDINT_MSK | EBI_LCDCTRLx_DCLKPOL_MSK | \ 103 EBI_LCDCTRLx_DATASETUP_MSK)) 104 /** 105 * @} 106 */ 107 108 /** @defgroup EBI_Public_Types EBI Public Types 109 * @{ 110 */ 111 112 /** 113 * @brief EBI Access Mode 114 */ 115 typedef enum { 116 EBI_ACCESS_MODE_A = 0x0U, /**< EBI access mode A */ 117 EBI_ACCESS_MODE_B = (0x1U << 28), /**< EBI access mode B */ 118 EBI_ACCESS_MODE_C = (0x2U << 28), /**< EBI access mode C */ 119 EBI_ACCESS_MODE_D = (0x3U << 28), /**< EBI access mode D */ 120 } ebi_access_mode_t; 121 122 /** 123 * @brief EBI NORSRAM Timing parameters structure definition 124 */ 125 typedef struct { 126 uint32_t addr_setup; /**< Address setup HCLK cycles number, the value between 0 and 15 */ 127 uint32_t addr_hold; /**< Address hold HCLK cycles number, the value between 0 and 15 */ 128 uint32_t data_setup; /**< Data setup HCLK cycles number, the value between 1 and 255 */ 129 uint32_t bus_dur; /**< Bus turnaround duration HCLK cycles, the value between 0 and 15 */ 130 uint32_t div; /**< Defines the period of CLK clock signal, the value between 2 and 16 */ 131 uint32_t latency; /**< Issue clock cycles before getting the first data, the value between 2 and 17 */ 132 ebi_access_mode_t mode; /**< Specifies the asynchronous access mode */ 133 } ald_ebi_nor_sram_timing_t; 134 135 /** 136 * @brief EBI_Wait_feature EBI Wait feature 137 */ 138 typedef enum { 139 EBI_NAND_WAIT_FEATURE_DISABLE = 0x0U, /**< NAND wait feature disable */ 140 EBI_NAND_WAIT_FEATURE_ENABLE = (0x1U << 1), /**< NAND wait feature enable */ 141 } ebi_nand_wait_feature_t; 142 143 /** 144 * @brief EBI NAND Data Width 145 */ 146 typedef enum { 147 EBI_NAND_MEM_BUS_WIDTH_8 = 0x0U, /**< NAND mem bus width 8-bits */ 148 EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4), /**< NAND mem bus width 16-bits */ 149 } ebi_nand_mem_bus_width_t; 150 151 /** 152 * @brief EBI NAND ECC STATE 153 */ 154 typedef enum { 155 EBI_NAND_ECC_DISABLE = 0U, /**< NAND ecc disable */ 156 EBI_NAND_ECC_ENABLE = (0x1U << 6), /**< NAND ecc enable */ 157 } ebi_nand_ecc_t; 158 159 /** 160 * @brief EBI ECC Page Size 161 */ 162 typedef enum { 163 EBI_NAND_ECC_PAGE_SIZE_256BYTE = 0U, /**< NAND ecc page size 256 bytes */ 164 EBI_NAND_ECC_PAGE_SIZE_512BYTE = (0x1U << 17), /**< NAND ecc page size 512 bytes */ 165 EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17), /**< NAND ecc page size 1024 bytes */ 166 EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17), /**< NAND ecc page size 2048 bytes */ 167 EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17), /**< NAND ecc page size 4096 bytes */ 168 EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17), /**< NAND ecc page size 8192 bytes */ 169 } ebi_md_ecc_page_size_t; 170 171 /** 172 * @brief EBI NAND Configuration Structure definition 173 */ 174 typedef struct { 175 uint32_t bank; /**< Specifies the NAND memory device that will be used */ 176 ebi_nand_wait_feature_t wait; /**< Enables or disables the Wait feature for the NAND Memory device */ 177 ebi_nand_mem_bus_width_t width; /**< Specifies the external memory device width */ 178 ebi_nand_ecc_t ecc; /**< Enables or disables the ECC computation */ 179 ebi_md_ecc_page_size_t size; /**< Defines the page size for the extended ECC */ 180 uint32_t cle_time; /**< Number of HCLK cycles between CLE low and RE low, the value between 0 and 255 */ 181 uint32_t ale_time; /**< Number of HCLK cycles between ALE low and RE low */ 182 } ald_ebi_nand_init_t; 183 184 /** 185 * @brief EBI NAND Timing parameters structure definition 186 */ 187 typedef struct { 188 uint32_t time; /**< Number of cycles to setup address, the value between 0 and 255 */ 189 uint32_t wait_time; /**< Number of HCLK cycles to assert the command ,the value between 0 and 255 */ 190 uint32_t hold_time; /**< Number of HCLK cycles to hold address or data, the value between 0 and 255 */ 191 uint32_t hiz_time; /**< Number of HCLK cycles data bus is kept in HiZ, the value between 0 and 255 */ 192 } ald_ebi_nand_timing_t; 193 194 /** 195 * @brief EBI Data Address Bus Multiplexing 196 */ 197 typedef enum { 198 EBI_DATA_ADDRESS_MUX_DISABLE = 0x0U, /**< Data address mux disable */ 199 EBI_DATA_ADDRESS_MUX_ENABLE = (0x1U << 1), /**< Data address mux enable */ 200 } ebi_data_address_mux_t; 201 202 /** 203 * @brief EBI NOR/SRAM Bank 204 */ 205 typedef enum { 206 EBI_NORSRAM_BANK1 = 0x0U, /**< Norsram bank 1 */ 207 EBI_NORSRAM_BANK2 = 0x2U, /**< Norsram bank 2 */ 208 EBI_NORSRAM_BANK3 = 0x4U, /**< Norsram bank 3 */ 209 EBI_NORSRAM_BANK4 = 0x6U, /**< Norsram bank 4 */ 210 } ebi_norsram_bank_t; 211 212 /** 213 * @brief EBI Memory Type 214 */ 215 typedef enum { 216 EBI_MEMORY_TYPE_SRAM = 0x0U, /**< Memory tyepe SRAM */ 217 EBI_MEMORY_TYPE_PSRAM = (0x1U << 2), /**< Memory tyepe PSRAM */ 218 EBI_MEMORY_TYPE_NOR = (0x2U << 2), /**< Memory tyepe NOR */ 219 } ebi_memory_type_t; 220 221 /** 222 * @brief EBI NOR/SRAM Data Width 223 */ 224 typedef enum { 225 EBI_NORSRAM_MEM_BUS_WIDTH_8 = 0x0U, /**< Norsram Memory width 8-bits */ 226 EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4), /**< Norsram Memory width 16-bits */ 227 EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4), /**< Norsram Memory width 32-bits */ 228 } ebi_norsram_mem_bus_width_t; 229 230 /** 231 * @brief EBI NOR/SRAM Flash Access 232 */ 233 typedef enum { 234 EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0U, /**< Norsram flash access disable */ 235 EBI_NORSRAM_FLASH_ACCESS_ENABLE = (0x1U << 6), /**< Norsram flash access enable */ 236 } ebi_norsram_flash_access_t; 237 238 /** 239 * @brief EBI Burst Access Mode 240 */ 241 typedef enum { 242 EBI_BURST_ACCESS_MODE_DISABLE = 0x0U, /**< Burst access disable */ 243 EBI_BURST_ACCESS_MODE_ENABLE = (0x1U << 8), /**< Burst access enable */ 244 } ebi_burst_access_mode_t; 245 246 /** 247 * @brief EBI Wait Signal Polarity 248 */ 249 typedef enum { 250 EBI_WAIT_SIGNAL_POLARITY_LOW = 0x0U, /**< Wait signal polarity low */ 251 EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9), /**< Wait signal polarity high */ 252 } ebi_wait_signal_polarity_t; 253 254 /** 255 * @brief EBI Wrap Mode 256 */ 257 typedef enum { 258 EBI_WRAP_MODE_DISABLE = 0x0U, /**< Wrap mode disable */ 259 EBI_WRAP_MODE_ENABLE = (0x1U << 10), /**< Wrap mode enable */ 260 } ebi_wrap_mode_t; 261 262 /** 263 * @brief EBI Wait Timing 264 */ 265 typedef enum { 266 EBI_WAIT_TIMING_BEFORE_WS = 0x0U, /**< Wait timing before ws */ 267 EBI_WAIT_TIMING_DURING_WS = (0x1U << 11), /**< Wait timing during ws */ 268 } ebi_wait_timing_t; 269 270 /** 271 * @brief EBI Write Operation State 272 */ 273 typedef enum { 274 EBI_WRITE_OPERATION_DISABLE = 0x0U, /**< Write operation disable */ 275 EBI_WRITE_OPERATION_ENABLE = (0x1U << 12), /**< Write operation enable */ 276 } ebi_write_operation_t; 277 278 /** 279 * @brief EBI Wait Signal 280 */ 281 typedef enum { 282 EBI_WAIT_SIGNAL_DISABLE = 0x0U, /**< Wait signal disable */ 283 EBI_WAIT_SIGNAL_ENABLE = (0x1U << 13), /**< Wait signal enable */ 284 } ebi_wait_signal_t; 285 286 /** 287 * @brief EBI Extended Mode 288 */ 289 typedef enum { 290 EBI_EXTENDED_MODE_DISABLE = 0x0U, /**< EBI extended mode disable */ 291 EBI_EXTENDED_MODE_ENABLE = (0x1U << 14), /**< EBI extended mode enable */ 292 } ebi_extended_mode_t; 293 294 /** 295 * @brief EBI Asynchronous Wait 296 */ 297 typedef enum { 298 EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0U, /**< Asynchronous wait disable */ 299 EBI_ASYNCHRONOUS_WAIT_ENABLE = (0x1U << 15), /**< Asynchronous wait enable */ 300 } ebi_asynchronous_wait_t; 301 302 /** 303 * @brief EBI Write Burst 304 */ 305 typedef enum { 306 EBI_WRITE_BURST_DISABLE = 0x0U, /**< Write burst disable */ 307 EBI_WRITE_BURST_ENABLE = (0x1U << 19), /**< Write burst enable */ 308 } ebi_write_burst_t; 309 310 /** 311 * @brief EBI PCR Memory Type 312 */ 313 typedef enum { 314 EBI_PCTRLR_MEMORY_TYPE_None = 0x0U, /**< PCR memory type none */ 315 EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3), /**< PCR memory type nand */ 316 } ebi_pctrlr_memory_type_t; 317 318 /** 319 * @brief EBI Interrupt definition 320 */ 321 typedef enum { 322 EBI_IT_RISING_EDGE = (1U << 3), /**< Rising edge trigger interrupt */ 323 EBI_IT_LEVEL = (1U << 4), /**< Level trigger interrupt */ 324 EBI_IT_FALLING_EDGE = (1U << 5), /**< Falling edge trigger interrupt */ 325 } ebi_it_t; 326 327 /** 328 * @brief EBI Flag definition 329 */ 330 typedef enum { 331 EBI_FLAG_RISING_EDGE = (1U << 0), /**< Rising edge flag */ 332 EBI_FLAG_LEVEL = (1U << 1), /**< Level flag */ 333 EBI_FLAG_FALLING_EDGE = (1U << 2), /**< Falling edge flag */ 334 EBI_FLAG_FEMPT = (1U << 6), /**< Rising edge trigger interrupt */ 335 } ebi_flag_t; 336 337 /** 338 * @brief EBI LCD_Horizontal Synch Polarity definition 339 */ 340 typedef enum { 341 EBI_LCD_HSYNCPOL_LOW = 0x0U, /**< Horizontal synch polarity low */ 342 EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29), /**< Horizontal synch polarity high */ 343 } ebi_lcd_hsyncpol_t; 344 345 /** 346 * @brief EBI LCD Vertical Synch Polarity definition 347 */ 348 typedef enum { 349 EBI_LCD_VSYNCPOL_LOW = 0x0U, /**< Vertical synch polarity low */ 350 EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28), /**< Vertical synch polarity high */ 351 } ebi_lcd_vsyncpol_t; 352 353 /** 354 * @brief EBI LCD Data Enable Polarity definition 355 */ 356 typedef enum { 357 EBI_LCD_DENPOL_LOW = 0x0U, /**< LCD data enable polarity low */ 358 EBI_LCD_DENPOL_HIGH = (0x1U << 27), /**< LCD data enable polarity high */ 359 } ebi_lcd_denpol_t; 360 361 /** 362 * @brief EBI LCD Enable definition 363 */ 364 typedef enum { 365 EBI_LCD_LCDEN_DISABLE = 0x0U, /**< LCD disable */ 366 EBI_LCD_LCDEN_ENABLE = (0x1U << 26), /**< LCD data enable polarity low */ 367 } ebi_lcd_lcden_t; 368 369 /** 370 * @brief EBI LCD Init Enable definition 371 */ 372 typedef enum { 373 EBI_LCD_LCDINT_DISABLE = 0x0U, /**< LCD init disable */ 374 EBI_LCD_LCDINT_ENABLE = (0x1 << 25), /**< LCD init enable */ 375 } ebi_lcd_lcdint_t; 376 377 /** 378 * @brief EBI LCD Data Clock definition 379 */ 380 typedef enum { 381 EBI_LCD_DCLKPOL_FALLING = 0x0U, /**< LCD data clock falling edge */ 382 EBI_LCD_DCLKPOL_RISING = (0x1U << 24), /**< LCD data clock rising edge */ 383 } ebi_lcd_dclkpol_t; 384 385 /** 386 * @brief EBI LCD parameters structure definition 387 */ 388 typedef struct { 389 uint8_t bank; /**< Specifies the NORSRAM memory device */ 390 ebi_lcd_hsyncpol_t h_polarity; /**< Horizontal sync polarity */ 391 ebi_lcd_vsyncpol_t v_polarity; /**< Vertical sync polarity */ 392 ebi_lcd_denpol_t data_polarity; /**< Data enable polarity */ 393 ebi_lcd_lcden_t enable; /**< LCD enable */ 394 ebi_lcd_dclkpol_t clk_polarity; /**< Data clock polarity */ 395 ebi_lcd_lcdint_t reset; /**< LCD Reset */ 396 uint8_t setup; /**< Data setup time */ 397 uint8_t v_width; /**< Vsync pulse width */ 398 uint8_t h_width; /**< Hsync puluse width */ 399 uint16_t nr_line; /**< Frame line number */ 400 uint16_t nr_pixel; /**< Frame pixel number */ 401 } ebi_lcd_init_t; 402 403 /** 404 * @brief NOR LCD handle Structure definition 405 */ 406 typedef struct { 407 EBI_LCD_TypeDef *inst; 408 ebi_lcd_init_t init; 409 } ebi_lcd_handle_t; 410 411 /** 412 * @brief EBI NORSRAM Configuration Structure definition 413 */ 414 typedef struct { 415 uint32_t bank; /**< Specifies the NORSRAM memory device, the value can be one of 0 ~ 3 */ 416 ebi_data_address_mux_t mux; /**< Address and data values are multiplexed or not */ 417 ebi_memory_type_t type; /**< Specifies the type of external memory */ 418 ebi_norsram_mem_bus_width_t width; /**< Specifies the external memory device width */ 419 ebi_burst_access_mode_t acc_mode; /**< Enables or disables the burst access mode for Flash memory */ 420 ebi_wait_signal_polarity_t polarity; /**< Wait signal polarity, valid only in burst mode */ 421 ebi_wrap_mode_t wrap_mode; /**< Enables or disables the Wrapped burst access mode, only in burst mode */ 422 ebi_wait_timing_t active; /**< Specifies if the wait signal is asserted, only in burst mode */ 423 ebi_write_operation_t write; /**< Enables or disables the write operation */ 424 ebi_wait_signal_t signal; /**< Enables or disables the wait state insertion, only in burst mode */ 425 ebi_extended_mode_t ext_mode; /**< Enables or disables the extended mode */ 426 ebi_asynchronous_wait_t wait; /**< Enables or disables wait signal during asynchronous transfers */ 427 ebi_write_burst_t burst; /**< Enables or disables the write burst operation */ 428 } ald_ebi_nor_sram_init_t; 429 430 /** 431 * @} 432 */ 433 434 /** @defgroup EBI_Private_Macros EBI Private Macros 435 * @{ 436 */ 437 #define IS_EBI_NORSRAM_BANK(x) (((x) == EBI_NORSRAM_BANK1) || \ 438 ((x) == EBI_NORSRAM_BANK2) || \ 439 ((x) == EBI_NORSRAM_BANK3) || \ 440 ((x) == EBI_NORSRAM_BANK4)) 441 #define IS_EBI_MUX(x) (((x) == EBI_DATA_ADDRESS_MUX_DISABLE) || \ 442 ((x) == EBI_DATA_ADDRESS_MUX_ENABLE)) 443 #define IS_EBI_MEMORY(x) (((x) == EBI_MEMORY_TYPE_SRAM) || \ 444 ((x) == EBI_MEMORY_TYPE_PSRAM) || \ 445 ((x) == EBI_MEMORY_TYPE_NOR)) 446 #define IS_EBI_NORSRAM_MEMORY_WIDTH(x) (((x) == EBI_NORSRAM_MEM_BUS_WIDTH_8) || \ 447 ((x) == EBI_NORSRAM_MEM_BUS_WIDTH_16) || \ 448 ((x) == EBI_NORSRAM_MEM_BUS_WIDTH_32)) 449 #define IS_EBI_WRITE_BURST(x) (((x) == EBI_WRITE_BURST_DISABLE) || \ 450 ((x) == EBI_WRITE_BURST_ENABLE)) 451 #define IS_EBI_ACCESS_MODE(x) (((x) == EBI_ACCESS_MODE_A) || \ 452 ((x) == EBI_ACCESS_MODE_B) || \ 453 ((x) == EBI_ACCESS_MODE_C) || \ 454 ((x) == EBI_ACCESS_MODE_D)) 455 #define IS_EBI_NAND_BANK(x) (((x) == EBI_NAND_BANK2) || \ 456 ((x) == EBI_NAND_BANK3)) 457 #define IS_EBI_WAIT_FEATURE(x) (((x) == EBI_NAND_WAIT_FEATURE_DISABLE) || \ 458 ((x) == EBI_NAND_WAIT_FEATURE_ENABLE)) 459 #define IS_EBI_NAND_MEMORY_WIDTH(x) (((x) == EBI_NAND_MEM_BUS_WIDTH_8) || \ 460 ((x) == EBI_NAND_MEM_BUS_WIDTH_16)) 461 #define IS_EBI_ECC_STATE(x) (((x) == EBI_NAND_ECC_DISABLE) || \ 462 ((x) == EBI_NAND_ECC_ENABLE)) 463 #define IS_EBI_ECCPAGE_SIZE(x) (((x) == EBI_NAND_ECC_PAGE_SIZE_256BYTE) || \ 464 ((x) == EBI_NAND_ECC_PAGE_SIZE_512BYTE) || \ 465 ((x) == EBI_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 466 ((x) == EBI_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 467 ((x) == EBI_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 468 ((x) == EBI_NAND_ECC_PAGE_SIZE_8192BYTE)) 469 #define IS_EBI_LCD_DEVICE(x) ((x) == EBI_LCD_DEVICE) 470 #define IS_EBI_HORIZONTAL_SYNCH(x) (((x) == EBI_LCD_HSYNCPOL_LOW) || \ 471 ((x) == EBI_LCD_HSYNCPOL_HIGH)) 472 #define IS_EBI_VERTICAL_SYNCH(x) (((x) == EBI_LCD_VSYNCPOL_LOW) || \ 473 ((x) == EBI_LCD_VSYNCPOL_HIGH)) 474 #define IS_EBI_DATA_ENABLE(x) (((x) == EBI_LCD_DENPOL_LOW) || \ 475 ((x) == EBI_LCD_DENPOL_HIGH)) 476 #define IS_EBI_LCD_ENABLE(x) (((x) == EBI_LCD_LCDEN_DISABLE) || \ 477 ((x) == EBI_LCD_LCDEN_ENABLE)) 478 #define IS_EBI_LCD_RESET(x) (((x) == EBI_LCD_LCDINT_DISABLE) || \ 479 ((x) == EBI_LCD_LCDINT_ENABLE)) 480 #define IS_EBI_DATA_CLOCK(x) (((x) == EBI_LCD_DCLKPOL_FALLING) || \ 481 ((x) == EBI_LCD_DCLKPOL_RISING)) 482 #define IS_EBI_LCD_DATASETUP_TIME(x) ((x) < 255U) 483 #define IS_EBI_HYSNC_PULSE_WIDTH(x) ((x) < 255U) 484 #define IS_EBI_VSYNC_PULSE_WIDTH(x) ((x) < 255U) 485 #define IS_EBI_FRAME_LINE_NUMBER(x) (((x) >= 1U) && ((x) < 65535)) 486 #define IS_EBI_FRAME_PIXEL_NUMBER(x) (((x) >= 1U) && ((x) < 65535)) 487 488 #define IS_EBI_TCLR_TIME(x) ((x) <= 255U) 489 #define IS_EBI_TAR_TIME(x) ((x) <= 255U) 490 #define IS_EBI_SETUP_TIME(x) ((x) <= 255U) 491 #define IS_EBI_WAIT_TIME(x) ((x) <= 255U) 492 #define IS_EBI_HOLD_TIME(x) ((x) <= 255U) 493 #define IS_EBI_HIZ_TIME(x) ((x) <= 255U) 494 #define IS_EBI_NORSRAM_DEVICE(x) ((x) == EBI_NOR_SRAM_DEVICE) 495 #define IS_EBI_NORSRAM_EXTENDED_DEVICE(x) ((x) == EBI_NOR_SRAM_EXTENDED_DEVICE) 496 #define IS_EBI_NAND_DEVICE(x) ((x) == EBI_NAND_DEVICE) 497 #define IS_EBI_BURSTMODE(x) (((x) == EBI_BURST_ACCESS_MODE_DISABLE) || \ 498 ((x) == EBI_BURST_ACCESS_MODE_ENABLE)) 499 #define IS_EBI_WAIT_POLARITY(x) (((x) == EBI_WAIT_SIGNAL_POLARITY_LOW) || \ 500 ((x) == EBI_WAIT_SIGNAL_POLARITY_HIGH)) 501 #define IS_EBI_WRAP_MODE(x) (((x) == EBI_WRAP_MODE_DISABLE) || \ 502 ((x) == EBI_WRAP_MODE_ENABLE)) 503 #define IS_EBI_WAIT_SIGNAL_ACTIVE(x) (((x) == EBI_WAIT_TIMING_BEFORE_WS) || \ 504 ((x) == EBI_WAIT_TIMING_DURING_WS)) 505 #define IS_EBI_WRITE_OPERATION(x) (((x) == EBI_WRITE_OPERATION_DISABLE) || \ 506 ((x) == EBI_WRITE_OPERATION_ENABLE)) 507 #define IS_EBI_WAITE_SIGNAL(x) (((x) == EBI_WAIT_SIGNAL_DISABLE) || \ 508 ((x) == EBI_WAIT_SIGNAL_ENABLE)) 509 #define IS_EBI_EXTENDED_MODE(x) (((x) == EBI_EXTENDED_MODE_DISABLE) || \ 510 ((x) == EBI_EXTENDED_MODE_ENABLE)) 511 #define IS_EBI_ASYNWAIT(x) (((x) == EBI_ASYNCHRONOUS_WAIT_DISABLE) || \ 512 ((x) == EBI_ASYNCHRONOUS_WAIT_ENABLE)) 513 #define IS_EBI_CLK_DIV(x) (((x) >= 1U) && ((x) <= 16U)) 514 #define IS_EBI_DATA_LATENCY(x) (((x) >= 1U) && ((x) <= 17U)) 515 #define IS_EBI_ADDRESS_SETUP_TIME(x) ((x) <= 15U) 516 #define IS_EBI_ADDRESS_HOLD_TIME(x) (((x) > 0U) && ((x) <= 15U)) 517 #define IS_EBI_DATASETUP_TIME(x) (((x) > 0U) && ((x) <= 255U)) 518 #define IS_EBI_TURNAROUND_TIME(x) ((x) <= 15U) 519 #define IS_EBI_BANK_NUMBER(x) (((x) > 0U) && ((x) <= 4U)) 520 /** 521 * @} 522 */ 523 524 /** @addtogroup EBI_Public_Functions 525 * @{ 526 */ 527 528 /** @addtogroup EBI_Public_Functions_Group1 529 * @{ 530 */ 531 /* NOR-FLASH SRAM initialize functions */ 532 void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init); 533 void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank); 534 void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode); 535 ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank); 536 /** 537 * @} 538 */ 539 540 /** @addtogroup EBI_Public_Functions_Group2 541 * @{ 542 */ 543 /* NOR/SRAM Control functions */ 544 void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); 545 void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); 546 void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); 547 void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); 548 /** 549 * @} 550 */ 551 552 /** @addtogroup EBI_Public_Functions_Group3 553 * @{ 554 */ 555 /* NAND-FLASH initialize functions */ 556 void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init); 557 void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank); 558 void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank); 559 void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank); 560 /** 561 * @} 562 */ 563 564 /** @addtogroup EBI_Public_Functions_Group4 565 * @{ 566 */ 567 /* NAND-FLASH control functions */ 568 void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank); 569 void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank); 570 void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it); 571 void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it); 572 void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank); 573 void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank); 574 ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout); 575 flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag); 576 void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag); 577 /** 578 * @} 579 */ 580 581 /** @addtogroup EBI_Public_Functions_Group5 582 * @{ 583 */ 584 void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd); 585 void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd); 586 /** 587 * @} 588 */ 589 /** 590 * @} 591 */ 592 /** 593 * @} 594 */ 595 /** 596 * @} 597 */ 598 #ifdef __cplusplus 599 } 600 #endif 601 602 #endif /* __ALD_EBI_H__ */ 603