1 /**
2 ******************************************************************************
3 * @file hk32f0xx_syscfg.c
4 * @version V1.0.1
5 * @date 2019-08-15
6 ===============================================================================
7 ##### How to use this driver #####
8 ===============================================================================
9 [..]
10 The SYSCFG registers can be accessed only when the SYSCFG
11 interface APB clock is enabled.
12 To enable SYSCFG APB clock use:
13 RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
14 * @endverbatim
15 *
16 ******************************************************************************
17 */
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "hk32f0xx_syscfg.h"
21
22 /** @addtogroup HK32F0xx_StdPeriph_Driver
23 * @{
24 */
25
26 /** @defgroup SYSCFG
27 * @brief SYSCFG driver modules
28 * @{
29 */
30
31 /* Private typedef -----------------------------------------------------------*/
32 /* Private define ------------------------------------------------------------*/
33 /* Private macro -------------------------------------------------------------*/
34 /* Private variables ---------------------------------------------------------*/
35 /* Private function prototypes -----------------------------------------------*/
36 /* Private functions ---------------------------------------------------------*/
37
38 /** @defgroup SYSCFG_Private_Functions
39 * @{
40 */
41
42 /** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
43 * @brief SYSCFG Initialization and Configuration functions
44 *
45 @verbatim
46 ===============================================================================
47 ##### SYSCFG Initialization and Configuration functions #####
48 ===============================================================================
49
50 @endverbatim
51 * @{
52 */
53
54 /**
55 * @brief Deinitializes the SYSCFG registers to their default reset values.
56 * @param None
57 * @retval None
58 * @note MEM_MODE bits are not affected by APB reset.
59 * @note MEM_MODE bits took the value from the user option bytes.
60 * @note CFGR2 register is not affected by APB reset.
61 * @note CLABBB configuration bits are locked when set.
62 * @note To unlock the configuration, perform a system reset.
63 */
SYSCFG_DeInit(void)64 void SYSCFG_DeInit(void)
65 {
66 /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
67 SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
68 /* Set EXTICRx registers to reset value */
69 SYSCFG->EXTICR[0] = 0;
70 SYSCFG->EXTICR[1] = 0;
71 SYSCFG->EXTICR[2] = 0;
72 SYSCFG->EXTICR[3] = 0;
73 /* Set CFGR2 register to reset value: clear SRAM parity error flag */
74 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE;
75 }
76
77 /**
78 * @brief Configures the memory mapping at address 0x00000000.
79 * @param SYSCFG_MemoryRemap: selects the memory remapping.
80 * This parameter can be one of the following values:
81 * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
82 * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
83 * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
84 * @retval None
85 */
SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)86 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
87 {
88 uint32_t tmpctrl = 0;
89
90 /* Check the parameter */
91 assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
92
93 /* Get CFGR1 register value */
94 tmpctrl = SYSCFG->CFGR1;
95
96 /* Clear MEM_MODE bits */
97 tmpctrl &= (uint32_t)(~SYSCFG_CFGR1_MEM_MODE);
98
99 /* Set the new MEM_MODE bits value */
100 tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
101
102 /* Set CFGR1 register with the new memory remap configuration */
103 SYSCFG->CFGR1 = tmpctrl;
104 }
105
106 /**
107 * @brief Configure the DMA channels remapping.
108 * @param SYSCFG_DMARemap: selects the DMA channels remap.
109 * This parameter can be one of the following values:
110 * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
111 * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
112 * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
113 * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
114 * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
115 * @param NewState: new state of the DMA channel remapping.
116 * This parameter can be: ENABLE or DISABLE.
117 * @note When enabled, DMA channel of the selected peripheral is remapped
118 * @note When disabled, Default DMA channel is mapped to the selected peripheral
119 * @note By default TIM17 DMA requests is mapped to channel 1,
120 * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
121 * TIM17 DMA requests to channel 2 and use
122 * SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
123 * TIM17 DMA requests to channel 1 (default mapping)
124 * @note This function is only used for HK32F030, HK32F031, devices.
125 * @retval None
126 */
SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap,FunctionalState NewState)127 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
128 {
129 /* Check the parameters */
130 assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
131 assert_param(IS_FUNCTIONAL_STATE(NewState));
132
133 if (NewState != DISABLE)
134 {
135 /* Remap the DMA channel */
136 SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
137 }
138 else
139 {
140 /* use the default DMA channel mapping */
141 SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
142 }
143 }
144
145 /**
146 * @brief Configure the I2C fast mode plus driving capability.
147 * @param SYSCFG_I2CFastModePlus: selects the pin.
148 * This parameter can be one of the following values:
149 * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
150 * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
151 * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
152 * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
153 * @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9
154 * @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10
155 * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C_Pxx_FM bits
156 *
157 * @param NewState: new state of the DMA channel remapping.
158 * This parameter can be: ENABLE or DISABLE.
159 * @note ENABLE: Enable fast mode plus driving capability for selected I2C pin
160 * @note DISABLE: Disable fast mode plus driving capability for selected I2C pin
161 * @note For I2C1, fast mode plus driving capability can be enabled on all selected
162 * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
163 * on each one of the following pins PB6, PB7, PB8 and PB9.
164 * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
165 * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
166 * @note For all I2C2 pins fast mode plus driving capability can be enabled
167 * only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
168 * @retval None
169 */
SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus,FunctionalState NewState)170 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
171 {
172 /* Check the parameters */
173 assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
174 assert_param(IS_FUNCTIONAL_STATE(NewState));
175
176 if (NewState != DISABLE)
177 {
178 /* Enable fast mode plus driving capability for selected pin */
179 SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
180 }
181 else
182 {
183 /* Disable fast mode plus driving capability for selected pin */
184 SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
185 }
186 }
187
188
189 /**
190 * @brief Selects the GPIO pin used as EXTI Line.
191 * @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
192 * for EXTI lines where x can be (A, B, C, D, or F).
193 * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
194 * @note This parameter can be EXTI_PinSourcex where x can be:
195 * For HK32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
196 * For HK32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
197 * @retval None
198 */
SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx,uint8_t EXTI_PinSourcex)199 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
200 {
201 uint32_t tmp = 0x00;
202
203 /* Check the parameters */
204 assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
205 assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
206
207 tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
208 SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
209 SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
210 }
211
212 /**
213 * @brief check ISR wrapper: Allow to determine interrupt source per line .
214 * @param IT_Source: specifies the interrupt source to check.
215 * This parameter can be one of the following values:
216 * @arg ITLINE_EWDG EWDG has expired
217 * @arg ITLINE_PVDOUT Power voltage detection Interrupt
218 * @arg ITLINE_VDDIO2 VDDIO2 Interrupt
219 * @arg ITLINE_RTC_WAKEUP RTC WAKEUP -> exti[20] Interrupt
220 * @arg ITLINE_RTC_TSTAMP RTC Time Stamp -> exti[19] interrupt
221 * @arg ITLINE_RTC_ALRA RTC Alarm -> exti[17] interrupt
222 * @arg ITLINE_FLASH_ITF Flash ITF Interrupt
223 * @arg ITLINE_CRS CRS Interrupt
224 * @arg ITLINE_CLK_CTRL CLK Control Interrupt
225 * @arg ITLINE_EXTI0 External Interrupt 0
226 * @arg ITLINE_EXTI1 External Interrupt 1
227 * @arg ITLINE_EXTI2 External Interrupt 2
228 * @arg ITLINE_EXTI3 External Interrupt 3
229 * @arg ITLINE_EXTI4 External Interrupt 4
230 * @arg ITLINE_EXTI5 External Interrupt 5
231 * @arg ITLINE_EXTI6 External Interrupt 6
232 * @arg ITLINE_EXTI7 External Interrupt 7
233 * @arg ITLINE_EXTI8 External Interrupt 8
234 * @arg ITLINE_EXTI9 External Interrupt 9
235 * @arg ITLINE_EXTI10 External Interrupt 10
236 * @arg ITLINE_EXTI11 External Interrupt 11
237 * @arg ITLINE_EXTI12 External Interrupt 12
238 * @arg ITLINE_EXTI13 External Interrupt 13
239 * @arg ITLINE_EXTI14 External Interrupt 14
240 * @arg ITLINE_EXTI15 External Interrupt 15
241 * @arg ITLINE_TSC_EOA Touch control EOA Interrupt
242 * @arg ITLINE_TSC_MCE Touch control MCE Interrupt
243 * @arg ITLINE_DMA1_CH1 DMA1 Channel 1 Interrupt
244 * @arg ITLINE_DMA1_CH2 DMA1 Channel 2 Interrupt
245 * @arg ITLINE_DMA1_CH3 DMA1 Channel 3 Interrupt
246 * @arg ITLINE_DMA2_CH1 DMA2 Channel 1 Interrupt
247 * @arg ITLINE_DMA2_CH2 DMA2 Channel 2 Interrupt
248 * @arg ITLINE_DMA1_CH4 DMA1 Channel 4 Interrupt
249 * @arg ITLINE_DMA1_CH5 DMA1 Channel 5 Interrupt
250 * @arg ITLINE_DMA1_CH6 DMA1 Channel 6 Interrupt
251 * @arg ITLINE_DMA1_CH7 DMA1 Channel 7 Interrupt
252 * @arg ITLINE_DMA2_CH3 DMA2 Channel 3 Interrupt
253 * @arg ITLINE_DMA2_CH4 DMA2 Channel 4 Interrupt
254 * @arg ITLINE_DMA2_CH5 DMA2 Channel 5 Interrupt
255 * @arg ITLINE_ADC ADC Interrupt
256 * @arg ITLINE_COMP1 COMP1 Interrupt -> exti[21]
257 * @arg ITLINE_COMP2 COMP2 Interrupt -> exti[21]
258 * @arg ITLINE_TIM1_BRK TIM1 BRK Interrupt
259 * @arg ITLINE_TIM1_UPD TIM1 UPD Interrupt
260 * @arg ITLINE_TIM1_TRG TIM1 TRG Interrupt
261 * @arg ITLINE_TIM1_CCU TIM1 CCU Interrupt
262 * @arg ITLINE_TIM1_CC TIM1 CC Interrupt
263 * @arg ITLINE_TIM2 TIM2 Interrupt
264 * @arg ITLINE_TIM3 TIM3 Interrupt
265 * @arg ITLINE_DAC DAC Interrupt
266 * @arg ITLINE_TIM6 TIM6 Interrupt
267 * @arg ITLINE_TIM7 TIM7 Interrupt
268 * @arg ITLINE_TIM14 TIM14 Interrupt
269 * @arg ITLINE_TIM15 TIM15 Interrupt
270 * @arg ITLINE_TIM16 TIM16 Interrupt
271 * @arg ITLINE_TIM17 TIM17 Interrupt
272 * @arg ITLINE_I2C1 I2C1 Interrupt -> exti[23]
273 * @arg ITLINE_I2C2 I2C2 Interrupt
274 * @arg ITLINE_SPI1 I2C1 Interrupt -> exti[23]
275 * @arg ITLINE_SPI2 SPI1 Interrupt
276 * @arg ITLINE_USART1 USART1 GLB Interrupt -> exti[25]
277 * @arg ITLINE_USART2 USART2 GLB Interrupt -> exti[26]
278 * @arg ITLINE_USART3 USART3 Interrupt
279 * @arg ITLINE_USART4 USART4 Interrupt
280 * @arg ITLINE_USART5 USART5 Interrupt
281 * @arg ITLINE_USART6 USART6 Interrupt
282 * @arg ITLINE_USART7 USART7 Interrupt
283 * @arg ITLINE_USART8 USART8 Interrupt
284 * @arg ITLINE_CAN CAN Interrupt
285 * @arg ITLINE_CEC CEC Interrupt
286 * @retval The new state of IT_LINE_SR.
287 */
SYSCFG_GetPendingIT(uint32_t ITSourceLine)288 uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine)
289 {
290 assert_param(IS_SYSCFG_ITLINE(ITSourceLine));
291 return (SYSCFG->IT_LINE_SR[(ITSourceLine >> 0x18)] & (ITSourceLine & 0x00FFFFFF));
292 }
293
294 /**
295 * @brief Connect the selected parameter to the break input of TIM1.
296 * @note The selected configuration is locked and can be unlocked by system reset
297 * @param SYSCFG_Break: selects the configuration to be connected to break
298 * input of TIM1
299 * This parameter can be any combination of the following values:
300 * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1,, not available for HK32F030 devices.
301 * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
302 * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
303 * @retval None
304 */
SYSCFG_BreakConfig(uint32_t SYSCFG_Break)305 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
306 {
307 /* Check the parameter */
308 assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
309
310 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
311 }
312
313 /**
314 * @brief Checks whether the specified SYSCFG flag is set or not.
315 * @param SYSCFG_Flag: specifies the SYSCFG flag to check.
316 * This parameter can be one of the following values:
317 * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
318 * @retval The new state of SYSCFG_Flag (SET or RESET).
319 */
SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)320 FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
321 {
322 FlagStatus bitstatus = RESET;
323
324 /* Check the parameter */
325 assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
326
327 /* Check the status of the specified SPI flag */
328 if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
329 {
330 /* SYSCFG_Flag is set */
331 bitstatus = SET;
332 }
333 else
334 {
335 /* SYSCFG_Flag is reset */
336 bitstatus = RESET;
337 }
338 /* Return the SYSCFG_Flag status */
339 return bitstatus;
340 }
341
342 /**
343 * @brief Clear the selected SYSCFG flag.
344 * @param SYSCFG_Flag: selects the flag to be cleared.
345 * This parameter can be any combination of the following values:
346 * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
347 * @retval None
348 */
SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)349 void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
350 {
351 /* Check the parameter */
352 assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
353
354 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
355 }
356
357 /**
358 * @}
359 */
360
361 /**
362 * @}
363 */
364
365 /**
366 * @}
367 */
368
369 /**
370 * @}
371 */
372