1 /** 2 ****************************************************************************** 3 * @file l1c_reg.h 4 * @version V1.2 5 * @date 2020-07-08 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __L1C_REG_H__ 37 #define __L1C_REG_H__ 38 39 #include "bl702.h" 40 41 /* 0x0 : l1c_config */ 42 #define L1C_CONFIG_OFFSET (0x0) 43 #define L1C_CACHEABLE L1C_CACHEABLE 44 #define L1C_CACHEABLE_POS (0U) 45 #define L1C_CACHEABLE_LEN (1U) 46 #define L1C_CACHEABLE_MSK (((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS) 47 #define L1C_CACHEABLE_UMSK (~(((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS)) 48 #define L1C_CNT_EN L1C_CNT_EN 49 #define L1C_CNT_EN_POS (1U) 50 #define L1C_CNT_EN_LEN (1U) 51 #define L1C_CNT_EN_MSK (((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS) 52 #define L1C_CNT_EN_UMSK (~(((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS)) 53 #define L1C_INVALID_EN L1C_INVALID_EN 54 #define L1C_INVALID_EN_POS (2U) 55 #define L1C_INVALID_EN_LEN (1U) 56 #define L1C_INVALID_EN_MSK (((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS) 57 #define L1C_INVALID_EN_UMSK (~(((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS)) 58 #define L1C_INVALID_DONE L1C_INVALID_DONE 59 #define L1C_INVALID_DONE_POS (3U) 60 #define L1C_INVALID_DONE_LEN (1U) 61 #define L1C_INVALID_DONE_MSK (((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS) 62 #define L1C_INVALID_DONE_UMSK (~(((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS)) 63 #define L1C_WT_EN L1C_WT_EN 64 #define L1C_WT_EN_POS (4U) 65 #define L1C_WT_EN_LEN (1U) 66 #define L1C_WT_EN_MSK (((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS) 67 #define L1C_WT_EN_UMSK (~(((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS)) 68 #define L1C_WB_EN L1C_WB_EN 69 #define L1C_WB_EN_POS (5U) 70 #define L1C_WB_EN_LEN (1U) 71 #define L1C_WB_EN_MSK (((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS) 72 #define L1C_WB_EN_UMSK (~(((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS)) 73 #define L1C_WA_EN L1C_WA_EN 74 #define L1C_WA_EN_POS (6U) 75 #define L1C_WA_EN_LEN (1U) 76 #define L1C_WA_EN_MSK (((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS) 77 #define L1C_WA_EN_UMSK (~(((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS)) 78 #define L1C_RANDOM_REPLACE L1C_RANDOM_REPLACE 79 #define L1C_RANDOM_REPLACE_POS (7U) 80 #define L1C_RANDOM_REPLACE_LEN (1U) 81 #define L1C_RANDOM_REPLACE_MSK (((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS) 82 #define L1C_RANDOM_REPLACE_UMSK (~(((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS)) 83 #define L1C_WAY_DIS L1C_WAY_DIS 84 #define L1C_WAY_DIS_POS (8U) 85 #define L1C_WAY_DIS_LEN (4U) 86 #define L1C_WAY_DIS_MSK (((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS) 87 #define L1C_WAY_DIS_UMSK (~(((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS)) 88 #define L1C_IROM_2T_ACCESS L1C_IROM_2T_ACCESS 89 #define L1C_IROM_2T_ACCESS_POS (12U) 90 #define L1C_IROM_2T_ACCESS_LEN (1U) 91 #define L1C_IROM_2T_ACCESS_MSK (((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS) 92 #define L1C_IROM_2T_ACCESS_UMSK (~(((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS)) 93 #define L1C_BYPASS L1C_BYPASS 94 #define L1C_BYPASS_POS (14U) 95 #define L1C_BYPASS_LEN (1U) 96 #define L1C_BYPASS_MSK (((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS) 97 #define L1C_BYPASS_UMSK (~(((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS)) 98 #define L1C_BMX_ERR_EN L1C_BMX_ERR_EN 99 #define L1C_BMX_ERR_EN_POS (15U) 100 #define L1C_BMX_ERR_EN_LEN (1U) 101 #define L1C_BMX_ERR_EN_MSK (((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS) 102 #define L1C_BMX_ERR_EN_UMSK (~(((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS)) 103 #define L1C_BMX_ARB_MODE L1C_BMX_ARB_MODE 104 #define L1C_BMX_ARB_MODE_POS (16U) 105 #define L1C_BMX_ARB_MODE_LEN (2U) 106 #define L1C_BMX_ARB_MODE_MSK (((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS) 107 #define L1C_BMX_ARB_MODE_UMSK (~(((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS)) 108 #define L1C_BMX_TIMEOUT_EN L1C_BMX_TIMEOUT_EN 109 #define L1C_BMX_TIMEOUT_EN_POS (20U) 110 #define L1C_BMX_TIMEOUT_EN_LEN (4U) 111 #define L1C_BMX_TIMEOUT_EN_MSK (((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS) 112 #define L1C_BMX_TIMEOUT_EN_UMSK (~(((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS)) 113 #define L1C_BMX_BUSY_OPTION_DIS L1C_BMX_BUSY_OPTION_DIS 114 #define L1C_BMX_BUSY_OPTION_DIS_POS (24U) 115 #define L1C_BMX_BUSY_OPTION_DIS_LEN (1U) 116 #define L1C_BMX_BUSY_OPTION_DIS_MSK (((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS) 117 #define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS)) 118 #define L1C_EARLY_RESP_DIS L1C_EARLY_RESP_DIS 119 #define L1C_EARLY_RESP_DIS_POS (25U) 120 #define L1C_EARLY_RESP_DIS_LEN (1U) 121 #define L1C_EARLY_RESP_DIS_MSK (((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS) 122 #define L1C_EARLY_RESP_DIS_UMSK (~(((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS)) 123 #define L1C_WRAP_DIS L1C_WRAP_DIS 124 #define L1C_WRAP_DIS_POS (26U) 125 #define L1C_WRAP_DIS_LEN (1U) 126 #define L1C_WRAP_DIS_MSK (((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS) 127 #define L1C_WRAP_DIS_UMSK (~(((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS)) 128 #define L1C_FLUSH_EN L1C_FLUSH_EN 129 #define L1C_FLUSH_EN_POS (28U) 130 #define L1C_FLUSH_EN_LEN (1U) 131 #define L1C_FLUSH_EN_MSK (((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS) 132 #define L1C_FLUSH_EN_UMSK (~(((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS)) 133 #define L1C_FLUSH_DONE L1C_FLUSH_DONE 134 #define L1C_FLUSH_DONE_POS (29U) 135 #define L1C_FLUSH_DONE_LEN (1U) 136 #define L1C_FLUSH_DONE_MSK (((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS) 137 #define L1C_FLUSH_DONE_UMSK (~(((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS)) 138 139 /* 0x4 : hit_cnt_lsb */ 140 #define L1C_HIT_CNT_LSB_OFFSET (0x4) 141 #define L1C_HIT_CNT_LSB L1C_HIT_CNT_LSB 142 #define L1C_HIT_CNT_LSB_POS (0U) 143 #define L1C_HIT_CNT_LSB_LEN (32U) 144 #define L1C_HIT_CNT_LSB_MSK (((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS) 145 #define L1C_HIT_CNT_LSB_UMSK (~(((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS)) 146 147 /* 0x8 : hit_cnt_msb */ 148 #define L1C_HIT_CNT_MSB_OFFSET (0x8) 149 #define L1C_HIT_CNT_MSB L1C_HIT_CNT_MSB 150 #define L1C_HIT_CNT_MSB_POS (0U) 151 #define L1C_HIT_CNT_MSB_LEN (32U) 152 #define L1C_HIT_CNT_MSB_MSK (((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS) 153 #define L1C_HIT_CNT_MSB_UMSK (~(((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS)) 154 155 /* 0xC : miss_cnt */ 156 #define L1C_MISS_CNT_OFFSET (0xC) 157 #define L1C_MISS_CNT L1C_MISS_CNT 158 #define L1C_MISS_CNT_POS (0U) 159 #define L1C_MISS_CNT_LEN (32U) 160 #define L1C_MISS_CNT_MSK (((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS) 161 #define L1C_MISS_CNT_UMSK (~(((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS)) 162 163 /* 0x10 : l1c_misc */ 164 #define L1C_MISC_OFFSET (0x10) 165 #define L1C_FSM L1C_FSM 166 #define L1C_FSM_POS (28U) 167 #define L1C_FSM_LEN (3U) 168 #define L1C_FSM_MSK (((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS) 169 #define L1C_FSM_UMSK (~(((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS)) 170 171 /* 0x200 : l1c_bmx_err_addr_en */ 172 #define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200) 173 #define L1C_BMX_ERR_ADDR_DIS L1C_BMX_ERR_ADDR_DIS 174 #define L1C_BMX_ERR_ADDR_DIS_POS (0U) 175 #define L1C_BMX_ERR_ADDR_DIS_LEN (1U) 176 #define L1C_BMX_ERR_ADDR_DIS_MSK (((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS) 177 #define L1C_BMX_ERR_ADDR_DIS_UMSK (~(((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS)) 178 #define L1C_BMX_ERR_DEC L1C_BMX_ERR_DEC 179 #define L1C_BMX_ERR_DEC_POS (4U) 180 #define L1C_BMX_ERR_DEC_LEN (1U) 181 #define L1C_BMX_ERR_DEC_MSK (((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS) 182 #define L1C_BMX_ERR_DEC_UMSK (~(((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS)) 183 #define L1C_BMX_ERR_TZ L1C_BMX_ERR_TZ 184 #define L1C_BMX_ERR_TZ_POS (5U) 185 #define L1C_BMX_ERR_TZ_LEN (1U) 186 #define L1C_BMX_ERR_TZ_MSK (((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS) 187 #define L1C_BMX_ERR_TZ_UMSK (~(((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS)) 188 #define L1C_HSEL_OPTION L1C_HSEL_OPTION 189 #define L1C_HSEL_OPTION_POS (16U) 190 #define L1C_HSEL_OPTION_LEN (4U) 191 #define L1C_HSEL_OPTION_MSK (((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS) 192 #define L1C_HSEL_OPTION_UMSK (~(((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS)) 193 194 /* 0x204 : l1c_bmx_err_addr */ 195 #define L1C_BMX_ERR_ADDR_OFFSET (0x204) 196 #define L1C_BMX_ERR_ADDR L1C_BMX_ERR_ADDR 197 #define L1C_BMX_ERR_ADDR_POS (0U) 198 #define L1C_BMX_ERR_ADDR_LEN (32U) 199 #define L1C_BMX_ERR_ADDR_MSK (((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS) 200 #define L1C_BMX_ERR_ADDR_UMSK (~(((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS)) 201 202 /* 0x208 : irom1_misr_dataout_0 */ 203 #define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208) 204 #define L1C_IROM1_MISR_DATAOUT_0 L1C_IROM1_MISR_DATAOUT_0 205 #define L1C_IROM1_MISR_DATAOUT_0_POS (0U) 206 #define L1C_IROM1_MISR_DATAOUT_0_LEN (32U) 207 #define L1C_IROM1_MISR_DATAOUT_0_MSK (((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS) 208 #define L1C_IROM1_MISR_DATAOUT_0_UMSK (~(((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS)) 209 210 /* 0x20C : irom1_misr_dataout_1 */ 211 #define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C) 212 #define L1C_IROM1_MISR_DATAOUT_1 L1C_IROM1_MISR_DATAOUT_1 213 #define L1C_IROM1_MISR_DATAOUT_1_POS (0U) 214 #define L1C_IROM1_MISR_DATAOUT_1_LEN (32U) 215 #define L1C_IROM1_MISR_DATAOUT_1_MSK (((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS) 216 #define L1C_IROM1_MISR_DATAOUT_1_UMSK (~(((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS)) 217 218 /* 0x210 : cpu_clk_gate */ 219 #define L1C_CPU_CLK_GATE_OFFSET (0x210) 220 #define L1C_FORCE_E21_CLOCK_ON_0 L1C_FORCE_E21_CLOCK_ON_0 221 #define L1C_FORCE_E21_CLOCK_ON_0_POS (0U) 222 #define L1C_FORCE_E21_CLOCK_ON_0_LEN (1U) 223 #define L1C_FORCE_E21_CLOCK_ON_0_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS) 224 #define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS)) 225 #define L1C_FORCE_E21_CLOCK_ON_1 L1C_FORCE_E21_CLOCK_ON_1 226 #define L1C_FORCE_E21_CLOCK_ON_1_POS (1U) 227 #define L1C_FORCE_E21_CLOCK_ON_1_LEN (1U) 228 #define L1C_FORCE_E21_CLOCK_ON_1_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS) 229 #define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS)) 230 #define L1C_FORCE_E21_CLOCK_ON_2 L1C_FORCE_E21_CLOCK_ON_2 231 #define L1C_FORCE_E21_CLOCK_ON_2_POS (2U) 232 #define L1C_FORCE_E21_CLOCK_ON_2_LEN (1U) 233 #define L1C_FORCE_E21_CLOCK_ON_2_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS) 234 #define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS)) 235 236 struct l1c_reg { 237 /* 0x0 : l1c_config */ 238 union { 239 struct 240 { 241 uint32_t l1c_cacheable : 1; /* [ 0], r/w, 0x0 */ 242 uint32_t l1c_cnt_en : 1; /* [ 1], r/w, 0x0 */ 243 uint32_t l1c_invalid_en : 1; /* [ 2], r/w, 0x0 */ 244 uint32_t l1c_invalid_done : 1; /* [ 3], r, 0x0 */ 245 uint32_t l1c_wt_en : 1; /* [ 4], r/w, 0x0 */ 246 uint32_t l1c_wb_en : 1; /* [ 5], r/w, 0x1 */ 247 uint32_t l1c_wa_en : 1; /* [ 6], r/w, 0x1 */ 248 uint32_t l1c_random_replace : 1; /* [ 7], r/w, 0x0 */ 249 uint32_t l1c_way_dis : 4; /* [11: 8], r/w, 0xf */ 250 uint32_t irom_2t_access : 1; /* [ 12], r/w, 0x0 */ 251 uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */ 252 uint32_t l1c_bypass : 1; /* [ 14], r/w, 0x0 */ 253 uint32_t l1c_bmx_err_en : 1; /* [ 15], r/w, 0x0 */ 254 uint32_t l1c_bmx_arb_mode : 2; /* [17:16], r/w, 0x0 */ 255 uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */ 256 uint32_t l1c_bmx_timeout_en : 4; /* [23:20], r/w, 0x0 */ 257 uint32_t l1c_bmx_busy_option_dis : 1; /* [ 24], r/w, 0x0 */ 258 uint32_t early_resp_dis : 1; /* [ 25], r/w, 0x1 */ 259 uint32_t wrap_dis : 1; /* [ 26], r/w, 0x1 */ 260 uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */ 261 uint32_t l1c_flush_en : 1; /* [ 28], r/w, 0x0 */ 262 uint32_t l1c_flush_done : 1; /* [ 29], r, 0x0 */ 263 uint32_t reserved_31_30 : 2; /* [31:30], rsvd, 0x0 */ 264 } BF; 265 uint32_t WORD; 266 } l1c_config; 267 268 /* 0x4 : hit_cnt_lsb */ 269 union { 270 struct 271 { 272 uint32_t hit_cnt_lsb : 32; /* [31: 0], r, 0x0 */ 273 } BF; 274 uint32_t WORD; 275 } hit_cnt_lsb; 276 277 /* 0x8 : hit_cnt_msb */ 278 union { 279 struct 280 { 281 uint32_t hit_cnt_msb : 32; /* [31: 0], r, 0x0 */ 282 } BF; 283 uint32_t WORD; 284 } hit_cnt_msb; 285 286 /* 0xC : miss_cnt */ 287 union { 288 struct 289 { 290 uint32_t miss_cnt : 32; /* [31: 0], r, 0x0 */ 291 } BF; 292 uint32_t WORD; 293 } miss_cnt; 294 295 /* 0x10 : l1c_misc */ 296 union { 297 struct 298 { 299 uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ 300 uint32_t l1c_fsm : 3; /* [30:28], r, 0x0 */ 301 uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ 302 } BF; 303 uint32_t WORD; 304 } l1c_misc; 305 306 /* 0x14 reserved */ 307 uint8_t RESERVED0x14[492]; 308 309 /* 0x200 : l1c_bmx_err_addr_en */ 310 union { 311 struct 312 { 313 uint32_t l1c_bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */ 314 uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ 315 uint32_t l1c_bmx_err_dec : 1; /* [ 4], r, 0x0 */ 316 uint32_t l1c_bmx_err_tz : 1; /* [ 5], r, 0x0 */ 317 uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ 318 uint32_t l1c_hsel_option : 4; /* [19:16], r/w, 0x0 */ 319 uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ 320 } BF; 321 uint32_t WORD; 322 } l1c_bmx_err_addr_en; 323 324 /* 0x204 : l1c_bmx_err_addr */ 325 union { 326 struct 327 { 328 uint32_t l1c_bmx_err_addr : 32; /* [31: 0], r, 0x0 */ 329 } BF; 330 uint32_t WORD; 331 } l1c_bmx_err_addr; 332 333 /* 0x208 : irom1_misr_dataout_0 */ 334 union { 335 struct 336 { 337 uint32_t irom1_misr_dataout_0 : 32; /* [31: 0], r, 0x0 */ 338 } BF; 339 uint32_t WORD; 340 } irom1_misr_dataout_0; 341 342 /* 0x20C : irom1_misr_dataout_1 */ 343 union { 344 struct 345 { 346 uint32_t irom1_misr_dataout_1 : 32; /* [31: 0], r, 0x0 */ 347 } BF; 348 uint32_t WORD; 349 } irom1_misr_dataout_1; 350 351 /* 0x210 : cpu_clk_gate */ 352 union { 353 struct 354 { 355 uint32_t force_e21_clock_on_0 : 1; /* [ 0], r/w, 0x0 */ 356 uint32_t force_e21_clock_on_1 : 1; /* [ 1], r/w, 0x0 */ 357 uint32_t force_e21_clock_on_2 : 1; /* [ 2], r/w, 0x0 */ 358 uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ 359 } BF; 360 uint32_t WORD; 361 } cpu_clk_gate; 362 }; 363 364 typedef volatile struct l1c_reg l1c_reg_t; 365 366 #endif /* __L1C_REG_H__ */ 367