1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2006-09-15 QiuYi the first version */ 9 10 #ifndef __BSP_H_ 11 #define __BSP_H_ 12 13 #include <i386.h> 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 /*******************************************************************/ 20 /* Timer Register */ 21 /*******************************************************************/ 22 #define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ 23 #define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ 24 #define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ 25 #define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ 26 #define TIMER_SEL0 0x00 /* select counter 0 */ 27 #define TIMER_SEL1 0x40 /* select counter 1 */ 28 #define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ 29 #define TIMER_ONESHOT 0x02 /* mode 1, one shot */ 30 #define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ 31 #define TIMER_SQWAVE 0x06 /* mode 3, square wave */ 32 #define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ 33 #define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ 34 #define TIMER_LATCH 0x00 /* latch counter for reading */ 35 #define TIMER_LSB 0x10 /* r/w counter LSB */ 36 #define TIMER_MSB 0x20 /* r/w counter MSB */ 37 #define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ 38 #define TIMER_BCD 0x01 /* count in BCD */ 39 40 #define TIMER_FREQ 1193182 41 #define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x)) 42 43 #define IO_TIMER1 0x040 /* 8253 Timer #1 */ 44 45 /*******************************************************************/ 46 /* Interrupt Controller */ 47 /*******************************************************************/ 48 /* these are processor defined */ 49 #define T_DIVIDE 0 /* divide error */ 50 #define T_DEBUG 1 /* debug exception */ 51 #define T_NMI 2 /* non-maskable interrupt */ 52 #define T_BRKPT 3 /* breakpoint */ 53 #define T_OFLOW 4 /* overflow */ 54 #define T_BOUND 5 /* bounds check */ 55 #define T_ILLOP 6 /* illegal opcode */ 56 #define T_DEVICE 7 /* device not available */ 57 #define T_DBLFLT 8 /* double fault */ 58 /* 9 is reserved */ 59 #define T_TSS 10 /* invalid task switch segment */ 60 #define T_SEGNP 11 /* segment not present */ 61 #define T_STACK 12 /* stack exception */ 62 #define T_GPFLT 13 /* genernal protection fault */ 63 #define T_PGFLT 14 /* page fault */ 64 /* 15 is reserved */ 65 #define T_FPERR 16 /* floating point error */ 66 #define T_ALIGN 17 /* aligment check */ 67 #define T_MCHK 18 /* machine check */ 68 #define T_DEFAULT 500 /* catchall */ 69 70 #define INTTIMER0 0 71 #define INTKEYBOARD 1 72 #define INTUART0_RX 4 73 #define CLOCK_IRQ 0 74 #define KEYBOARD_IRQ 1 75 #define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */ 76 #define ETHER_IRQ 3 /* default ethernet interrupt vector */ 77 #define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */ 78 #define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */ 79 #define XT_WINI_IRQ 5 /* xt winchester */ 80 #define FLOPPY_IRQ 6 /* floppy disk */ 81 #define PRINTER_IRQ 7 82 #define AT_WINI_IRQ 14 /* at winchester */ 83 /* I/O Addresses of the two 8259A programmable interrupt controllers */ 84 #define IO_PIC1 0x20 /* Master(IRQs 0-7) */ 85 #define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */ 86 #define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */ 87 #define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */ 88 89 #define MAX_HANDLERS 16 /*max number of isr handler*/ 90 91 /*******************************************************************/ 92 /* CRT Register */ 93 /*******************************************************************/ 94 #define MONO_BASE 0x3b4 95 #define MONO_BUF 0xb0000 96 #define CGA_BASE 0x3d4 97 #define CGA_BUF 0xb8000 98 99 #define CRT_ROWS 25 100 #define CRT_COLS 80 101 #define CRT_SIZE (CRT_ROWS * CRT_COLS) 102 103 /*******************************************************************/ 104 /* Keyboard Register */ 105 /*******************************************************************/ 106 #define KBSTATP 0x64 /* kbd controller status port(I) */ 107 #define KBS_DIB 0x01 /* kbd data in buffer */ 108 #define KBDATAP 0x60 /* kbd data port(I) */ 109 /* AT keyboard */ 110 /* 8042 ports */ 111 #define KB_DATA 0x60 /* I/O port for keyboard data 112 * Read : Read Output Buffer 113 * Write: Write Input Buffer(8042 Data&8048 Command) */ 114 #define KB_CMD 0x64 /* I/O port for keyboard command 115 * Read : Read Status Register 116 * Write: Write Input Buffer(8042 Command) */ 117 #define LED_CODE 0xED 118 #define KB_ACK 0xFA 119 120 /*******************************************************************/ 121 /* Serial Register */ 122 /*******************************************************************/ 123 /*Serial I/O code */ 124 #define COM1 0x3F8 125 #define COMSTATUS 5 126 #define COMDATA 0x01 127 #define COMREAD 0 128 #define COMWRITE 0 129 130 /* Bits definition of the Line Status Register (LSR)*/ 131 #define DR 0x01 /* Data Ready */ 132 #define OE 0x02 /* Overrun Error */ 133 #define PE 0x04 /* Parity Error */ 134 #define FE 0x08 /* Framing Error */ 135 #define BI 0x10 /* Break Interrupt */ 136 #define THRE 0x20 /* Transmitter Holding Register Empty */ 137 #define TEMT 0x40 /* Transmitter Empty */ 138 #define ERFIFO 0x80 /* Error receive Fifo */ 139 140 #ifdef __cplusplus 141 } 142 #endif 143 144 #endif /* __BSP_H_ */ 145