1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16 (+) Access to Routing Interfaces registers
17
18 @endverbatim
19 ******************************************************************************
20 * @attention
21 *
22 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
23 * All rights reserved.</center></h2>
24 *
25 * This software component is licensed by ST under BSD 3-Clause license,
26 * the "License"; You may not use this file except in compliance with the
27 * License. You may obtain a copy of the License at:
28 * opensource.org/licenses/BSD-3-Clause
29 *
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32L1xx_LL_SYSTEM_H
35 #define __STM32L1xx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32l1xx.h"
43
44 /** @addtogroup STM32L1xx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61
62 /**
63 * @brief Power-down in Run mode Flash key
64 */
65 #define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */
66 #define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
67 to unlock the RUN_PD bit in FLASH_ACR */
68
69 /**
70 * @}
71 */
72
73 /* Private macros ------------------------------------------------------------*/
74
75 /* Exported types ------------------------------------------------------------*/
76 /* Exported constants --------------------------------------------------------*/
77 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
78 * @{
79 */
80
81 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
82 * @{
83 */
84 #define LL_SYSCFG_REMAP_FLASH (0x00000000U) /*<! Main Flash memory mapped at 0x00000000 */
85 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*<! System Flash memory mapped at 0x00000000 */
86 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*<! Embedded SRAM mapped at 0x00000000 */
87 #if defined(FSMC_R_BASE)
88 #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*<! FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
89 #endif /* FSMC_R_BASE */
90 /**
91 * @}
92 */
93
94 /** @defgroup SYSTEM_LL_EC_BOOT SYSCFG BOOT MODE
95 * @{
96 */
97 #define LL_SYSCFG_BOOTMODE_FLASH (0x00000000U) /*<! Main Flash memory boot mode */
98 #define LL_SYSCFG_BOOTMODE_SYSTEMFLASH SYSCFG_MEMRMP_BOOT_MODE_0 /*<! System Flash memory boot mode */
99 #if defined(FSMC_BANK1)
100 #define LL_SYSCFG_BOOTMODE_FSMC SYSCFG_MEMRMP_BOOT_MODE_1 /*<! FSMC boot mode */
101 #endif /* FSMC_BANK1 */
102 #define LL_SYSCFG_BOOTMODE_SRAM SYSCFG_MEMRMP_BOOT_MODE /*<! Embedded SRAM boot mode */
103 /**
104 * @}
105 */
106
107 #if defined(LCD)
108 /** @defgroup SYSTEM_LL_EC_LCDCAPA SYSCFG LCD capacitance connection
109 * @{
110 */
111 #define LL_SYSCFG_LCDCAPA_PB2 SYSCFG_PMC_LCD_CAPA_0 /*<! controls the connection of VLCDrail2 on PB2/LCD_VCAP2 */
112 #define LL_SYSCFG_LCDCAPA_PB12 SYSCFG_PMC_LCD_CAPA_1 /*<! controls the connection of VLCDrail1 on PB12/LCD_VCAP1 */
113 #define LL_SYSCFG_LCDCAPA_PB0 SYSCFG_PMC_LCD_CAPA_2 /*<! controls the connection of VLCDrail3 on PB0/LCD_VCAP3 */
114 #define LL_SYSCFG_LCDCAPA_PE11 SYSCFG_PMC_LCD_CAPA_3 /*<! controls the connection of VLCDrail1 on PE11/LCD_VCAP1 */
115 #define LL_SYSCFG_LCDCAPA_PE12 SYSCFG_PMC_LCD_CAPA_4 /*<! controls the connection of VLCDrail3 on PE12/LCD_VCAP3 */
116 /**
117 * @}
118 */
119
120 #endif /* LCD */
121
122 /** @defgroup SYSTEM_LL_EC_EXTI SYSCFG EXTI PORT
123 * @{
124 */
125 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
126 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
127 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
128 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
129 #if defined(GPIOE)
130 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
131 #endif /* GPIOE */
132 #if defined(GPIOF)
133 #define LL_SYSCFG_EXTI_PORTF 6U /*!< EXTI PORT F */
134 #endif /* GPIOF */
135 #if defined(GPIOG)
136 #define LL_SYSCFG_EXTI_PORTG 7U /*!< EXTI PORT G */
137 #endif /* GPIOG */
138 #define LL_SYSCFG_EXTI_PORTH 5U /*!< EXTI PORT H */
139 /**
140 * @}
141 */
142
143 /** @addtogroup SYSTEM_LL_EC_SYSCFG EXTI LINE
144 * @{
145 */
146 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
147 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
148 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
149 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
150 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
151 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
152 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
153 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
154 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
155 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
156 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
157 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
158 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
159 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
160 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
161 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */
162 /**
163 * @}
164 */
165
166 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
167 * @{
168 */
169 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
170 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
171 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
172 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
173 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
174 /**
175 * @}
176 */
177
178 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
179 * @{
180 */
181 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
182 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
183 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
184 #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
185 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
186 #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
187 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
188 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
189 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
190 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Counter stopped when Core is halted */
191 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
192 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
193 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
194 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
195 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
196 /**
197 * @}
198 */
199
200 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
201 * @{
202 */
203 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
204 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
205 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
206 /**
207 * @}
208 */
209
210 /** @defgroup SYSTEM_LL_EC_TIM_SELECT RI TIM selection
211 * @{
212 */
213 #define LL_RI_TIM_SELECT_NONE (0x00000000U) /*!< No timer selected */
214 #define LL_RI_TIM_SELECT_TIM2 RI_ICR_TIM_0 /*!< Timer 2 selected */
215 #define LL_RI_TIM_SELECT_TIM3 RI_ICR_TIM_1 /*!< Timer 3 selected */
216 #define LL_RI_TIM_SELECT_TIM4 RI_ICR_TIM /*!< Timer 4 selected */
217 /**
218 * @}
219 */
220
221 /** @defgroup SYSTEM_LL_EC_INPUTCAPTURE RI Input Capture number
222 * @{
223 */
224 #define LL_RI_INPUTCAPTURE_1 (RI_ICR_IC1 | RI_ICR_IC1OS) /*!< Input Capture 1 select output */
225 #define LL_RI_INPUTCAPTURE_2 (RI_ICR_IC2 | RI_ICR_IC2OS) /*!< Input Capture 2 select output */
226 #define LL_RI_INPUTCAPTURE_3 (RI_ICR_IC3 | RI_ICR_IC3OS) /*!< Input Capture 3 select output */
227 #define LL_RI_INPUTCAPTURE_4 (RI_ICR_IC4 | RI_ICR_IC4OS) /*!< Input Capture 4 select output */
228 /**
229 * @}
230 */
231
232 /** @defgroup SYSTEM_LL_EC_INPUTCAPTUREROUTING RI Input Capture Routing
233 * @{
234 */
235 /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
236 #define LL_RI_INPUTCAPTUREROUTING_0 (0x00000000U) /*!< PA0 PA1 PA2 PA3 */
237 #define LL_RI_INPUTCAPTUREROUTING_1 (0x00000001U) /*!< PA4 PA5 PA6 PA7 */
238 #define LL_RI_INPUTCAPTUREROUTING_2 (0x00000002U) /*!< PA8 PA9 PA10 PA11 */
239 #define LL_RI_INPUTCAPTUREROUTING_3 (0x00000003U) /*!< PA12 PA13 PA14 PA15 */
240 #define LL_RI_INPUTCAPTUREROUTING_4 (0x00000004U) /*!< PC0 PC1 PC2 PC3 */
241 #define LL_RI_INPUTCAPTUREROUTING_5 (0x00000005U) /*!< PC4 PC5 PC6 PC7 */
242 #define LL_RI_INPUTCAPTUREROUTING_6 (0x00000006U) /*!< PC8 PC9 PC10 PC11 */
243 #define LL_RI_INPUTCAPTUREROUTING_7 (0x00000007U) /*!< PC12 PC13 PC14 PC15 */
244 #define LL_RI_INPUTCAPTUREROUTING_8 (0x00000008U) /*!< PD0 PD1 PD2 PD3 */
245 #define LL_RI_INPUTCAPTUREROUTING_9 (0x00000009U) /*!< PD4 PD5 PD6 PD7 */
246 #define LL_RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /*!< PD8 PD9 PD10 PD11 */
247 #define LL_RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /*!< PD12 PD13 PD14 PD15 */
248 #if defined(GPIOE)
249 #define LL_RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /*!< PE0 PE1 PE2 PE3 */
250 #define LL_RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /*!< PE4 PE5 PE6 PE7 */
251 #define LL_RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /*!< PE8 PE9 PE10 PE11 */
252 #define LL_RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /*!< PE12 PE13 PE14 PE15 */
253 #endif /* GPIOE */
254 /**
255 * @}
256 */
257
258 /** @defgroup SYSTEM_LL_EC_IOSWITCH_LINKED_ADC RI IO Switch linked to ADC
259 * @{
260 */
261 #define LL_RI_IOSWITCH_CH0 RI_ASCR1_CH_0 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */
262 #define LL_RI_IOSWITCH_CH1 RI_ASCR1_CH_1 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */
263 #define LL_RI_IOSWITCH_CH2 RI_ASCR1_CH_2 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */
264 #define LL_RI_IOSWITCH_CH3 RI_ASCR1_CH_3 /*!< CH[3:0] GR1[4:1]: I/O Analog switch control */
265 #define LL_RI_IOSWITCH_CH4 RI_ASCR1_CH_4 /*!< CH4: Analog switch control */
266 #define LL_RI_IOSWITCH_CH5 RI_ASCR1_CH_5 /*!< CH5: Comparator 1 analog switch*/
267 #define LL_RI_IOSWITCH_CH6 RI_ASCR1_CH_6 /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */
268 #define LL_RI_IOSWITCH_CH7 RI_ASCR1_CH_7 /*!< CH[7:6] GR2[2:1]: I/O Analog switch control */
269 #define LL_RI_IOSWITCH_CH8 RI_ASCR1_CH_8 /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */
270 #define LL_RI_IOSWITCH_CH9 RI_ASCR1_CH_9 /*!< CH[9:8] GR3[2:1]: I/O Analog switch control */
271 #define LL_RI_IOSWITCH_CH10 RI_ASCR1_CH_10 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */
272 #define LL_RI_IOSWITCH_CH11 RI_ASCR1_CH_11 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */
273 #define LL_RI_IOSWITCH_CH12 RI_ASCR1_CH_12 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */
274 #define LL_RI_IOSWITCH_CH13 RI_ASCR1_CH_13 /*!< CH[13:10] GR8[4:1]: I/O Analog switch control */
275 #define LL_RI_IOSWITCH_CH14 RI_ASCR1_CH_14 /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */
276 #define LL_RI_IOSWITCH_CH15 RI_ASCR1_CH_15 /*!< CH[15:14] GR9[2:1]: I/O Analog switch control */
277 #define LL_RI_IOSWITCH_CH18 RI_ASCR1_CH_18 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */
278 #define LL_RI_IOSWITCH_CH19 RI_ASCR1_CH_19 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */
279 #define LL_RI_IOSWITCH_CH20 RI_ASCR1_CH_20 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */
280 #define LL_RI_IOSWITCH_CH21 RI_ASCR1_CH_21 /*!< CH[21:18]/GR7[4:1]: I/O Analog switch control */
281 #define LL_RI_IOSWITCH_CH22 RI_ASCR1_CH_22 /*!< Analog I/O switch control of channels CH22 */
282 #define LL_RI_IOSWITCH_CH23 RI_ASCR1_CH_23 /*!< Analog I/O switch control of channels CH23 */
283 #define LL_RI_IOSWITCH_CH24 RI_ASCR1_CH_24 /*!< Analog I/O switch control of channels CH24 */
284 #define LL_RI_IOSWITCH_CH25 RI_ASCR1_CH_25 /*!< Analog I/O switch control of channels CH25 */
285 #define LL_RI_IOSWITCH_VCOMP RI_ASCR1_VCOMP /*!< VCOMP (ADC channel 26) is an internal switch
286 used to connect selected channel to COMP1 non inverting input */
287 #if defined(RI_ASCR1_CH_27)
288 #define LL_RI_IOSWITCH_CH27 RI_ASCR1_CH_27 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */
289 #define LL_RI_IOSWITCH_CH28 RI_ASCR1_CH_28 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */
290 #define LL_RI_IOSWITCH_CH29 RI_ASCR1_CH_29 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */
291 #define LL_RI_IOSWITCH_CH30 RI_ASCR1_CH_30 /*!< CH[30:27]/GR11[4:1]: I/O Analog switch control */
292 #define LL_RI_IOSWITCH_CH31 RI_ASCR1_CH_31 /*!< CH31/GR11-5 I/O Analog switch control */
293 #endif /* RI_ASCR1_CH_27 */
294 /**
295 * @}
296 */
297
298 /** @defgroup SYSTEM_LL_EC_IOSWITCH_NOT_LINKED_ADC RI IO Switch not linked to ADC
299 * @{
300 */
301 #define LL_RI_IOSWITCH_GR10_1 RI_ASCR2_GR10_1 /*!< GR10-1 I/O analog switch control */
302 #define LL_RI_IOSWITCH_GR10_2 RI_ASCR2_GR10_2 /*!< GR10-2 I/O analog switch control */
303 #define LL_RI_IOSWITCH_GR10_3 RI_ASCR2_GR10_3 /*!< GR10-3 I/O analog switch control */
304 #define LL_RI_IOSWITCH_GR10_4 RI_ASCR2_GR10_4 /*!< GR10-4 I/O analog switch control */
305 #define LL_RI_IOSWITCH_GR6_1 RI_ASCR2_GR6_1 /*!< GR6-1 I/O analog switch control */
306 #define LL_RI_IOSWITCH_GR6_2 RI_ASCR2_GR6_2 /*!< GR6-2 I/O analog switch control */
307 #define LL_RI_IOSWITCH_GR5_1 RI_ASCR2_GR5_1 /*!< GR5-1 I/O analog switch control */
308 #define LL_RI_IOSWITCH_GR5_2 RI_ASCR2_GR5_2 /*!< GR5-2 I/O analog switch control */
309 #define LL_RI_IOSWITCH_GR5_3 RI_ASCR2_GR5_3 /*!< GR5-3 I/O analog switch control */
310 #define LL_RI_IOSWITCH_GR4_1 RI_ASCR2_GR4_1 /*!< GR4-1 I/O analog switch control */
311 #define LL_RI_IOSWITCH_GR4_2 RI_ASCR2_GR4_2 /*!< GR4-2 I/O analog switch control */
312 #define LL_RI_IOSWITCH_GR4_3 RI_ASCR2_GR4_3 /*!< GR4-3 I/O analog switch control */
313 #if defined(RI_ASCR2_CH0b)
314 #define LL_RI_IOSWITCH_CH0b RI_ASCR2_CH0b /*!< CH0b-GR03-3 I/O analog switch control */
315 #if defined(RI_ASCR2_CH1b)
316 #define LL_RI_IOSWITCH_CH1b RI_ASCR2_CH1b /*!< CH1b-GR03-4 I/O analog switch control */
317 #define LL_RI_IOSWITCH_CH2b RI_ASCR2_CH2b /*!< CH2b-GR03-5 I/O analog switch control */
318 #define LL_RI_IOSWITCH_CH3b RI_ASCR2_CH3b /*!< CH3b-GR09-3 I/O analog switch control */
319 #define LL_RI_IOSWITCH_CH6b RI_ASCR2_CH6b /*!< CH6b-GR09-4 I/O analog switch control */
320 #define LL_RI_IOSWITCH_CH7b RI_ASCR2_CH7b /*!< CH7b-GR02-3 I/O analog switch control */
321 #define LL_RI_IOSWITCH_CH8b RI_ASCR2_CH8b /*!< CH8b-GR02-4 I/O analog switch control */
322 #define LL_RI_IOSWITCH_CH9b RI_ASCR2_CH9b /*!< CH9b-GR02-5 I/O analog switch control */
323 #define LL_RI_IOSWITCH_CH10b RI_ASCR2_CH10b /*!< CH10b-GR07-5 I/O analog switch control */
324 #define LL_RI_IOSWITCH_CH11b RI_ASCR2_CH11b /*!< CH11b-GR07-6 I/O analog switch control */
325 #define LL_RI_IOSWITCH_CH12b RI_ASCR2_CH12b /*!< CH12b-GR07-7 I/O analog switch control */
326 #endif /* RI_ASCR2_CH1b */
327 #define LL_RI_IOSWITCH_GR6_3 RI_ASCR2_GR6_3 /*!< GR6-3 I/O analog switch control */
328 #define LL_RI_IOSWITCH_GR6_4 RI_ASCR2_GR6_4 /*!< GR6-4 I/O analog switch control */
329 #endif /* RI_ASCR2_CH0b */
330 /**
331 * @}
332 */
333
334 /** @defgroup SYSTEM_LL_EC_HSYTERESIS_PORT RI HSYTERESIS PORT
335 * @{
336 */
337 #define LL_RI_HSYTERESIS_PORT_A 0U /*!< HYSTERESIS PORT A */
338 #define LL_RI_HSYTERESIS_PORT_B 1U /*!< HYSTERESIS PORT B */
339 #define LL_RI_HSYTERESIS_PORT_C 2U /*!< HYSTERESIS PORT C */
340 #define LL_RI_HSYTERESIS_PORT_D 3U /*!< HYSTERESIS PORT D */
341 #if defined(GPIOE)
342 #define LL_RI_HSYTERESIS_PORT_E 4U /*!< HYSTERESIS PORT E */
343 #endif /* GPIOE */
344 #if defined(GPIOF)
345 #define LL_RI_HSYTERESIS_PORT_F 5U /*!< HYSTERESIS PORT F */
346 #endif /* GPIOF */
347 #if defined(GPIOG)
348 #define LL_RI_HSYTERESIS_PORT_G 6U /*!< HYSTERESIS PORT G */
349 #endif /* GPIOG */
350 /**
351 * @}
352 */
353
354 /** @defgroup SYSTEM_LL_EC_PIN RI PIN
355 * @{
356 */
357 #define LL_RI_PIN_0 ((uint16_t)0x0001U) /*!< Pin 0 selected */
358 #define LL_RI_PIN_1 ((uint16_t)0x0002U) /*!< Pin 1 selected */
359 #define LL_RI_PIN_2 ((uint16_t)0x0004U) /*!< Pin 2 selected */
360 #define LL_RI_PIN_3 ((uint16_t)0x0008U) /*!< Pin 3 selected */
361 #define LL_RI_PIN_4 ((uint16_t)0x0010U) /*!< Pin 4 selected */
362 #define LL_RI_PIN_5 ((uint16_t)0x0020U) /*!< Pin 5 selected */
363 #define LL_RI_PIN_6 ((uint16_t)0x0040U) /*!< Pin 6 selected */
364 #define LL_RI_PIN_7 ((uint16_t)0x0080U) /*!< Pin 7 selected */
365 #define LL_RI_PIN_8 ((uint16_t)0x0100U) /*!< Pin 8 selected */
366 #define LL_RI_PIN_9 ((uint16_t)0x0200U) /*!< Pin 9 selected */
367 #define LL_RI_PIN_10 ((uint16_t)0x0400U) /*!< Pin 10 selected */
368 #define LL_RI_PIN_11 ((uint16_t)0x0800U) /*!< Pin 11 selected */
369 #define LL_RI_PIN_12 ((uint16_t)0x1000U) /*!< Pin 12 selected */
370 #define LL_RI_PIN_13 ((uint16_t)0x2000U) /*!< Pin 13 selected */
371 #define LL_RI_PIN_14 ((uint16_t)0x4000U) /*!< Pin 14 selected */
372 #define LL_RI_PIN_15 ((uint16_t)0x8000U) /*!< Pin 15 selected */
373 #define LL_RI_PIN_ALL ((uint16_t)0xFFFFU) /*!< All pins selected */
374 /**
375 * @}
376 */
377
378 #if defined(RI_ASMR1_PA)
379 /** @defgroup SYSTEM_LL_EC_PORT RI PORT
380 * @{
381 */
382 #define LL_RI_PORT_A 0U /*!< PORT A */
383 #define LL_RI_PORT_B 1U /*!< PORT B */
384 #define LL_RI_PORT_C 2U /*!< PORT C */
385 #if defined(GPIOF)
386 #define LL_RI_PORT_F 3U /*!< PORT F */
387 #endif /* GPIOF */
388 #if defined(GPIOG)
389 #define LL_RI_PORT_G 4U /*!< PORT G */
390 #endif /* GPIOG */
391 /**
392 * @}
393 */
394
395 #endif /* RI_ASMR1_PA */
396
397
398 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
399 * @{
400 */
401 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
402 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
403 /**
404 * @}
405 */
406
407 /**
408 * @}
409 */
410
411 /* Exported macro ------------------------------------------------------------*/
412
413 /* Exported functions --------------------------------------------------------*/
414 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
415 * @{
416 */
417
418 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
419 * @{
420 */
421
422 /**
423 * @brief Set memory mapping at address 0x00000000
424 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
425 * @param Memory This parameter can be one of the following values:
426 * @arg @ref LL_SYSCFG_REMAP_FLASH
427 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
428 * @arg @ref LL_SYSCFG_REMAP_SRAM
429 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
430 *
431 * (*) value not defined in all devices
432 * @retval None
433 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)434 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
435 {
436 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
437 }
438
439 /**
440 * @brief Get memory mapping at address 0x00000000
441 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
442 * @retval Returned value can be one of the following values:
443 * @arg @ref LL_SYSCFG_REMAP_FLASH
444 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
445 * @arg @ref LL_SYSCFG_REMAP_SRAM
446 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
447 *
448 * (*) value not defined in all devices.
449 */
LL_SYSCFG_GetRemapMemory(void)450 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
451 {
452 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
453 }
454
455 /**
456 * @brief Return the boot mode as configured by user.
457 * @rmtoll SYSCFG_MEMRMP BOOT_MODE LL_SYSCFG_GetBootMode
458 * @retval Returned value can be one of the following values:
459 * @arg @ref LL_SYSCFG_BOOTMODE_FLASH
460 * @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH
461 * @arg @ref LL_SYSCFG_BOOTMODE_FSMC (*)
462 * @arg @ref LL_SYSCFG_BOOTMODE_SRAM
463 *
464 * (*) value not defined in all devices.
465 */
LL_SYSCFG_GetBootMode(void)466 __STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void)
467 {
468 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE));
469 }
470
471 /**
472 * @brief Enable internal pull-up on USB DP line.
473 * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_EnableUSBPullUp
474 * @retval None
475 */
LL_SYSCFG_EnableUSBPullUp(void)476 __STATIC_INLINE void LL_SYSCFG_EnableUSBPullUp(void)
477 {
478 SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU);
479 }
480
481 /**
482 * @brief Disable internal pull-up on USB DP line.
483 * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_DisableUSBPullUp
484 * @retval None
485 */
LL_SYSCFG_DisableUSBPullUp(void)486 __STATIC_INLINE void LL_SYSCFG_DisableUSBPullUp(void)
487 {
488 CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU);
489 }
490
491 #if defined(LCD)
492 /**
493 * @brief Enable decoupling capacitance connection.
494 * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_EnableLCDCapacitanceConnection
495 * @param Pin This parameter can be a combination of the following values:
496 * @arg @ref LL_SYSCFG_LCDCAPA_PB2
497 * @arg @ref LL_SYSCFG_LCDCAPA_PB12
498 * @arg @ref LL_SYSCFG_LCDCAPA_PB0
499 * @arg @ref LL_SYSCFG_LCDCAPA_PE11
500 * @arg @ref LL_SYSCFG_LCDCAPA_PE12
501 * @retval None
502 */
LL_SYSCFG_EnableLCDCapacitanceConnection(uint32_t Pin)503 __STATIC_INLINE void LL_SYSCFG_EnableLCDCapacitanceConnection(uint32_t Pin)
504 {
505 SET_BIT(SYSCFG->PMC, Pin);
506 }
507
508 /**
509 * @brief DIsable decoupling capacitance connection.
510 * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_DisableLCDCapacitanceConnection
511 * @param Pin This parameter can be a combination of the following values:
512 * @arg @ref LL_SYSCFG_LCDCAPA_PB2
513 * @arg @ref LL_SYSCFG_LCDCAPA_PB12
514 * @arg @ref LL_SYSCFG_LCDCAPA_PB0
515 * @arg @ref LL_SYSCFG_LCDCAPA_PE11
516 * @arg @ref LL_SYSCFG_LCDCAPA_PE12
517 * @retval None
518 */
LL_SYSCFG_DisableLCDCapacitanceConnection(uint32_t Pin)519 __STATIC_INLINE void LL_SYSCFG_DisableLCDCapacitanceConnection(uint32_t Pin)
520 {
521 CLEAR_BIT(SYSCFG->PMC, Pin);
522 }
523 #endif /* LCD */
524
525 /**
526 * @brief Configure source input for the EXTI external interrupt.
527 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
528 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
529 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
530 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
531 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
532 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
533 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
534 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
535 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
536 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
537 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
538 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
539 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
540 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
541 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
542 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
543 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
544 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
545 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
546 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
547 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
548 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
549 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
550 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
551 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
552 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
553 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
554 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
555 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
556 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
557 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
558 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
559 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
560 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
561 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
562 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
563 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
564 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
565 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
566 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
567 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
568 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
569 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
570 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
571 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
572 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
573 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
574 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
575 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
576 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
577 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
578 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
579 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
580 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
581 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
582 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
583 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
584 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
585 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
586 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
587 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
588 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
589 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
590 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
591 * @param Port This parameter can be one of the following values:
592 * @arg @ref LL_SYSCFG_EXTI_PORTA
593 * @arg @ref LL_SYSCFG_EXTI_PORTB
594 * @arg @ref LL_SYSCFG_EXTI_PORTC
595 * @arg @ref LL_SYSCFG_EXTI_PORTD
596 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
597 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
598 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
599 * @arg @ref LL_SYSCFG_EXTI_PORTH
600 *
601 * (*) value not defined in all devices.
602 * @param Line This parameter can be one of the following values:
603 * @arg @ref LL_SYSCFG_EXTI_LINE0
604 * @arg @ref LL_SYSCFG_EXTI_LINE1
605 * @arg @ref LL_SYSCFG_EXTI_LINE2
606 * @arg @ref LL_SYSCFG_EXTI_LINE3
607 * @arg @ref LL_SYSCFG_EXTI_LINE4
608 * @arg @ref LL_SYSCFG_EXTI_LINE5
609 * @arg @ref LL_SYSCFG_EXTI_LINE6
610 * @arg @ref LL_SYSCFG_EXTI_LINE7
611 * @arg @ref LL_SYSCFG_EXTI_LINE8
612 * @arg @ref LL_SYSCFG_EXTI_LINE9
613 * @arg @ref LL_SYSCFG_EXTI_LINE10
614 * @arg @ref LL_SYSCFG_EXTI_LINE11
615 * @arg @ref LL_SYSCFG_EXTI_LINE12
616 * @arg @ref LL_SYSCFG_EXTI_LINE13
617 * @arg @ref LL_SYSCFG_EXTI_LINE14
618 * @arg @ref LL_SYSCFG_EXTI_LINE15
619 * @retval None
620 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)621 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
622 {
623 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
624 }
625
626 /**
627 * @brief Get the configured defined for specific EXTI Line
628 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
629 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
630 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
631 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
632 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
633 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
634 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
635 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
636 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
637 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
638 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
639 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
640 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
641 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
642 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
643 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
644 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
645 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
646 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
647 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
648 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
649 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
650 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
651 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
652 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
653 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
654 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
655 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
656 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
657 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
658 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
659 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
660 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
661 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
662 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
663 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
664 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
665 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
666 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
667 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
668 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
669 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
670 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
671 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
672 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
673 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
674 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
675 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
676 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
677 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
678 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
679 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
680 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
681 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
682 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
683 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
684 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
685 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
686 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
687 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
688 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
689 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
690 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
691 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
692 * @param Line This parameter can be one of the following values:
693 * @arg @ref LL_SYSCFG_EXTI_LINE0
694 * @arg @ref LL_SYSCFG_EXTI_LINE1
695 * @arg @ref LL_SYSCFG_EXTI_LINE2
696 * @arg @ref LL_SYSCFG_EXTI_LINE3
697 * @arg @ref LL_SYSCFG_EXTI_LINE4
698 * @arg @ref LL_SYSCFG_EXTI_LINE5
699 * @arg @ref LL_SYSCFG_EXTI_LINE6
700 * @arg @ref LL_SYSCFG_EXTI_LINE7
701 * @arg @ref LL_SYSCFG_EXTI_LINE8
702 * @arg @ref LL_SYSCFG_EXTI_LINE9
703 * @arg @ref LL_SYSCFG_EXTI_LINE10
704 * @arg @ref LL_SYSCFG_EXTI_LINE11
705 * @arg @ref LL_SYSCFG_EXTI_LINE12
706 * @arg @ref LL_SYSCFG_EXTI_LINE13
707 * @arg @ref LL_SYSCFG_EXTI_LINE14
708 * @arg @ref LL_SYSCFG_EXTI_LINE15
709 * @retval Returned value can be one of the following values:
710 * @arg @ref LL_SYSCFG_EXTI_PORTA
711 * @arg @ref LL_SYSCFG_EXTI_PORTB
712 * @arg @ref LL_SYSCFG_EXTI_PORTC
713 * @arg @ref LL_SYSCFG_EXTI_PORTD
714 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
715 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
716 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
717 * @arg @ref LL_SYSCFG_EXTI_PORTH
718 *
719 * (*) value not defined in all devices.
720 */
LL_SYSCFG_GetEXTISource(uint32_t Line)721 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
722 {
723 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16)) >> POSITION_VAL(Line >> 16));
724 }
725
726 /**
727 * @}
728 */
729
730 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
731 * @{
732 */
733
734 /**
735 * @brief Return the device identifier
736 * @note 0x416: Cat.1 device\n
737 * 0x429: Cat.2 device\n
738 * 0x427: Cat.3 device\n
739 * 0x436: Cat.4 device or Cat.3 device(1)\n
740 * 0x437: Cat.5 device\n
741 *
742 * (1) Cat.3 devices: STM32L15xxC or STM3216xxC devices with
743 * RPN ending with letter 'A', in WLCSP64 packages or with more then 100 pin.
744 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
745 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
746 */
LL_DBGMCU_GetDeviceID(void)747 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
748 {
749 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
750 }
751
752 /**
753 * @brief Return the device revision identifier
754 * @note This field indicates the revision of the device.
755 For example, it is read as Cat.1 RevA -> 0x1000, Cat.2 Rev Z -> 0x1018...
756 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
757 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
758 */
LL_DBGMCU_GetRevisionID(void)759 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
760 {
761 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
762 }
763
764 /**
765 * @brief Enable the Debug Module during SLEEP mode
766 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
767 * @retval None
768 */
LL_DBGMCU_EnableDBGSleepMode(void)769 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
770 {
771 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
772 }
773
774 /**
775 * @brief Disable the Debug Module during SLEEP mode
776 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
777 * @retval None
778 */
LL_DBGMCU_DisableDBGSleepMode(void)779 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
780 {
781 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
782 }
783
784 /**
785 * @brief Enable the Debug Module during STOP mode
786 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
787 * @retval None
788 */
LL_DBGMCU_EnableDBGStopMode(void)789 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
790 {
791 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
792 }
793
794 /**
795 * @brief Disable the Debug Module during STOP mode
796 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
797 * @retval None
798 */
LL_DBGMCU_DisableDBGStopMode(void)799 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
800 {
801 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
802 }
803
804 /**
805 * @brief Enable the Debug Module during STANDBY mode
806 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
807 * @retval None
808 */
LL_DBGMCU_EnableDBGStandbyMode(void)809 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
810 {
811 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
812 }
813
814 /**
815 * @brief Disable the Debug Module during STANDBY mode
816 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
817 * @retval None
818 */
LL_DBGMCU_DisableDBGStandbyMode(void)819 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
820 {
821 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
822 }
823
824 /**
825 * @brief Set Trace pin assignment control
826 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
827 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
828 * @param PinAssignment This parameter can be one of the following values:
829 * @arg @ref LL_DBGMCU_TRACE_NONE
830 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
831 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
832 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
833 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
834 * @retval None
835 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)836 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
837 {
838 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
839 }
840
841 /**
842 * @brief Get Trace pin assignment control
843 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
844 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
845 * @retval Returned value can be one of the following values:
846 * @arg @ref LL_DBGMCU_TRACE_NONE
847 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
848 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
849 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
850 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
851 */
LL_DBGMCU_GetTracePinAssignment(void)852 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
853 {
854 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
855 }
856
857 /**
858 * @brief Freeze APB1 peripherals (group1 peripherals)
859 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
860 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
861 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
862 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
863 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
864 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
865 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
866 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
867 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
868 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
869 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph
870 * @param Periphs This parameter can be a combination of the following values:
871 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
872 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
873 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
874 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
875 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
876 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
877 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*)
878 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
879 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
880 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
881 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
882 * (*) value not defined in all devices.
883 * @retval None
884 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)885 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
886 {
887 SET_BIT(DBGMCU->APB1FZ, Periphs);
888 }
889
890 /**
891 * @brief Unfreeze APB1 peripherals (group1 peripherals)
892 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
893 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
894 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
895 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
896 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
897 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
898 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
899 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
900 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
901 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
902 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
903 * @param Periphs This parameter can be a combination of the following values:
904 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
905 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
906 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
907 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
908 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
909 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
910 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*)
911 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
912 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
913 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
914 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
915 * (*) value not defined in all devices.
916 * @retval None
917 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)918 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
919 {
920 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
921 }
922
923 /**
924 * @brief Freeze APB2 peripherals
925 * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
926 * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
927 * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
928 * @param Periphs This parameter can be a combination of the following values:
929 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
930 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
931 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
932 * @retval None
933 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)934 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
935 {
936 SET_BIT(DBGMCU->APB2FZ, Periphs);
937 }
938
939 /**
940 * @brief Unfreeze APB2 peripherals
941 * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
942 * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
943 * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
944 * @param Periphs This parameter can be a combination of the following values:
945 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
946 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
947 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
948 * @retval None
949 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)950 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
951 {
952 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
953 }
954
955 /**
956 * @}
957 */
958
959 #if defined(COMP_CSR_VREFOUTEN)
960 /** @defgroup SYSTEM_LL_EF_VREFOUT VREFOUT
961 * @{
962 */
963
964 /**
965 * @brief Enable the output of internal reference voltage (VrefInt) on I/O pin.
966 * @note The VrefInt output can be routed to any I/O in group 3:
967 * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
968 * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
969 * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
970 * CH1b (PF11) or CH2b (PF12).
971 * Note: Comparator peripheral clock must be preliminarily enabled.
972 * Refer to function "LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_COMP)".
973 * Note: In addition with this macro, VrefInt output buffer must be
974 * connected to the selected I/O pin. Refer to functions
975 * "LL_RI_EnableSwitchControlMode()" and "LL_RI_CloseIOSwitchLinkedToADC()".
976 * @note VrefInt output enable: Internal reference voltage connected to I/O group 3
977 * VrefInt output disable: Internal reference voltage disconnected from I/O group 3
978 * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_Enable
979 * @retval None
980 */
LL_VREFOUT_Enable(void)981 __STATIC_INLINE void LL_VREFOUT_Enable(void)
982 {
983 SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN);
984 }
985
986 /**
987 * @brief Disable the output of internal reference voltage (VrefInt) on I/O pin.
988 * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_Disable
989 * @retval None
990 */
LL_VREFOUT_Disable(void)991 __STATIC_INLINE void LL_VREFOUT_Disable(void)
992 {
993 CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN);
994 }
995
996 /**
997 * @brief Check if output of internal reference voltage (VrefInt) is connected to I/O pin.
998 * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_IsEnabled
999 * @retval State of bit (1 or 0).
1000 */
LL_VREFOUT_IsEnabled(void)1001 __STATIC_INLINE uint32_t LL_VREFOUT_IsEnabled(void)
1002 {
1003 return ((READ_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) == COMP_CSR_VREFOUTEN) ? 1UL : 0UL);
1004 }
1005
1006 /**
1007 * @}
1008 */
1009 #endif /* COMP_CSR_VREFOUTEN */
1010
1011 /** @defgroup SYSTEM_LL_EF_RI RI
1012 * @{
1013 */
1014
1015 /**
1016 * @brief Configures the routing interface to map Input Capture x of TIMx to a selected I/O pin.
1017 * @rmtoll RI_ICR IC1OS LL_RI_SetRemapInputCapture_TIM\n
1018 * RI_ICR IC2OS LL_RI_SetRemapInputCapture_TIM\n
1019 * RI_ICR IC3OS LL_RI_SetRemapInputCapture_TIM\n
1020 * RI_ICR IC4OS LL_RI_SetRemapInputCapture_TIM\n
1021 * RI_ICR TIM LL_RI_SetRemapInputCapture_TIM\n
1022 * RI_ICR IC1 LL_RI_SetRemapInputCapture_TIM\n
1023 * RI_ICR IC2 LL_RI_SetRemapInputCapture_TIM\n
1024 * RI_ICR IC3 LL_RI_SetRemapInputCapture_TIM\n
1025 * RI_ICR IC4 LL_RI_SetRemapInputCapture_TIM
1026 * @param TIM_Select This parameter can be one of the following values:
1027 * @arg @ref LL_RI_TIM_SELECT_NONE
1028 * @arg @ref LL_RI_TIM_SELECT_TIM2
1029 * @arg @ref LL_RI_TIM_SELECT_TIM3
1030 * @arg @ref LL_RI_TIM_SELECT_TIM4
1031 * @param InputCaptureChannel This parameter can be one of the following values:
1032 * @arg @ref LL_RI_INPUTCAPTURE_1
1033 * @arg @ref LL_RI_INPUTCAPTURE_2
1034 * @arg @ref LL_RI_INPUTCAPTURE_3
1035 * @arg @ref LL_RI_INPUTCAPTURE_4
1036 * @param Input This parameter can be one of the following values:
1037 * @arg @ref LL_RI_INPUTCAPTUREROUTING_0
1038 * @arg @ref LL_RI_INPUTCAPTUREROUTING_1
1039 * @arg @ref LL_RI_INPUTCAPTUREROUTING_2
1040 * @arg @ref LL_RI_INPUTCAPTUREROUTING_3
1041 * @arg @ref LL_RI_INPUTCAPTUREROUTING_4
1042 * @arg @ref LL_RI_INPUTCAPTUREROUTING_5
1043 * @arg @ref LL_RI_INPUTCAPTUREROUTING_6
1044 * @arg @ref LL_RI_INPUTCAPTUREROUTING_7
1045 * @arg @ref LL_RI_INPUTCAPTUREROUTING_8
1046 * @arg @ref LL_RI_INPUTCAPTUREROUTING_9
1047 * @arg @ref LL_RI_INPUTCAPTUREROUTING_10
1048 * @arg @ref LL_RI_INPUTCAPTUREROUTING_11
1049 * @arg @ref LL_RI_INPUTCAPTUREROUTING_12 (*)
1050 * @arg @ref LL_RI_INPUTCAPTUREROUTING_13 (*)
1051 * @arg @ref LL_RI_INPUTCAPTUREROUTING_14 (*)
1052 * @arg @ref LL_RI_INPUTCAPTUREROUTING_15 (*)
1053 *
1054 * (*) value not defined in all devices.
1055 * @retval None
1056 */
LL_RI_SetRemapInputCapture_TIM(uint32_t TIM_Select,uint32_t InputCaptureChannel,uint32_t Input)1057 __STATIC_INLINE void LL_RI_SetRemapInputCapture_TIM(uint32_t TIM_Select, uint32_t InputCaptureChannel, uint32_t Input)
1058 {
1059 MODIFY_REG(RI->ICR,
1060 RI_ICR_TIM | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (InputCaptureChannel & (RI_ICR_IC4OS | RI_ICR_IC3OS | RI_ICR_IC2OS | RI_ICR_IC1OS)),
1061 TIM_Select | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (Input << POSITION_VAL(InputCaptureChannel)));
1062 }
1063
1064 /**
1065 * @brief Disable the TIM Input capture remap (select the standard AF)
1066 * @rmtoll RI_ICR IC1 LL_RI_DisableRemapInputCapture_TIM\n
1067 * RI_ICR IC2 LL_RI_DisableRemapInputCapture_TIM\n
1068 * RI_ICR IC3 LL_RI_DisableRemapInputCapture_TIM\n
1069 * RI_ICR IC4 LL_RI_DisableRemapInputCapture_TIM
1070 * @param InputCaptureChannel This parameter can be a combination of the following values:
1071 * @arg @ref LL_RI_INPUTCAPTURE_1
1072 * @arg @ref LL_RI_INPUTCAPTURE_2
1073 * @arg @ref LL_RI_INPUTCAPTURE_3
1074 * @arg @ref LL_RI_INPUTCAPTURE_4
1075 * @retval None
1076 */
LL_RI_DisableRemapInputCapture_TIM(uint32_t InputCaptureChannel)1077 __STATIC_INLINE void LL_RI_DisableRemapInputCapture_TIM(uint32_t InputCaptureChannel)
1078 {
1079 CLEAR_BIT(RI->ICR, (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)));
1080 }
1081
1082 /**
1083 * @brief Close the routing interface Input Output switches linked to ADC.
1084 * @rmtoll RI_ASCR1 CH LL_RI_CloseIOSwitchLinkedToADC\n
1085 * RI_ASCR1 VCOMP LL_RI_CloseIOSwitchLinkedToADC
1086 * @param IOSwitch This parameter can be a combination of the following values:
1087 * @arg @ref LL_RI_IOSWITCH_CH0
1088 * @arg @ref LL_RI_IOSWITCH_CH1
1089 * @arg @ref LL_RI_IOSWITCH_CH2
1090 * @arg @ref LL_RI_IOSWITCH_CH3
1091 * @arg @ref LL_RI_IOSWITCH_CH4
1092 * @arg @ref LL_RI_IOSWITCH_CH5
1093 * @arg @ref LL_RI_IOSWITCH_CH6
1094 * @arg @ref LL_RI_IOSWITCH_CH7
1095 * @arg @ref LL_RI_IOSWITCH_CH8
1096 * @arg @ref LL_RI_IOSWITCH_CH9
1097 * @arg @ref LL_RI_IOSWITCH_CH10
1098 * @arg @ref LL_RI_IOSWITCH_CH11
1099 * @arg @ref LL_RI_IOSWITCH_CH12
1100 * @arg @ref LL_RI_IOSWITCH_CH13
1101 * @arg @ref LL_RI_IOSWITCH_CH14
1102 * @arg @ref LL_RI_IOSWITCH_CH15
1103 * @arg @ref LL_RI_IOSWITCH_CH18
1104 * @arg @ref LL_RI_IOSWITCH_CH19
1105 * @arg @ref LL_RI_IOSWITCH_CH20
1106 * @arg @ref LL_RI_IOSWITCH_CH21
1107 * @arg @ref LL_RI_IOSWITCH_CH22
1108 * @arg @ref LL_RI_IOSWITCH_CH23
1109 * @arg @ref LL_RI_IOSWITCH_CH24
1110 * @arg @ref LL_RI_IOSWITCH_CH25
1111 * @arg @ref LL_RI_IOSWITCH_VCOMP
1112 * @arg @ref LL_RI_IOSWITCH_CH27 (*)
1113 * @arg @ref LL_RI_IOSWITCH_CH28 (*)
1114 * @arg @ref LL_RI_IOSWITCH_CH29 (*)
1115 * @arg @ref LL_RI_IOSWITCH_CH30 (*)
1116 * @arg @ref LL_RI_IOSWITCH_CH31 (*)
1117 *
1118 * (*) value not defined in all devices.
1119 * @retval None
1120 */
LL_RI_CloseIOSwitchLinkedToADC(uint32_t IOSwitch)1121 __STATIC_INLINE void LL_RI_CloseIOSwitchLinkedToADC(uint32_t IOSwitch)
1122 {
1123 SET_BIT(RI->ASCR1, IOSwitch);
1124 }
1125
1126 /**
1127 * @brief Open the routing interface Input Output switches linked to ADC.
1128 * @rmtoll RI_ASCR1 CH LL_RI_OpenIOSwitchLinkedToADC\n
1129 * RI_ASCR1 VCOMP LL_RI_OpenIOSwitchLinkedToADC
1130 * @param IOSwitch This parameter can be a combination of the following values:
1131 * @arg @ref LL_RI_IOSWITCH_CH0
1132 * @arg @ref LL_RI_IOSWITCH_CH1
1133 * @arg @ref LL_RI_IOSWITCH_CH2
1134 * @arg @ref LL_RI_IOSWITCH_CH3
1135 * @arg @ref LL_RI_IOSWITCH_CH4
1136 * @arg @ref LL_RI_IOSWITCH_CH5
1137 * @arg @ref LL_RI_IOSWITCH_CH6
1138 * @arg @ref LL_RI_IOSWITCH_CH7
1139 * @arg @ref LL_RI_IOSWITCH_CH8
1140 * @arg @ref LL_RI_IOSWITCH_CH9
1141 * @arg @ref LL_RI_IOSWITCH_CH10
1142 * @arg @ref LL_RI_IOSWITCH_CH11
1143 * @arg @ref LL_RI_IOSWITCH_CH12
1144 * @arg @ref LL_RI_IOSWITCH_CH13
1145 * @arg @ref LL_RI_IOSWITCH_CH14
1146 * @arg @ref LL_RI_IOSWITCH_CH15
1147 * @arg @ref LL_RI_IOSWITCH_CH18
1148 * @arg @ref LL_RI_IOSWITCH_CH19
1149 * @arg @ref LL_RI_IOSWITCH_CH20
1150 * @arg @ref LL_RI_IOSWITCH_CH21
1151 * @arg @ref LL_RI_IOSWITCH_CH22
1152 * @arg @ref LL_RI_IOSWITCH_CH23
1153 * @arg @ref LL_RI_IOSWITCH_CH24
1154 * @arg @ref LL_RI_IOSWITCH_CH25
1155 * @arg @ref LL_RI_IOSWITCH_VCOMP
1156 * @arg @ref LL_RI_IOSWITCH_CH27 (*)
1157 * @arg @ref LL_RI_IOSWITCH_CH28 (*)
1158 * @arg @ref LL_RI_IOSWITCH_CH29 (*)
1159 * @arg @ref LL_RI_IOSWITCH_CH30 (*)
1160 * @arg @ref LL_RI_IOSWITCH_CH31 (*)
1161 *
1162 * (*) value not defined in all devices.
1163 * @retval None
1164 */
LL_RI_OpenIOSwitchLinkedToADC(uint32_t IOSwitch)1165 __STATIC_INLINE void LL_RI_OpenIOSwitchLinkedToADC(uint32_t IOSwitch)
1166 {
1167 CLEAR_BIT(RI->ASCR1, IOSwitch);
1168 }
1169
1170 /**
1171 * @brief Enable the switch control mode.
1172 * @rmtoll RI_ASCR1 SCM LL_RI_EnableSwitchControlMode
1173 * @retval None
1174 */
LL_RI_EnableSwitchControlMode(void)1175 __STATIC_INLINE void LL_RI_EnableSwitchControlMode(void)
1176 {
1177 SET_BIT(RI->ASCR1, RI_ASCR1_SCM);
1178 }
1179
1180 /**
1181 * @brief Disable the switch control mode.
1182 * @rmtoll RI_ASCR1 SCM LL_RI_DisableSwitchControlMode
1183 * @retval None
1184 */
LL_RI_DisableSwitchControlMode(void)1185 __STATIC_INLINE void LL_RI_DisableSwitchControlMode(void)
1186 {
1187 CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM);
1188 }
1189
1190 /**
1191 * @brief Close the routing interface Input Output switches not linked to ADC.
1192 * @rmtoll RI_ASCR2 GR10_1 LL_RI_CloseIOSwitchNotLinkedToADC\n
1193 * RI_ASCR2 GR10_2 LL_RI_CloseIOSwitchNotLinkedToADC\n
1194 * RI_ASCR2 GR10_3 LL_RI_CloseIOSwitchNotLinkedToADC\n
1195 * RI_ASCR2 GR10_4 LL_RI_CloseIOSwitchNotLinkedToADC\n
1196 * RI_ASCR2 GR6_1 LL_RI_CloseIOSwitchNotLinkedToADC\n
1197 * RI_ASCR2 GR6_2 LL_RI_CloseIOSwitchNotLinkedToADC\n
1198 * RI_ASCR2 GR5_1 LL_RI_CloseIOSwitchNotLinkedToADC\n
1199 * RI_ASCR2 GR5_2 LL_RI_CloseIOSwitchNotLinkedToADC\n
1200 * RI_ASCR2 GR5_3 LL_RI_CloseIOSwitchNotLinkedToADC\n
1201 * RI_ASCR2 GR4_1 LL_RI_CloseIOSwitchNotLinkedToADC\n
1202 * RI_ASCR2 GR4_2 LL_RI_CloseIOSwitchNotLinkedToADC\n
1203 * RI_ASCR2 GR4_3 LL_RI_CloseIOSwitchNotLinkedToADC\n
1204 * RI_ASCR2 GR4_4 LL_RI_CloseIOSwitchNotLinkedToADC\n
1205 * RI_ASCR2 CH0b LL_RI_CloseIOSwitchNotLinkedToADC\n
1206 * RI_ASCR2 CH1b LL_RI_CloseIOSwitchNotLinkedToADC\n
1207 * RI_ASCR2 CH2b LL_RI_CloseIOSwitchNotLinkedToADC\n
1208 * RI_ASCR2 CH3b LL_RI_CloseIOSwitchNotLinkedToADC\n
1209 * RI_ASCR2 CH6b LL_RI_CloseIOSwitchNotLinkedToADC\n
1210 * RI_ASCR2 CH7b LL_RI_CloseIOSwitchNotLinkedToADC\n
1211 * RI_ASCR2 CH8b LL_RI_CloseIOSwitchNotLinkedToADC\n
1212 * RI_ASCR2 CH9b LL_RI_CloseIOSwitchNotLinkedToADC\n
1213 * RI_ASCR2 CH10b LL_RI_CloseIOSwitchNotLinkedToADC\n
1214 * RI_ASCR2 CH11b LL_RI_CloseIOSwitchNotLinkedToADC\n
1215 * RI_ASCR2 CH12b LL_RI_CloseIOSwitchNotLinkedToADC\n
1216 * RI_ASCR2 GR6_3 LL_RI_CloseIOSwitchNotLinkedToADC\n
1217 * RI_ASCR2 GR6_4 LL_RI_CloseIOSwitchNotLinkedToADC
1218 * @param IOSwitch This parameter can be a combination of the following values:
1219 * @arg @ref LL_RI_IOSWITCH_GR10_1
1220 * @arg @ref LL_RI_IOSWITCH_GR10_2
1221 * @arg @ref LL_RI_IOSWITCH_GR10_3
1222 * @arg @ref LL_RI_IOSWITCH_GR10_4
1223 * @arg @ref LL_RI_IOSWITCH_GR6_1
1224 * @arg @ref LL_RI_IOSWITCH_GR6_2
1225 * @arg @ref LL_RI_IOSWITCH_GR5_1
1226 * @arg @ref LL_RI_IOSWITCH_GR5_2
1227 * @arg @ref LL_RI_IOSWITCH_GR5_3
1228 * @arg @ref LL_RI_IOSWITCH_GR4_1
1229 * @arg @ref LL_RI_IOSWITCH_GR4_2
1230 * @arg @ref LL_RI_IOSWITCH_GR4_3
1231 * @arg @ref LL_RI_IOSWITCH_CH0b (*)
1232 * @arg @ref LL_RI_IOSWITCH_CH1b (*)
1233 * @arg @ref LL_RI_IOSWITCH_CH2b (*)
1234 * @arg @ref LL_RI_IOSWITCH_CH3b (*)
1235 * @arg @ref LL_RI_IOSWITCH_CH6b (*)
1236 * @arg @ref LL_RI_IOSWITCH_CH7b (*)
1237 * @arg @ref LL_RI_IOSWITCH_CH8b (*)
1238 * @arg @ref LL_RI_IOSWITCH_CH9b (*)
1239 * @arg @ref LL_RI_IOSWITCH_CH10b (*)
1240 * @arg @ref LL_RI_IOSWITCH_CH11b (*)
1241 * @arg @ref LL_RI_IOSWITCH_CH12b (*)
1242 * @arg @ref LL_RI_IOSWITCH_GR6_3
1243 * @arg @ref LL_RI_IOSWITCH_GR6_4
1244 *
1245 * (*) value not defined in all devices.
1246 * @retval None
1247 */
LL_RI_CloseIOSwitchNotLinkedToADC(uint32_t IOSwitch)1248 __STATIC_INLINE void LL_RI_CloseIOSwitchNotLinkedToADC(uint32_t IOSwitch)
1249 {
1250 SET_BIT(RI->ASCR2, IOSwitch);
1251 }
1252
1253 /**
1254 * @brief Open the routing interface Input Output switches not linked to ADC.
1255 * @rmtoll RI_ASCR2 GR10_1 LL_RI_OpenIOSwitchNotLinkedToADC\n
1256 * RI_ASCR2 GR10_2 LL_RI_OpenIOSwitchNotLinkedToADC\n
1257 * RI_ASCR2 GR10_3 LL_RI_OpenIOSwitchNotLinkedToADC\n
1258 * RI_ASCR2 GR10_4 LL_RI_OpenIOSwitchNotLinkedToADC\n
1259 * RI_ASCR2 GR6_1 LL_RI_OpenIOSwitchNotLinkedToADC\n
1260 * RI_ASCR2 GR6_2 LL_RI_OpenIOSwitchNotLinkedToADC\n
1261 * RI_ASCR2 GR5_1 LL_RI_OpenIOSwitchNotLinkedToADC\n
1262 * RI_ASCR2 GR5_2 LL_RI_OpenIOSwitchNotLinkedToADC\n
1263 * RI_ASCR2 GR5_3 LL_RI_OpenIOSwitchNotLinkedToADC\n
1264 * RI_ASCR2 GR4_1 LL_RI_OpenIOSwitchNotLinkedToADC\n
1265 * RI_ASCR2 GR4_2 LL_RI_OpenIOSwitchNotLinkedToADC\n
1266 * RI_ASCR2 GR4_3 LL_RI_OpenIOSwitchNotLinkedToADC\n
1267 * RI_ASCR2 GR4_4 LL_RI_OpenIOSwitchNotLinkedToADC\n
1268 * RI_ASCR2 CH0b LL_RI_OpenIOSwitchNotLinkedToADC\n
1269 * RI_ASCR2 CH1b LL_RI_OpenIOSwitchNotLinkedToADC\n
1270 * RI_ASCR2 CH2b LL_RI_OpenIOSwitchNotLinkedToADC\n
1271 * RI_ASCR2 CH3b LL_RI_OpenIOSwitchNotLinkedToADC\n
1272 * RI_ASCR2 CH6b LL_RI_OpenIOSwitchNotLinkedToADC\n
1273 * RI_ASCR2 CH7b LL_RI_OpenIOSwitchNotLinkedToADC\n
1274 * RI_ASCR2 CH8b LL_RI_OpenIOSwitchNotLinkedToADC\n
1275 * RI_ASCR2 CH9b LL_RI_OpenIOSwitchNotLinkedToADC\n
1276 * RI_ASCR2 CH10b LL_RI_OpenIOSwitchNotLinkedToADC\n
1277 * RI_ASCR2 CH11b LL_RI_OpenIOSwitchNotLinkedToADC\n
1278 * RI_ASCR2 CH12b LL_RI_OpenIOSwitchNotLinkedToADC\n
1279 * RI_ASCR2 GR6_3 LL_RI_OpenIOSwitchNotLinkedToADC\n
1280 * RI_ASCR2 GR6_4 LL_RI_OpenIOSwitchNotLinkedToADC
1281 * @param IOSwitch This parameter can be a combination of the following values:
1282 * @arg @ref LL_RI_IOSWITCH_GR10_1
1283 * @arg @ref LL_RI_IOSWITCH_GR10_2
1284 * @arg @ref LL_RI_IOSWITCH_GR10_3
1285 * @arg @ref LL_RI_IOSWITCH_GR10_4
1286 * @arg @ref LL_RI_IOSWITCH_GR6_1
1287 * @arg @ref LL_RI_IOSWITCH_GR6_2
1288 * @arg @ref LL_RI_IOSWITCH_GR5_1
1289 * @arg @ref LL_RI_IOSWITCH_GR5_2
1290 * @arg @ref LL_RI_IOSWITCH_GR5_3
1291 * @arg @ref LL_RI_IOSWITCH_GR4_1
1292 * @arg @ref LL_RI_IOSWITCH_GR4_2
1293 * @arg @ref LL_RI_IOSWITCH_GR4_3
1294 * @arg @ref LL_RI_IOSWITCH_CH0b (*)
1295 * @arg @ref LL_RI_IOSWITCH_CH1b (*)
1296 * @arg @ref LL_RI_IOSWITCH_CH2b (*)
1297 * @arg @ref LL_RI_IOSWITCH_CH3b (*)
1298 * @arg @ref LL_RI_IOSWITCH_CH6b (*)
1299 * @arg @ref LL_RI_IOSWITCH_CH7b (*)
1300 * @arg @ref LL_RI_IOSWITCH_CH8b (*)
1301 * @arg @ref LL_RI_IOSWITCH_CH9b (*)
1302 * @arg @ref LL_RI_IOSWITCH_CH10b (*)
1303 * @arg @ref LL_RI_IOSWITCH_CH11b (*)
1304 * @arg @ref LL_RI_IOSWITCH_CH12b (*)
1305 * @arg @ref LL_RI_IOSWITCH_GR6_3
1306 * @arg @ref LL_RI_IOSWITCH_GR6_4
1307 *
1308 * (*) value not defined in all devices.
1309 * @retval None
1310 */
LL_RI_OpenIOSwitchNotLinkedToADC(uint32_t IOSwitch)1311 __STATIC_INLINE void LL_RI_OpenIOSwitchNotLinkedToADC(uint32_t IOSwitch)
1312 {
1313 CLEAR_BIT(RI->ASCR2, IOSwitch);
1314 }
1315
1316 /**
1317 * @brief Enable Hysteresis of the input schmitt triger of the port X
1318 * @rmtoll RI_HYSCR1 PA LL_RI_EnableHysteresis\n
1319 * RI_HYSCR1 PB LL_RI_EnableHysteresis\n
1320 * RI_HYSCR1 PC LL_RI_EnableHysteresis\n
1321 * RI_HYSCR1 PD LL_RI_EnableHysteresis\n
1322 * RI_HYSCR1 PE LL_RI_EnableHysteresis\n
1323 * RI_HYSCR1 PF LL_RI_EnableHysteresis\n
1324 * RI_HYSCR1 PG LL_RI_EnableHysteresis\n
1325 * RI_HYSCR2 PA LL_RI_EnableHysteresis\n
1326 * RI_HYSCR2 PB LL_RI_EnableHysteresis\n
1327 * RI_HYSCR2 PC LL_RI_EnableHysteresis\n
1328 * RI_HYSCR2 PD LL_RI_EnableHysteresis\n
1329 * RI_HYSCR2 PE LL_RI_EnableHysteresis\n
1330 * RI_HYSCR2 PF LL_RI_EnableHysteresis\n
1331 * RI_HYSCR2 PG LL_RI_EnableHysteresis\n
1332 * RI_HYSCR3 PA LL_RI_EnableHysteresis\n
1333 * RI_HYSCR3 PB LL_RI_EnableHysteresis\n
1334 * RI_HYSCR3 PC LL_RI_EnableHysteresis\n
1335 * RI_HYSCR3 PD LL_RI_EnableHysteresis\n
1336 * RI_HYSCR3 PE LL_RI_EnableHysteresis\n
1337 * RI_HYSCR3 PF LL_RI_EnableHysteresis\n
1338 * RI_HYSCR3 PG LL_RI_EnableHysteresis\n
1339 * RI_HYSCR4 PA LL_RI_EnableHysteresis\n
1340 * RI_HYSCR4 PB LL_RI_EnableHysteresis\n
1341 * RI_HYSCR4 PC LL_RI_EnableHysteresis\n
1342 * RI_HYSCR4 PD LL_RI_EnableHysteresis\n
1343 * RI_HYSCR4 PE LL_RI_EnableHysteresis\n
1344 * RI_HYSCR4 PF LL_RI_EnableHysteresis\n
1345 * RI_HYSCR4 PG LL_RI_EnableHysteresis
1346 * @param Port This parameter can be one of the following values:
1347 * @arg @ref LL_RI_HSYTERESIS_PORT_A
1348 * @arg @ref LL_RI_HSYTERESIS_PORT_B
1349 * @arg @ref LL_RI_HSYTERESIS_PORT_C
1350 * @arg @ref LL_RI_HSYTERESIS_PORT_D
1351 * @arg @ref LL_RI_HSYTERESIS_PORT_E (*)
1352 * @arg @ref LL_RI_HSYTERESIS_PORT_F (*)
1353 * @arg @ref LL_RI_HSYTERESIS_PORT_G (*)
1354 *
1355 * (*) value not defined in all devices.
1356 * @param Pin This parameter can be a combination of the following values:
1357 * @arg @ref LL_RI_PIN_0
1358 * @arg @ref LL_RI_PIN_1
1359 * @arg @ref LL_RI_PIN_2
1360 * @arg @ref LL_RI_PIN_3
1361 * @arg @ref LL_RI_PIN_4
1362 * @arg @ref LL_RI_PIN_5
1363 * @arg @ref LL_RI_PIN_6
1364 * @arg @ref LL_RI_PIN_7
1365 * @arg @ref LL_RI_PIN_8
1366 * @arg @ref LL_RI_PIN_9
1367 * @arg @ref LL_RI_PIN_10
1368 * @arg @ref LL_RI_PIN_11
1369 * @arg @ref LL_RI_PIN_12
1370 * @arg @ref LL_RI_PIN_13
1371 * @arg @ref LL_RI_PIN_14
1372 * @arg @ref LL_RI_PIN_15
1373 * @arg @ref LL_RI_PIN_ALL
1374 * @retval None
1375 */
LL_RI_EnableHysteresis(uint32_t Port,uint32_t Pin)1376 __STATIC_INLINE void LL_RI_EnableHysteresis(uint32_t Port, uint32_t Pin)
1377 {
1378 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + (Port >> 1U));
1379 CLEAR_BIT(*reg, Pin << (16U * (Port & 1U)));
1380 }
1381
1382 /**
1383 * @brief Disable Hysteresis of the input schmitt triger of the port X
1384 * @rmtoll RI_HYSCR1 PA LL_RI_DisableHysteresis\n
1385 * RI_HYSCR1 PB LL_RI_DisableHysteresis\n
1386 * RI_HYSCR1 PC LL_RI_DisableHysteresis\n
1387 * RI_HYSCR1 PD LL_RI_DisableHysteresis\n
1388 * RI_HYSCR1 PE LL_RI_DisableHysteresis\n
1389 * RI_HYSCR1 PF LL_RI_DisableHysteresis\n
1390 * RI_HYSCR1 PG LL_RI_DisableHysteresis\n
1391 * RI_HYSCR2 PA LL_RI_DisableHysteresis\n
1392 * RI_HYSCR2 PB LL_RI_DisableHysteresis\n
1393 * RI_HYSCR2 PC LL_RI_DisableHysteresis\n
1394 * RI_HYSCR2 PD LL_RI_DisableHysteresis\n
1395 * RI_HYSCR2 PE LL_RI_DisableHysteresis\n
1396 * RI_HYSCR2 PF LL_RI_DisableHysteresis\n
1397 * RI_HYSCR2 PG LL_RI_DisableHysteresis\n
1398 * RI_HYSCR3 PA LL_RI_DisableHysteresis\n
1399 * RI_HYSCR3 PB LL_RI_DisableHysteresis\n
1400 * RI_HYSCR3 PC LL_RI_DisableHysteresis\n
1401 * RI_HYSCR3 PD LL_RI_DisableHysteresis\n
1402 * RI_HYSCR3 PE LL_RI_DisableHysteresis\n
1403 * RI_HYSCR3 PF LL_RI_DisableHysteresis\n
1404 * RI_HYSCR3 PG LL_RI_DisableHysteresis\n
1405 * RI_HYSCR4 PA LL_RI_DisableHysteresis\n
1406 * RI_HYSCR4 PB LL_RI_DisableHysteresis\n
1407 * RI_HYSCR4 PC LL_RI_DisableHysteresis\n
1408 * RI_HYSCR4 PD LL_RI_DisableHysteresis\n
1409 * RI_HYSCR4 PE LL_RI_DisableHysteresis\n
1410 * RI_HYSCR4 PF LL_RI_DisableHysteresis\n
1411 * RI_HYSCR4 PG LL_RI_DisableHysteresis
1412 * @param Port This parameter can be one of the following values:
1413 * @arg @ref LL_RI_HSYTERESIS_PORT_A
1414 * @arg @ref LL_RI_HSYTERESIS_PORT_B
1415 * @arg @ref LL_RI_HSYTERESIS_PORT_C
1416 * @arg @ref LL_RI_HSYTERESIS_PORT_D
1417 * @arg @ref LL_RI_HSYTERESIS_PORT_E (*)
1418 * @arg @ref LL_RI_HSYTERESIS_PORT_F (*)
1419 * @arg @ref LL_RI_HSYTERESIS_PORT_G (*)
1420 *
1421 * (*) value not defined in all devices.
1422 * @param Pin This parameter can be a combination of the following values:
1423 * @arg @ref LL_RI_PIN_0
1424 * @arg @ref LL_RI_PIN_1
1425 * @arg @ref LL_RI_PIN_2
1426 * @arg @ref LL_RI_PIN_3
1427 * @arg @ref LL_RI_PIN_4
1428 * @arg @ref LL_RI_PIN_5
1429 * @arg @ref LL_RI_PIN_6
1430 * @arg @ref LL_RI_PIN_7
1431 * @arg @ref LL_RI_PIN_8
1432 * @arg @ref LL_RI_PIN_9
1433 * @arg @ref LL_RI_PIN_10
1434 * @arg @ref LL_RI_PIN_11
1435 * @arg @ref LL_RI_PIN_12
1436 * @arg @ref LL_RI_PIN_13
1437 * @arg @ref LL_RI_PIN_14
1438 * @arg @ref LL_RI_PIN_15
1439 * @arg @ref LL_RI_PIN_ALL
1440 * @retval None
1441 */
LL_RI_DisableHysteresis(uint32_t Port,uint32_t Pin)1442 __STATIC_INLINE void LL_RI_DisableHysteresis(uint32_t Port, uint32_t Pin)
1443 {
1444 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + ((Port >> 1U) << 2U));
1445 SET_BIT(*reg, Pin << (16U * (Port & 1U)));
1446 }
1447
1448 #if defined(RI_ASMR1_PA)
1449 /**
1450 * @brief Control analog switches of port X through the ADC interface or RI_ASCRx registers.
1451 * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByADC\n
1452 * RI_ASMR1 PB LL_RI_ControlSwitchByADC\n
1453 * RI_ASMR1 PC LL_RI_ControlSwitchByADC\n
1454 * RI_ASMR1 PF LL_RI_ControlSwitchByADC\n
1455 * RI_ASMR1 PG LL_RI_ControlSwitchByADC\n
1456 * RI_ASMR2 PA LL_RI_ControlSwitchByADC\n
1457 * RI_ASMR2 PB LL_RI_ControlSwitchByADC\n
1458 * RI_ASMR2 PC LL_RI_ControlSwitchByADC\n
1459 * RI_ASMR2 PF LL_RI_ControlSwitchByADC\n
1460 * RI_ASMR2 PG LL_RI_ControlSwitchByADC\n
1461 * RI_ASMR3 PA LL_RI_ControlSwitchByADC\n
1462 * RI_ASMR3 PB LL_RI_ControlSwitchByADC\n
1463 * RI_ASMR3 PC LL_RI_ControlSwitchByADC\n
1464 * RI_ASMR3 PF LL_RI_ControlSwitchByADC\n
1465 * RI_ASMR3 PG LL_RI_ControlSwitchByADC\n
1466 * RI_ASMR4 PA LL_RI_ControlSwitchByADC\n
1467 * RI_ASMR4 PB LL_RI_ControlSwitchByADC\n
1468 * RI_ASMR4 PC LL_RI_ControlSwitchByADC\n
1469 * RI_ASMR4 PF LL_RI_ControlSwitchByADC\n
1470 * RI_ASMR4 PG LL_RI_ControlSwitchByADC\n
1471 * RI_ASMR5 PA LL_RI_ControlSwitchByADC\n
1472 * RI_ASMR5 PB LL_RI_ControlSwitchByADC\n
1473 * RI_ASMR5 PC LL_RI_ControlSwitchByADC\n
1474 * RI_ASMR5 PF LL_RI_ControlSwitchByADC\n
1475 * RI_ASMR5 PG LL_RI_ControlSwitchByADC
1476 * @param Port This parameter can be one of the following values:
1477 * @arg @ref LL_RI_PORT_A
1478 * @arg @ref LL_RI_PORT_B
1479 * @arg @ref LL_RI_PORT_C
1480 * @arg @ref LL_RI_PORT_F (*)
1481 * @arg @ref LL_RI_PORT_G (*)
1482 *
1483 * (*) value not defined in all devices.
1484 * @param Pin This parameter can be a combination of the following values:
1485 * @arg @ref LL_RI_PIN_0
1486 * @arg @ref LL_RI_PIN_1
1487 * @arg @ref LL_RI_PIN_2
1488 * @arg @ref LL_RI_PIN_3
1489 * @arg @ref LL_RI_PIN_4
1490 * @arg @ref LL_RI_PIN_5
1491 * @arg @ref LL_RI_PIN_6
1492 * @arg @ref LL_RI_PIN_7
1493 * @arg @ref LL_RI_PIN_8
1494 * @arg @ref LL_RI_PIN_9
1495 * @arg @ref LL_RI_PIN_10
1496 * @arg @ref LL_RI_PIN_11
1497 * @arg @ref LL_RI_PIN_12
1498 * @arg @ref LL_RI_PIN_13
1499 * @arg @ref LL_RI_PIN_14
1500 * @arg @ref LL_RI_PIN_15
1501 * @arg @ref LL_RI_PIN_ALL
1502 * @retval None
1503 */
LL_RI_ControlSwitchByADC(uint32_t Port,uint32_t Pin)1504 __STATIC_INLINE void LL_RI_ControlSwitchByADC(uint32_t Port, uint32_t Pin)
1505 {
1506 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2));
1507 CLEAR_BIT(*reg, Pin);
1508 }
1509 #endif /* RI_ASMR1_PA */
1510
1511 #if defined(RI_ASMR1_PA)
1512 /**
1513 * @brief Control analog switches of port X by the timer OC.
1514 * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByTIM\n
1515 * RI_ASMR1 PB LL_RI_ControlSwitchByTIM\n
1516 * RI_ASMR1 PC LL_RI_ControlSwitchByTIM\n
1517 * RI_ASMR1 PF LL_RI_ControlSwitchByTIM\n
1518 * RI_ASMR1 PG LL_RI_ControlSwitchByTIM\n
1519 * RI_ASMR2 PA LL_RI_ControlSwitchByTIM\n
1520 * RI_ASMR2 PB LL_RI_ControlSwitchByTIM\n
1521 * RI_ASMR2 PC LL_RI_ControlSwitchByTIM\n
1522 * RI_ASMR2 PF LL_RI_ControlSwitchByTIM\n
1523 * RI_ASMR2 PG LL_RI_ControlSwitchByTIM\n
1524 * RI_ASMR3 PA LL_RI_ControlSwitchByTIM\n
1525 * RI_ASMR3 PB LL_RI_ControlSwitchByTIM\n
1526 * RI_ASMR3 PC LL_RI_ControlSwitchByTIM\n
1527 * RI_ASMR3 PF LL_RI_ControlSwitchByTIM\n
1528 * RI_ASMR3 PG LL_RI_ControlSwitchByTIM\n
1529 * RI_ASMR4 PA LL_RI_ControlSwitchByTIM\n
1530 * RI_ASMR4 PB LL_RI_ControlSwitchByTIM\n
1531 * RI_ASMR4 PC LL_RI_ControlSwitchByTIM\n
1532 * RI_ASMR4 PF LL_RI_ControlSwitchByTIM\n
1533 * RI_ASMR4 PG LL_RI_ControlSwitchByTIM\n
1534 * RI_ASMR5 PA LL_RI_ControlSwitchByTIM\n
1535 * RI_ASMR5 PB LL_RI_ControlSwitchByTIM\n
1536 * RI_ASMR5 PC LL_RI_ControlSwitchByTIM\n
1537 * RI_ASMR5 PF LL_RI_ControlSwitchByTIM\n
1538 * RI_ASMR5 PG LL_RI_ControlSwitchByTIM
1539 * @param Port This parameter can be one of the following values:
1540 * @arg @ref LL_RI_PORT_A
1541 * @arg @ref LL_RI_PORT_B
1542 * @arg @ref LL_RI_PORT_C
1543 * @arg @ref LL_RI_PORT_F (*)
1544 * @arg @ref LL_RI_PORT_G (*)
1545 *
1546 * (*) value not defined in all devices.
1547 * @param Pin This parameter can be a combination of the following values:
1548 * @arg @ref LL_RI_PIN_0
1549 * @arg @ref LL_RI_PIN_1
1550 * @arg @ref LL_RI_PIN_2
1551 * @arg @ref LL_RI_PIN_3
1552 * @arg @ref LL_RI_PIN_4
1553 * @arg @ref LL_RI_PIN_5
1554 * @arg @ref LL_RI_PIN_6
1555 * @arg @ref LL_RI_PIN_7
1556 * @arg @ref LL_RI_PIN_8
1557 * @arg @ref LL_RI_PIN_9
1558 * @arg @ref LL_RI_PIN_10
1559 * @arg @ref LL_RI_PIN_11
1560 * @arg @ref LL_RI_PIN_12
1561 * @arg @ref LL_RI_PIN_13
1562 * @arg @ref LL_RI_PIN_14
1563 * @arg @ref LL_RI_PIN_15
1564 * @arg @ref LL_RI_PIN_ALL
1565 * @retval None
1566 */
LL_RI_ControlSwitchByTIM(uint32_t Port,uint32_t Pin)1567 __STATIC_INLINE void LL_RI_ControlSwitchByTIM(uint32_t Port, uint32_t Pin)
1568 {
1569 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2));
1570 SET_BIT(*reg, Pin);
1571 }
1572 #endif /* RI_ASMR1_PA */
1573
1574 #if defined(RI_CMR1_PA)
1575 /**
1576 * @brief Mask the input of port X during the capacitive sensing acquisition.
1577 * @rmtoll RI_CMR1 PA LL_RI_MaskChannelDuringAcquisition\n
1578 * RI_CMR1 PB LL_RI_MaskChannelDuringAcquisition\n
1579 * RI_CMR1 PC LL_RI_MaskChannelDuringAcquisition\n
1580 * RI_CMR1 PF LL_RI_MaskChannelDuringAcquisition\n
1581 * RI_CMR1 PG LL_RI_MaskChannelDuringAcquisition\n
1582 * RI_CMR2 PA LL_RI_MaskChannelDuringAcquisition\n
1583 * RI_CMR2 PB LL_RI_MaskChannelDuringAcquisition\n
1584 * RI_CMR2 PC LL_RI_MaskChannelDuringAcquisition\n
1585 * RI_CMR2 PF LL_RI_MaskChannelDuringAcquisition\n
1586 * RI_CMR2 PG LL_RI_MaskChannelDuringAcquisition\n
1587 * RI_CMR3 PA LL_RI_MaskChannelDuringAcquisition\n
1588 * RI_CMR3 PB LL_RI_MaskChannelDuringAcquisition\n
1589 * RI_CMR3 PC LL_RI_MaskChannelDuringAcquisition\n
1590 * RI_CMR3 PF LL_RI_MaskChannelDuringAcquisition\n
1591 * RI_CMR3 PG LL_RI_MaskChannelDuringAcquisition\n
1592 * RI_CMR4 PA LL_RI_MaskChannelDuringAcquisition\n
1593 * RI_CMR4 PB LL_RI_MaskChannelDuringAcquisition\n
1594 * RI_CMR4 PC LL_RI_MaskChannelDuringAcquisition\n
1595 * RI_CMR4 PF LL_RI_MaskChannelDuringAcquisition\n
1596 * RI_CMR4 PG LL_RI_MaskChannelDuringAcquisition\n
1597 * RI_CMR5 PA LL_RI_MaskChannelDuringAcquisition\n
1598 * RI_CMR5 PB LL_RI_MaskChannelDuringAcquisition\n
1599 * RI_CMR5 PC LL_RI_MaskChannelDuringAcquisition\n
1600 * RI_CMR5 PF LL_RI_MaskChannelDuringAcquisition\n
1601 * RI_CMR5 PG LL_RI_MaskChannelDuringAcquisition
1602 * @param Port This parameter can be one of the following values:
1603 * @arg @ref LL_RI_PORT_A
1604 * @arg @ref LL_RI_PORT_B
1605 * @arg @ref LL_RI_PORT_C
1606 * @arg @ref LL_RI_PORT_F (*)
1607 * @arg @ref LL_RI_PORT_G (*)
1608 *
1609 * (*) value not defined in all devices.
1610 * @param Pin This parameter can be a combination of the following values:
1611 * @arg @ref LL_RI_PIN_0
1612 * @arg @ref LL_RI_PIN_1
1613 * @arg @ref LL_RI_PIN_2
1614 * @arg @ref LL_RI_PIN_3
1615 * @arg @ref LL_RI_PIN_4
1616 * @arg @ref LL_RI_PIN_5
1617 * @arg @ref LL_RI_PIN_6
1618 * @arg @ref LL_RI_PIN_7
1619 * @arg @ref LL_RI_PIN_8
1620 * @arg @ref LL_RI_PIN_9
1621 * @arg @ref LL_RI_PIN_10
1622 * @arg @ref LL_RI_PIN_11
1623 * @arg @ref LL_RI_PIN_12
1624 * @arg @ref LL_RI_PIN_13
1625 * @arg @ref LL_RI_PIN_14
1626 * @arg @ref LL_RI_PIN_15
1627 * @arg @ref LL_RI_PIN_ALL
1628 * @retval None
1629 */
LL_RI_MaskChannelDuringAcquisition(uint32_t Port,uint32_t Pin)1630 __STATIC_INLINE void LL_RI_MaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin)
1631 {
1632 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2));
1633 CLEAR_BIT(*reg, Pin);
1634 }
1635 #endif /* RI_CMR1_PA */
1636
1637 #if defined(RI_CMR1_PA)
1638 /**
1639 * @brief Unmask the input of port X during the capacitive sensing acquisition.
1640 * @rmtoll RI_CMR1 PA LL_RI_UnmaskChannelDuringAcquisition\n
1641 * RI_CMR1 PB LL_RI_UnmaskChannelDuringAcquisition\n
1642 * RI_CMR1 PC LL_RI_UnmaskChannelDuringAcquisition\n
1643 * RI_CMR1 PF LL_RI_UnmaskChannelDuringAcquisition\n
1644 * RI_CMR1 PG LL_RI_UnmaskChannelDuringAcquisition\n
1645 * RI_CMR2 PA LL_RI_UnmaskChannelDuringAcquisition\n
1646 * RI_CMR2 PB LL_RI_UnmaskChannelDuringAcquisition\n
1647 * RI_CMR2 PC LL_RI_UnmaskChannelDuringAcquisition\n
1648 * RI_CMR2 PF LL_RI_UnmaskChannelDuringAcquisition\n
1649 * RI_CMR2 PG LL_RI_UnmaskChannelDuringAcquisition\n
1650 * RI_CMR3 PA LL_RI_UnmaskChannelDuringAcquisition\n
1651 * RI_CMR3 PB LL_RI_UnmaskChannelDuringAcquisition\n
1652 * RI_CMR3 PC LL_RI_UnmaskChannelDuringAcquisition\n
1653 * RI_CMR3 PF LL_RI_UnmaskChannelDuringAcquisition\n
1654 * RI_CMR3 PG LL_RI_UnmaskChannelDuringAcquisition\n
1655 * RI_CMR4 PA LL_RI_UnmaskChannelDuringAcquisition\n
1656 * RI_CMR4 PB LL_RI_UnmaskChannelDuringAcquisition\n
1657 * RI_CMR4 PC LL_RI_UnmaskChannelDuringAcquisition\n
1658 * RI_CMR4 PF LL_RI_UnmaskChannelDuringAcquisition\n
1659 * RI_CMR4 PG LL_RI_UnmaskChannelDuringAcquisition\n
1660 * RI_CMR5 PA LL_RI_UnmaskChannelDuringAcquisition\n
1661 * RI_CMR5 PB LL_RI_UnmaskChannelDuringAcquisition\n
1662 * RI_CMR5 PC LL_RI_UnmaskChannelDuringAcquisition\n
1663 * RI_CMR5 PF LL_RI_UnmaskChannelDuringAcquisition\n
1664 * RI_CMR5 PG LL_RI_UnmaskChannelDuringAcquisition
1665 * @param Port This parameter can be one of the following values:
1666 * @arg @ref LL_RI_PORT_A
1667 * @arg @ref LL_RI_PORT_B
1668 * @arg @ref LL_RI_PORT_C
1669 * @arg @ref LL_RI_PORT_F (*)
1670 * @arg @ref LL_RI_PORT_G (*)
1671 *
1672 * (*) value not defined in all devices.
1673 * @param Pin This parameter can be a combination of the following values:
1674 * @arg @ref LL_RI_PIN_0
1675 * @arg @ref LL_RI_PIN_1
1676 * @arg @ref LL_RI_PIN_2
1677 * @arg @ref LL_RI_PIN_3
1678 * @arg @ref LL_RI_PIN_4
1679 * @arg @ref LL_RI_PIN_5
1680 * @arg @ref LL_RI_PIN_6
1681 * @arg @ref LL_RI_PIN_7
1682 * @arg @ref LL_RI_PIN_8
1683 * @arg @ref LL_RI_PIN_9
1684 * @arg @ref LL_RI_PIN_10
1685 * @arg @ref LL_RI_PIN_11
1686 * @arg @ref LL_RI_PIN_12
1687 * @arg @ref LL_RI_PIN_13
1688 * @arg @ref LL_RI_PIN_14
1689 * @arg @ref LL_RI_PIN_15
1690 * @arg @ref LL_RI_PIN_ALL
1691 * @retval None
1692 */
LL_RI_UnmaskChannelDuringAcquisition(uint32_t Port,uint32_t Pin)1693 __STATIC_INLINE void LL_RI_UnmaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin)
1694 {
1695 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2));
1696 SET_BIT(*reg, Pin);
1697 }
1698 #endif /* RI_CMR1_PA */
1699
1700 #if defined(RI_CICR1_PA)
1701 /**
1702 * @brief Identify channel for timer input capture
1703 * @rmtoll RI_CICR1 PA LL_RI_IdentifyChannelIO\n
1704 * RI_CICR1 PB LL_RI_IdentifyChannelIO\n
1705 * RI_CICR1 PC LL_RI_IdentifyChannelIO\n
1706 * RI_CICR1 PF LL_RI_IdentifyChannelIO\n
1707 * RI_CICR1 PG LL_RI_IdentifyChannelIO\n
1708 * RI_CICR2 PA LL_RI_IdentifyChannelIO\n
1709 * RI_CICR2 PB LL_RI_IdentifyChannelIO\n
1710 * RI_CICR2 PC LL_RI_IdentifyChannelIO\n
1711 * RI_CICR2 PF LL_RI_IdentifyChannelIO\n
1712 * RI_CICR2 PG LL_RI_IdentifyChannelIO\n
1713 * RI_CICR3 PA LL_RI_IdentifyChannelIO\n
1714 * RI_CICR3 PB LL_RI_IdentifyChannelIO\n
1715 * RI_CICR3 PC LL_RI_IdentifyChannelIO\n
1716 * RI_CICR3 PF LL_RI_IdentifyChannelIO\n
1717 * RI_CICR3 PG LL_RI_IdentifyChannelIO\n
1718 * RI_CICR4 PA LL_RI_IdentifyChannelIO\n
1719 * RI_CICR4 PB LL_RI_IdentifyChannelIO\n
1720 * RI_CICR4 PC LL_RI_IdentifyChannelIO\n
1721 * RI_CICR4 PF LL_RI_IdentifyChannelIO\n
1722 * RI_CICR4 PG LL_RI_IdentifyChannelIO\n
1723 * RI_CICR5 PA LL_RI_IdentifyChannelIO\n
1724 * RI_CICR5 PB LL_RI_IdentifyChannelIO\n
1725 * RI_CICR5 PC LL_RI_IdentifyChannelIO\n
1726 * RI_CICR5 PF LL_RI_IdentifyChannelIO\n
1727 * RI_CICR5 PG LL_RI_IdentifyChannelIO
1728 * @param Port This parameter can be one of the following values:
1729 * @arg @ref LL_RI_PORT_A
1730 * @arg @ref LL_RI_PORT_B
1731 * @arg @ref LL_RI_PORT_C
1732 * @arg @ref LL_RI_PORT_F (*)
1733 * @arg @ref LL_RI_PORT_G (*)
1734 *
1735 * (*) value not defined in all devices.
1736 * @param Pin This parameter can be a combination of the following values:
1737 * @arg @ref LL_RI_PIN_0
1738 * @arg @ref LL_RI_PIN_1
1739 * @arg @ref LL_RI_PIN_2
1740 * @arg @ref LL_RI_PIN_3
1741 * @arg @ref LL_RI_PIN_4
1742 * @arg @ref LL_RI_PIN_5
1743 * @arg @ref LL_RI_PIN_6
1744 * @arg @ref LL_RI_PIN_7
1745 * @arg @ref LL_RI_PIN_8
1746 * @arg @ref LL_RI_PIN_9
1747 * @arg @ref LL_RI_PIN_10
1748 * @arg @ref LL_RI_PIN_11
1749 * @arg @ref LL_RI_PIN_12
1750 * @arg @ref LL_RI_PIN_13
1751 * @arg @ref LL_RI_PIN_14
1752 * @arg @ref LL_RI_PIN_15
1753 * @arg @ref LL_RI_PIN_ALL
1754 * @retval None
1755 */
LL_RI_IdentifyChannelIO(uint32_t Port,uint32_t Pin)1756 __STATIC_INLINE void LL_RI_IdentifyChannelIO(uint32_t Port, uint32_t Pin)
1757 {
1758 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2));
1759 CLEAR_BIT(*reg, Pin);
1760 }
1761 #endif /* RI_CICR1_PA */
1762
1763 #if defined(RI_CICR1_PA)
1764 /**
1765 * @brief Identify sampling capacitor for timer input capture
1766 * @rmtoll RI_CICR1 PA LL_RI_IdentifySamplingCapacitorIO\n
1767 * RI_CICR1 PB LL_RI_IdentifySamplingCapacitorIO\n
1768 * RI_CICR1 PC LL_RI_IdentifySamplingCapacitorIO\n
1769 * RI_CICR1 PF LL_RI_IdentifySamplingCapacitorIO\n
1770 * RI_CICR1 PG LL_RI_IdentifySamplingCapacitorIO\n
1771 * RI_CICR2 PA LL_RI_IdentifySamplingCapacitorIO\n
1772 * RI_CICR2 PB LL_RI_IdentifySamplingCapacitorIO\n
1773 * RI_CICR2 PC LL_RI_IdentifySamplingCapacitorIO\n
1774 * RI_CICR2 PF LL_RI_IdentifySamplingCapacitorIO\n
1775 * RI_CICR2 PG LL_RI_IdentifySamplingCapacitorIO\n
1776 * RI_CICR3 PA LL_RI_IdentifySamplingCapacitorIO\n
1777 * RI_CICR3 PB LL_RI_IdentifySamplingCapacitorIO\n
1778 * RI_CICR3 PC LL_RI_IdentifySamplingCapacitorIO\n
1779 * RI_CICR3 PF LL_RI_IdentifySamplingCapacitorIO\n
1780 * RI_CICR3 PG LL_RI_IdentifySamplingCapacitorIO\n
1781 * RI_CICR4 PA LL_RI_IdentifySamplingCapacitorIO\n
1782 * RI_CICR4 PB LL_RI_IdentifySamplingCapacitorIO\n
1783 * RI_CICR4 PC LL_RI_IdentifySamplingCapacitorIO\n
1784 * RI_CICR4 PF LL_RI_IdentifySamplingCapacitorIO\n
1785 * RI_CICR4 PG LL_RI_IdentifySamplingCapacitorIO\n
1786 * RI_CICR5 PA LL_RI_IdentifySamplingCapacitorIO\n
1787 * RI_CICR5 PB LL_RI_IdentifySamplingCapacitorIO\n
1788 * RI_CICR5 PC LL_RI_IdentifySamplingCapacitorIO\n
1789 * RI_CICR5 PF LL_RI_IdentifySamplingCapacitorIO\n
1790 * RI_CICR5 PG LL_RI_IdentifySamplingCapacitorIO
1791 * @param Port This parameter can be one of the following values:
1792 * @arg @ref LL_RI_PORT_A
1793 * @arg @ref LL_RI_PORT_B
1794 * @arg @ref LL_RI_PORT_C
1795 * @arg @ref LL_RI_PORT_F (*)
1796 * @arg @ref LL_RI_PORT_G (*)
1797 *
1798 * (*) value not defined in all devices.
1799 * @param Pin This parameter can be a combination of the following values:
1800 * @arg @ref LL_RI_PIN_0
1801 * @arg @ref LL_RI_PIN_1
1802 * @arg @ref LL_RI_PIN_2
1803 * @arg @ref LL_RI_PIN_3
1804 * @arg @ref LL_RI_PIN_4
1805 * @arg @ref LL_RI_PIN_5
1806 * @arg @ref LL_RI_PIN_6
1807 * @arg @ref LL_RI_PIN_7
1808 * @arg @ref LL_RI_PIN_8
1809 * @arg @ref LL_RI_PIN_9
1810 * @arg @ref LL_RI_PIN_10
1811 * @arg @ref LL_RI_PIN_11
1812 * @arg @ref LL_RI_PIN_12
1813 * @arg @ref LL_RI_PIN_13
1814 * @arg @ref LL_RI_PIN_14
1815 * @arg @ref LL_RI_PIN_15
1816 * @arg @ref LL_RI_PIN_ALL
1817 * @retval None
1818 */
LL_RI_IdentifySamplingCapacitorIO(uint32_t Port,uint32_t Pin)1819 __STATIC_INLINE void LL_RI_IdentifySamplingCapacitorIO(uint32_t Port, uint32_t Pin)
1820 {
1821 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2));
1822 SET_BIT(*reg, Pin);
1823 }
1824 #endif /* RI_CICR1_PA */
1825
1826 /**
1827 * @}
1828 */
1829
1830 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1831 * @{
1832 */
1833
1834 /**
1835 * @brief Set FLASH Latency
1836 * @note Latetency can be modified only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess)
1837 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1838 * @param Latency This parameter can be one of the following values:
1839 * @arg @ref LL_FLASH_LATENCY_0
1840 * @arg @ref LL_FLASH_LATENCY_1
1841 * @retval None
1842 */
LL_FLASH_SetLatency(uint32_t Latency)1843 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1844 {
1845 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1846 }
1847
1848 /**
1849 * @brief Get FLASH Latency
1850 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1851 * @retval Returned value can be one of the following values:
1852 * @arg @ref LL_FLASH_LATENCY_0
1853 * @arg @ref LL_FLASH_LATENCY_1
1854 */
LL_FLASH_GetLatency(void)1855 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1856 {
1857 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1858 }
1859
1860 /**
1861 * @brief Enable Prefetch
1862 * @note Prefetch can be enabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess)
1863 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1864 * @retval None
1865 */
LL_FLASH_EnablePrefetch(void)1866 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1867 {
1868 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1869 }
1870
1871 /**
1872 * @brief Disable Prefetch
1873 * @note Prefetch can be disabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess)
1874 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1875 * @retval None
1876 */
LL_FLASH_DisablePrefetch(void)1877 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1878 {
1879 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1880 }
1881
1882 /**
1883 * @brief Check if Prefetch buffer is enabled
1884 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1885 * @retval State of bit (1 or 0).
1886 */
LL_FLASH_IsPrefetchEnabled(void)1887 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1888 {
1889 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == FLASH_ACR_PRFTEN) ? 1UL : 0UL);
1890 }
1891
1892 /**
1893 * @brief Enable 64-bit access
1894 * @rmtoll FLASH_ACR ACC64 LL_FLASH_Enable64bitAccess
1895 * @retval None
1896 */
LL_FLASH_Enable64bitAccess(void)1897 __STATIC_INLINE void LL_FLASH_Enable64bitAccess(void)
1898 {
1899 SET_BIT(FLASH->ACR, FLASH_ACR_ACC64);
1900 }
1901
1902 /**
1903 * @brief Disable 64-bit access
1904 * @rmtoll FLASH_ACR ACC64 LL_FLASH_Disable64bitAccess
1905 * @retval None
1906 */
LL_FLASH_Disable64bitAccess(void)1907 __STATIC_INLINE void LL_FLASH_Disable64bitAccess(void)
1908 {
1909 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ACC64);
1910 }
1911
1912 /**
1913 * @brief Check if 64-bit access is enabled
1914 * @rmtoll FLASH_ACR ACC64 LL_FLASH_Is64bitAccessEnabled
1915 * @retval State of bit (1 or 0).
1916 */
LL_FLASH_Is64bitAccessEnabled(void)1917 __STATIC_INLINE uint32_t LL_FLASH_Is64bitAccessEnabled(void)
1918 {
1919 return ((READ_BIT(FLASH->ACR, FLASH_ACR_ACC64) == FLASH_ACR_ACC64) ? 1UL : 0UL);
1920 }
1921
1922
1923 /**
1924 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
1925 * @note Flash memory can be put in power-down mode only when the code is executed
1926 * from RAM
1927 * @note Flash must not be accessed when power down is enabled
1928 * @note Flash must not be put in power-down while a program or an erase operation
1929 * is on-going
1930 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1931 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
1932 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
1933 * @retval None
1934 */
LL_FLASH_EnableRunPowerDown(void)1935 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1936 {
1937 /* Following values must be written consecutively to unlock the RUN_PD bit in
1938 FLASH_ACR */
1939 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1940 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1941 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1942 }
1943
1944 /**
1945 * @brief Disable Flash Power-down mode during run mode or Low-power run mode
1946 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
1947 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
1948 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
1949 * @retval None
1950 */
LL_FLASH_DisableRunPowerDown(void)1951 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
1952 {
1953 /* Following values must be written consecutively to unlock the RUN_PD bit in
1954 FLASH_ACR */
1955 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1956 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1957 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1958 }
1959
1960 /**
1961 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1962 * @note Flash must not be put in power-down while a program or an erase operation
1963 * is on-going
1964 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1965 * @retval None
1966 */
LL_FLASH_EnableSleepPowerDown(void)1967 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1968 {
1969 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1970 }
1971
1972 /**
1973 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1974 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1975 * @retval None
1976 */
LL_FLASH_DisableSleepPowerDown(void)1977 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1978 {
1979 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1980 }
1981
1982 /**
1983 * @}
1984 */
1985
1986 /**
1987 * @}
1988 */
1989
1990 /**
1991 * @}
1992 */
1993
1994 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) */
1995
1996 /**
1997 * @}
1998 */
1999
2000 #ifdef __cplusplus
2001 }
2002 #endif
2003
2004 #endif /* __STM32L1xx_LL_SYSTEM_H */
2005
2006 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2007