1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32L1xx_LL_RCC_H
22 #define __STM32L1xx_LL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l1xx.h"
30
31 /** @addtogroup STM32L1xx_LL_Driver
32 * @{
33 */
34
35 #if defined(RCC)
36
37 /** @defgroup RCC_LL RCC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /* Exported types ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
48 * @{
49 */
50
51 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
52 * @{
53 */
54
55 /**
56 * @brief RCC Clocks Frequency Structure
57 */
58 typedef struct
59 {
60 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
61 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
62 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
63 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
64 } LL_RCC_ClocksTypeDef;
65
66 /**
67 * @}
68 */
69
70 /**
71 * @}
72 */
73 #endif /* USE_FULL_LL_DRIVER */
74
75 /* Exported constants --------------------------------------------------------*/
76 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
77 * @{
78 */
79
80 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
81 * @brief Defines used to adapt values of different oscillators
82 * @note These values could be modified in the user environment according to
83 * HW set-up.
84 * @{
85 */
86 #if !defined (HSE_VALUE)
87 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
88 #endif /* HSE_VALUE */
89
90 #if !defined (HSI_VALUE)
91 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
92 #endif /* HSI_VALUE */
93
94 #if !defined (LSE_VALUE)
95 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
96 #endif /* LSE_VALUE */
97
98 #if !defined (LSI_VALUE)
99 #define LSI_VALUE 37000U /*!< Value of the LSI oscillator in Hz */
100 #endif /* LSI_VALUE */
101 /**
102 * @}
103 */
104
105 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
106 * @brief Flags defines which can be used with LL_RCC_WriteReg function
107 * @{
108 */
109 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
110 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
111 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
112 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
113 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
114 #define LL_RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC /*!< MSI Ready Interrupt Clear */
115 #if defined(RCC_LSECSS_SUPPORT)
116 #define LL_RCC_CIR_LSECSSC RCC_CIR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
117 #endif /* RCC_LSECSS_SUPPORT */
118 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
119 /**
120 * @}
121 */
122
123 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
124 * @brief Flags defines which can be used with LL_RCC_ReadReg function
125 * @{
126 */
127 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
128 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
129 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
130 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
131 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
132 #define LL_RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF /*!< MSI Ready Interrupt flag */
133 #if defined(RCC_LSECSS_SUPPORT)
134 #define LL_RCC_CIR_LSECSSF RCC_CIR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
135 #endif /* RCC_LSECSS_SUPPORT */
136 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
137 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
138 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
139 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
140 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
141 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
142 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
143 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
144 /**
145 * @}
146 */
147
148 /** @defgroup RCC_LL_EC_IT IT Defines
149 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
150 * @{
151 */
152 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
153 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
154 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
155 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
156 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
157 #define LL_RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE /*!< MSI Ready Interrupt Enable */
158 #if defined(RCC_LSECSS_SUPPORT)
159 #define LL_RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE /*!< LSE CSS Interrupt Enable */
160 #endif /* RCC_LSECSS_SUPPORT */
161 /**
162 * @}
163 */
164
165 /** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
166 * @{
167 */
168 #define LL_RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */
169 #define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */
170 #define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */
171 #define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */
172 /**
173 * @}
174 */
175
176 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
177 * @{
178 */
179 #define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
180 #define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz*/
181 #define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
182 #define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
183 #define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
184 #define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
185 #define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
186 /**
187 * @}
188 */
189
190 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
191 * @{
192 */
193 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
194 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
195 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
196 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
197 /**
198 * @}
199 */
200
201 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
202 * @{
203 */
204 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
205 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
206 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
207 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
208 /**
209 * @}
210 */
211
212 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
213 * @{
214 */
215 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
216 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
217 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
218 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
219 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
220 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
221 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
222 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
223 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
224 /**
225 * @}
226 */
227
228 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
229 * @{
230 */
231 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
232 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
233 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
234 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
235 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
236 /**
237 * @}
238 */
239
240 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
241 * @{
242 */
243 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
244 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
245 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
246 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
247 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
248 /**
249 * @}
250 */
251
252 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
253 * @{
254 */
255 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
256 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
257 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
258 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /*!< MSI selection as MCO source */
259 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
260 #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */
261 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */
262 #define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MCO source */
263 /**
264 * @}
265 */
266
267 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
268 * @{
269 */
270 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO Clock divided by 1 */
271 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
272 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */
273 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */
274 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
275 /**
276 * @}
277 */
278 #if defined(USE_FULL_LL_DRIVER)
279 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
280 * @{
281 */
282 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
283 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
284 /**
285 * @}
286 */
287 #endif /* USE_FULL_LL_DRIVER */
288
289
290
291 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
292 * @{
293 */
294 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
295 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
296 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
297 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by a programmable prescaler
298 (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
299 /**
300 * @}
301 */
302
303 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
304 * @{
305 */
306 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock * 3 */
307 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock * 4 */
308 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock * 6 */
309 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock * 8 */
310 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */
311 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */
312 #define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */
313 #define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */
314 #define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */
315 /**
316 * @}
317 */
318
319 /** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
320 * @{
321 */
322 #define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */
323 #define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */
324 #define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */
325 /**
326 * @}
327 */
328
329 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
330 * @{
331 */
332 #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
333 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
334 /**
335 * @}
336 */
337
338 /**
339 * @}
340 */
341
342 /* Exported macro ------------------------------------------------------------*/
343 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
344 * @{
345 */
346
347 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
348 * @{
349 */
350
351 /**
352 * @brief Write a value in RCC register
353 * @param __REG__ Register to be written
354 * @param __VALUE__ Value to be written in the register
355 * @retval None
356 */
357 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
358
359 /**
360 * @brief Read a value in RCC register
361 * @param __REG__ Register to be read
362 * @retval Register value
363 */
364 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
365 /**
366 * @}
367 */
368
369 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
370 * @{
371 */
372
373 /**
374 * @brief Helper macro to calculate the PLLCLK frequency
375 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
376 * @ref LL_RCC_PLL_GetMultiplicator (),
377 * @ref LL_RCC_PLL_GetDivider ());
378 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
379 * @param __PLLMUL__ This parameter can be one of the following values:
380 * @arg @ref LL_RCC_PLL_MUL_3
381 * @arg @ref LL_RCC_PLL_MUL_4
382 * @arg @ref LL_RCC_PLL_MUL_6
383 * @arg @ref LL_RCC_PLL_MUL_8
384 * @arg @ref LL_RCC_PLL_MUL_12
385 * @arg @ref LL_RCC_PLL_MUL_16
386 * @arg @ref LL_RCC_PLL_MUL_24
387 * @arg @ref LL_RCC_PLL_MUL_32
388 * @arg @ref LL_RCC_PLL_MUL_48
389 * @param __PLLDIV__ This parameter can be one of the following values:
390 * @arg @ref LL_RCC_PLL_DIV_2
391 * @arg @ref LL_RCC_PLL_DIV_3
392 * @arg @ref LL_RCC_PLL_DIV_4
393 * @retval PLL clock frequency (in Hz)
394 */
395 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_CFGR_PLLMUL_Pos]) / (((__PLLDIV__) >> RCC_CFGR_PLLDIV_Pos)+1U))
396
397 /**
398 * @brief Helper macro to calculate the HCLK frequency
399 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
400 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
401 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
402 * @param __AHBPRESCALER__ This parameter can be one of the following values:
403 * @arg @ref LL_RCC_SYSCLK_DIV_1
404 * @arg @ref LL_RCC_SYSCLK_DIV_2
405 * @arg @ref LL_RCC_SYSCLK_DIV_4
406 * @arg @ref LL_RCC_SYSCLK_DIV_8
407 * @arg @ref LL_RCC_SYSCLK_DIV_16
408 * @arg @ref LL_RCC_SYSCLK_DIV_64
409 * @arg @ref LL_RCC_SYSCLK_DIV_128
410 * @arg @ref LL_RCC_SYSCLK_DIV_256
411 * @arg @ref LL_RCC_SYSCLK_DIV_512
412 * @retval HCLK clock frequency (in Hz)
413 */
414 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
415
416 /**
417 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
418 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
419 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
420 * @param __HCLKFREQ__ HCLK frequency
421 * @param __APB1PRESCALER__ This parameter can be one of the following values:
422 * @arg @ref LL_RCC_APB1_DIV_1
423 * @arg @ref LL_RCC_APB1_DIV_2
424 * @arg @ref LL_RCC_APB1_DIV_4
425 * @arg @ref LL_RCC_APB1_DIV_8
426 * @arg @ref LL_RCC_APB1_DIV_16
427 * @retval PCLK1 clock frequency (in Hz)
428 */
429 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
430
431 /**
432 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
433 * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
434 * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
435 * @param __HCLKFREQ__ HCLK frequency
436 * @param __APB2PRESCALER__ This parameter can be one of the following values:
437 * @arg @ref LL_RCC_APB2_DIV_1
438 * @arg @ref LL_RCC_APB2_DIV_2
439 * @arg @ref LL_RCC_APB2_DIV_4
440 * @arg @ref LL_RCC_APB2_DIV_8
441 * @arg @ref LL_RCC_APB2_DIV_16
442 * @retval PCLK2 clock frequency (in Hz)
443 */
444 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
445
446 /**
447 * @brief Helper macro to calculate the MSI frequency (in Hz)
448 * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
449 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
450 * @param __MSIRANGE__ This parameter can be one of the following values:
451 * @arg @ref LL_RCC_MSIRANGE_0
452 * @arg @ref LL_RCC_MSIRANGE_1
453 * @arg @ref LL_RCC_MSIRANGE_2
454 * @arg @ref LL_RCC_MSIRANGE_3
455 * @arg @ref LL_RCC_MSIRANGE_4
456 * @arg @ref LL_RCC_MSIRANGE_5
457 * @arg @ref LL_RCC_MSIRANGE_6
458 * @retval MSI clock frequency (in Hz)
459 */
460 #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1UL << (((__MSIRANGE__) >> RCC_ICSCR_MSIRANGE_Pos) + 1U))))
461
462 /**
463 * @}
464 */
465
466 /**
467 * @}
468 */
469
470 /* Exported functions --------------------------------------------------------*/
471 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
472 * @{
473 */
474
475 /** @defgroup RCC_LL_EF_HSE HSE
476 * @{
477 */
478
479 /**
480 * @brief Enable the Clock Security System.
481 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
482 * @retval None
483 */
LL_RCC_HSE_EnableCSS(void)484 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
485 {
486 SET_BIT(RCC->CR, RCC_CR_CSSON);
487 }
488
489 /**
490 * @brief Disable the Clock Security System.
491 * @note Cannot be disabled in HSE is ready (only by hardware)
492 * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
493 * @retval None
494 */
LL_RCC_HSE_DisableCSS(void)495 __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
496 {
497 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
498 }
499
500 /**
501 * @brief Enable HSE external oscillator (HSE Bypass)
502 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
503 * @retval None
504 */
LL_RCC_HSE_EnableBypass(void)505 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
506 {
507 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
508 }
509
510 /**
511 * @brief Disable HSE external oscillator (HSE Bypass)
512 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
513 * @retval None
514 */
LL_RCC_HSE_DisableBypass(void)515 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
516 {
517 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
518 }
519
520 /**
521 * @brief Enable HSE crystal oscillator (HSE ON)
522 * @rmtoll CR HSEON LL_RCC_HSE_Enable
523 * @retval None
524 */
LL_RCC_HSE_Enable(void)525 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
526 {
527 SET_BIT(RCC->CR, RCC_CR_HSEON);
528 }
529
530 /**
531 * @brief Disable HSE crystal oscillator (HSE ON)
532 * @rmtoll CR HSEON LL_RCC_HSE_Disable
533 * @retval None
534 */
LL_RCC_HSE_Disable(void)535 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
536 {
537 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
538 }
539
540 /**
541 * @brief Check if HSE oscillator Ready
542 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
543 * @retval State of bit (1 or 0).
544 */
LL_RCC_HSE_IsReady(void)545 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
546 {
547 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
548 }
549
550 /**
551 * @brief Configure the RTC prescaler (divider)
552 * @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler
553 * @param Div This parameter can be one of the following values:
554 * @arg @ref LL_RCC_RTC_HSE_DIV_2
555 * @arg @ref LL_RCC_RTC_HSE_DIV_4
556 * @arg @ref LL_RCC_RTC_HSE_DIV_8
557 * @arg @ref LL_RCC_RTC_HSE_DIV_16
558 * @retval None
559 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)560 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
561 {
562 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
563 }
564
565 /**
566 * @brief Get the RTC divider (prescaler)
567 * @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler
568 * @retval Returned value can be one of the following values:
569 * @arg @ref LL_RCC_RTC_HSE_DIV_2
570 * @arg @ref LL_RCC_RTC_HSE_DIV_4
571 * @arg @ref LL_RCC_RTC_HSE_DIV_8
572 * @arg @ref LL_RCC_RTC_HSE_DIV_16
573 */
LL_RCC_GetRTC_HSEPrescaler(void)574 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
575 {
576 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
577 }
578
579 /**
580 * @}
581 */
582
583 /** @defgroup RCC_LL_EF_HSI HSI
584 * @{
585 */
586
587 /**
588 * @brief Enable HSI oscillator
589 * @rmtoll CR HSION LL_RCC_HSI_Enable
590 * @retval None
591 */
LL_RCC_HSI_Enable(void)592 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
593 {
594 SET_BIT(RCC->CR, RCC_CR_HSION);
595 }
596
597 /**
598 * @brief Disable HSI oscillator
599 * @rmtoll CR HSION LL_RCC_HSI_Disable
600 * @retval None
601 */
LL_RCC_HSI_Disable(void)602 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
603 {
604 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
605 }
606
607 /**
608 * @brief Check if HSI clock is ready
609 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
610 * @retval State of bit (1 or 0).
611 */
LL_RCC_HSI_IsReady(void)612 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
613 {
614 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
615 }
616
617 /**
618 * @brief Get HSI Calibration value
619 * @note When HSITRIM is written, HSICAL is updated with the sum of
620 * HSITRIM and the factory trim value
621 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
622 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
623 */
LL_RCC_HSI_GetCalibration(void)624 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
625 {
626 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
627 }
628
629 /**
630 * @brief Set HSI Calibration trimming
631 * @note user-programmable trimming value that is added to the HSICAL
632 * @note Default value is 16, which, when added to the HSICAL value,
633 * should trim the HSI to 16 MHz +/- 1 %
634 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
635 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
636 * @retval None
637 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)638 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
639 {
640 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
641 }
642
643 /**
644 * @brief Get HSI Calibration trimming
645 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
646 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
647 */
LL_RCC_HSI_GetCalibTrimming(void)648 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
649 {
650 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
651 }
652
653 /**
654 * @}
655 */
656
657 /** @defgroup RCC_LL_EF_LSE LSE
658 * @{
659 */
660
661 /**
662 * @brief Enable Low Speed External (LSE) crystal.
663 * @rmtoll CSR LSEON LL_RCC_LSE_Enable
664 * @retval None
665 */
LL_RCC_LSE_Enable(void)666 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
667 {
668 SET_BIT(RCC->CSR, RCC_CSR_LSEON);
669 }
670
671 /**
672 * @brief Disable Low Speed External (LSE) crystal.
673 * @rmtoll CSR LSEON LL_RCC_LSE_Disable
674 * @retval None
675 */
LL_RCC_LSE_Disable(void)676 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
677 {
678 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
679 }
680
681 /**
682 * @brief Enable external clock source (LSE bypass).
683 * @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass
684 * @retval None
685 */
LL_RCC_LSE_EnableBypass(void)686 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
687 {
688 SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
689 }
690
691 /**
692 * @brief Disable external clock source (LSE bypass).
693 * @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass
694 * @retval None
695 */
LL_RCC_LSE_DisableBypass(void)696 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
697 {
698 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
699 }
700
701 #if defined(RCC_LSECSS_SUPPORT)
702 /**
703 * @brief Enable Clock security system on LSE.
704 * @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS
705 * @retval None
706 */
LL_RCC_LSE_EnableCSS(void)707 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
708 {
709 SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
710 }
711
712 /**
713 * @brief Disable Clock security system on LSE.
714 * @note Clock security system can be disabled only after a LSE
715 * failure detection. In that case it MUST be disabled by software.
716 * @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS
717 * @retval None
718 */
LL_RCC_LSE_DisableCSS(void)719 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
720 {
721 CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
722 }
723
724 #endif /* RCC_LSECSS_SUPPORT */
725 /**
726 * @brief Check if LSE oscillator Ready
727 * @rmtoll CSR LSERDY LL_RCC_LSE_IsReady
728 * @retval State of bit (1 or 0).
729 */
LL_RCC_LSE_IsReady(void)730 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
731 {
732 return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL);
733 }
734
735 #if defined(RCC_LSECSS_SUPPORT)
736 /**
737 * @brief Check if CSS on LSE failure Detection
738 * @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected
739 * @retval State of bit (1 or 0).
740 */
LL_RCC_LSE_IsCSSDetected(void)741 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
742 {
743 return ((READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == RCC_CSR_LSECSSD) ? 1UL : 0UL);
744 }
745
746 #endif /* RCC_LSECSS_SUPPORT */
747 /**
748 * @}
749 */
750
751 /** @defgroup RCC_LL_EF_LSI LSI
752 * @{
753 */
754
755 /**
756 * @brief Enable LSI Oscillator
757 * @rmtoll CSR LSION LL_RCC_LSI_Enable
758 * @retval None
759 */
LL_RCC_LSI_Enable(void)760 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
761 {
762 SET_BIT(RCC->CSR, RCC_CSR_LSION);
763 }
764
765 /**
766 * @brief Disable LSI Oscillator
767 * @rmtoll CSR LSION LL_RCC_LSI_Disable
768 * @retval None
769 */
LL_RCC_LSI_Disable(void)770 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
771 {
772 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
773 }
774
775 /**
776 * @brief Check if LSI is Ready
777 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
778 * @retval State of bit (1 or 0).
779 */
LL_RCC_LSI_IsReady(void)780 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
781 {
782 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
783 }
784
785 /**
786 * @}
787 */
788
789 /** @defgroup RCC_LL_EF_MSI MSI
790 * @{
791 */
792
793 /**
794 * @brief Enable MSI oscillator
795 * @rmtoll CR MSION LL_RCC_MSI_Enable
796 * @retval None
797 */
LL_RCC_MSI_Enable(void)798 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
799 {
800 SET_BIT(RCC->CR, RCC_CR_MSION);
801 }
802
803 /**
804 * @brief Disable MSI oscillator
805 * @rmtoll CR MSION LL_RCC_MSI_Disable
806 * @retval None
807 */
LL_RCC_MSI_Disable(void)808 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
809 {
810 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
811 }
812
813 /**
814 * @brief Check if MSI oscillator Ready
815 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
816 * @retval State of bit (1 or 0).
817 */
LL_RCC_MSI_IsReady(void)818 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
819 {
820 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
821 }
822
823 /**
824 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
825 * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange
826 * @param Range This parameter can be one of the following values:
827 * @arg @ref LL_RCC_MSIRANGE_0
828 * @arg @ref LL_RCC_MSIRANGE_1
829 * @arg @ref LL_RCC_MSIRANGE_2
830 * @arg @ref LL_RCC_MSIRANGE_3
831 * @arg @ref LL_RCC_MSIRANGE_4
832 * @arg @ref LL_RCC_MSIRANGE_5
833 * @arg @ref LL_RCC_MSIRANGE_6
834 * @retval None
835 */
LL_RCC_MSI_SetRange(uint32_t Range)836 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
837 {
838 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
839 }
840
841 /**
842 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
843 * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange
844 * @retval Returned value can be one of the following values:
845 * @arg @ref LL_RCC_MSIRANGE_0
846 * @arg @ref LL_RCC_MSIRANGE_1
847 * @arg @ref LL_RCC_MSIRANGE_2
848 * @arg @ref LL_RCC_MSIRANGE_3
849 * @arg @ref LL_RCC_MSIRANGE_4
850 * @arg @ref LL_RCC_MSIRANGE_5
851 * @arg @ref LL_RCC_MSIRANGE_6
852 */
LL_RCC_MSI_GetRange(void)853 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
854 {
855 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
856 }
857
858 /**
859 * @brief Get MSI Calibration value
860 * @note When MSITRIM is written, MSICAL is updated with the sum of
861 * MSITRIM and the factory trim value
862 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
863 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
864 */
LL_RCC_MSI_GetCalibration(void)865 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
866 {
867 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
868 }
869
870 /**
871 * @brief Set MSI Calibration trimming
872 * @note user-programmable trimming value that is added to the MSICAL
873 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
874 * @param Value between Min_Data = 0x00 and Max_Data = 0xFF
875 * @retval None
876 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)877 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
878 {
879 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
880 }
881
882 /**
883 * @brief Get MSI Calibration trimming
884 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
885 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
886 */
LL_RCC_MSI_GetCalibTrimming(void)887 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
888 {
889 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
890 }
891
892 /**
893 * @}
894 */
895
896 /** @defgroup RCC_LL_EF_System System
897 * @{
898 */
899
900 /**
901 * @brief Configure the system clock source
902 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
903 * @param Source This parameter can be one of the following values:
904 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
905 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
906 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
907 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
908 * @retval None
909 */
LL_RCC_SetSysClkSource(uint32_t Source)910 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
911 {
912 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
913 }
914
915 /**
916 * @brief Get the system clock source
917 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
918 * @retval Returned value can be one of the following values:
919 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
920 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
921 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
922 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
923 */
LL_RCC_GetSysClkSource(void)924 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
925 {
926 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
927 }
928
929 /**
930 * @brief Set AHB prescaler
931 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
932 * @param Prescaler This parameter can be one of the following values:
933 * @arg @ref LL_RCC_SYSCLK_DIV_1
934 * @arg @ref LL_RCC_SYSCLK_DIV_2
935 * @arg @ref LL_RCC_SYSCLK_DIV_4
936 * @arg @ref LL_RCC_SYSCLK_DIV_8
937 * @arg @ref LL_RCC_SYSCLK_DIV_16
938 * @arg @ref LL_RCC_SYSCLK_DIV_64
939 * @arg @ref LL_RCC_SYSCLK_DIV_128
940 * @arg @ref LL_RCC_SYSCLK_DIV_256
941 * @arg @ref LL_RCC_SYSCLK_DIV_512
942 * @retval None
943 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)944 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
945 {
946 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
947 }
948
949 /**
950 * @brief Set APB1 prescaler
951 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
952 * @param Prescaler This parameter can be one of the following values:
953 * @arg @ref LL_RCC_APB1_DIV_1
954 * @arg @ref LL_RCC_APB1_DIV_2
955 * @arg @ref LL_RCC_APB1_DIV_4
956 * @arg @ref LL_RCC_APB1_DIV_8
957 * @arg @ref LL_RCC_APB1_DIV_16
958 * @retval None
959 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)960 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
961 {
962 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
963 }
964
965 /**
966 * @brief Set APB2 prescaler
967 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
968 * @param Prescaler This parameter can be one of the following values:
969 * @arg @ref LL_RCC_APB2_DIV_1
970 * @arg @ref LL_RCC_APB2_DIV_2
971 * @arg @ref LL_RCC_APB2_DIV_4
972 * @arg @ref LL_RCC_APB2_DIV_8
973 * @arg @ref LL_RCC_APB2_DIV_16
974 * @retval None
975 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)976 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
977 {
978 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
979 }
980
981 /**
982 * @brief Get AHB prescaler
983 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
984 * @retval Returned value can be one of the following values:
985 * @arg @ref LL_RCC_SYSCLK_DIV_1
986 * @arg @ref LL_RCC_SYSCLK_DIV_2
987 * @arg @ref LL_RCC_SYSCLK_DIV_4
988 * @arg @ref LL_RCC_SYSCLK_DIV_8
989 * @arg @ref LL_RCC_SYSCLK_DIV_16
990 * @arg @ref LL_RCC_SYSCLK_DIV_64
991 * @arg @ref LL_RCC_SYSCLK_DIV_128
992 * @arg @ref LL_RCC_SYSCLK_DIV_256
993 * @arg @ref LL_RCC_SYSCLK_DIV_512
994 */
LL_RCC_GetAHBPrescaler(void)995 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
996 {
997 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
998 }
999
1000 /**
1001 * @brief Get APB1 prescaler
1002 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1003 * @retval Returned value can be one of the following values:
1004 * @arg @ref LL_RCC_APB1_DIV_1
1005 * @arg @ref LL_RCC_APB1_DIV_2
1006 * @arg @ref LL_RCC_APB1_DIV_4
1007 * @arg @ref LL_RCC_APB1_DIV_8
1008 * @arg @ref LL_RCC_APB1_DIV_16
1009 */
LL_RCC_GetAPB1Prescaler(void)1010 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1011 {
1012 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1013 }
1014
1015 /**
1016 * @brief Get APB2 prescaler
1017 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1018 * @retval Returned value can be one of the following values:
1019 * @arg @ref LL_RCC_APB2_DIV_1
1020 * @arg @ref LL_RCC_APB2_DIV_2
1021 * @arg @ref LL_RCC_APB2_DIV_4
1022 * @arg @ref LL_RCC_APB2_DIV_8
1023 * @arg @ref LL_RCC_APB2_DIV_16
1024 */
LL_RCC_GetAPB2Prescaler(void)1025 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1026 {
1027 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1028 }
1029
1030 /**
1031 * @}
1032 */
1033
1034 /** @defgroup RCC_LL_EF_MCO MCO
1035 * @{
1036 */
1037
1038 /**
1039 * @brief Configure MCOx
1040 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
1041 * CFGR MCOPRE LL_RCC_ConfigMCO
1042 * @param MCOxSource This parameter can be one of the following values:
1043 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1044 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1045 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1046 * @arg @ref LL_RCC_MCO1SOURCE_MSI
1047 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1048 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1049 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1050 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1051 * @param MCOxPrescaler This parameter can be one of the following values:
1052 * @arg @ref LL_RCC_MCO1_DIV_1
1053 * @arg @ref LL_RCC_MCO1_DIV_2
1054 * @arg @ref LL_RCC_MCO1_DIV_4
1055 * @arg @ref LL_RCC_MCO1_DIV_8
1056 * @arg @ref LL_RCC_MCO1_DIV_16
1057 * @retval None
1058 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1059 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1060 {
1061 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1062 }
1063
1064 /**
1065 * @}
1066 */
1067
1068
1069
1070 /** @defgroup RCC_LL_EF_RTC RTC
1071 * @{
1072 */
1073
1074 /**
1075 * @brief Set RTC Clock Source
1076 * @note Once the RTC clock source has been selected, it cannot be changed any more unless
1077 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
1078 * set). The RTCRST bit can be used to reset them.
1079 * @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource
1080 * @param Source This parameter can be one of the following values:
1081 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1082 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1083 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1084 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
1085 * @retval None
1086 */
LL_RCC_SetRTCClockSource(uint32_t Source)1087 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1088 {
1089 MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
1090 }
1091
1092 /**
1093 * @brief Get RTC Clock Source
1094 * @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource
1095 * @retval Returned value can be one of the following values:
1096 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1097 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1098 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1099 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
1100 */
LL_RCC_GetRTCClockSource(void)1101 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1102 {
1103 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
1104 }
1105
1106 /**
1107 * @brief Enable RTC
1108 * @rmtoll CSR RTCEN LL_RCC_EnableRTC
1109 * @retval None
1110 */
LL_RCC_EnableRTC(void)1111 __STATIC_INLINE void LL_RCC_EnableRTC(void)
1112 {
1113 SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
1114 }
1115
1116 /**
1117 * @brief Disable RTC
1118 * @rmtoll CSR RTCEN LL_RCC_DisableRTC
1119 * @retval None
1120 */
LL_RCC_DisableRTC(void)1121 __STATIC_INLINE void LL_RCC_DisableRTC(void)
1122 {
1123 CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
1124 }
1125
1126 /**
1127 * @brief Check if RTC has been enabled or not
1128 * @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC
1129 * @retval State of bit (1 or 0).
1130 */
LL_RCC_IsEnabledRTC(void)1131 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
1132 {
1133 return ((READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == RCC_CSR_RTCEN) ? 1UL : 0UL);
1134 }
1135
1136 /**
1137 * @brief Force the Backup domain reset
1138 * @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset
1139 * @retval None
1140 */
LL_RCC_ForceBackupDomainReset(void)1141 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
1142 {
1143 SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
1144 }
1145
1146 /**
1147 * @brief Release the Backup domain reset
1148 * @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset
1149 * @retval None
1150 */
LL_RCC_ReleaseBackupDomainReset(void)1151 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
1152 {
1153 CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
1154 }
1155
1156 /**
1157 * @}
1158 */
1159
1160 /** @defgroup RCC_LL_EF_PLL PLL
1161 * @{
1162 */
1163
1164 /**
1165 * @brief Enable PLL
1166 * @rmtoll CR PLLON LL_RCC_PLL_Enable
1167 * @retval None
1168 */
LL_RCC_PLL_Enable(void)1169 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
1170 {
1171 SET_BIT(RCC->CR, RCC_CR_PLLON);
1172 }
1173
1174 /**
1175 * @brief Disable PLL
1176 * @note Cannot be disabled if the PLL clock is used as the system clock
1177 * @rmtoll CR PLLON LL_RCC_PLL_Disable
1178 * @retval None
1179 */
LL_RCC_PLL_Disable(void)1180 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
1181 {
1182 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
1183 }
1184
1185 /**
1186 * @brief Check if PLL Ready
1187 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
1188 * @retval State of bit (1 or 0).
1189 */
LL_RCC_PLL_IsReady(void)1190 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
1191 {
1192 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
1193 }
1194
1195 /**
1196 * @brief Configure PLL used for SYSCLK Domain
1197 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
1198 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
1199 * CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS
1200 * @param Source This parameter can be one of the following values:
1201 * @arg @ref LL_RCC_PLLSOURCE_HSI
1202 * @arg @ref LL_RCC_PLLSOURCE_HSE
1203 * @param PLLMul This parameter can be one of the following values:
1204 * @arg @ref LL_RCC_PLL_MUL_3
1205 * @arg @ref LL_RCC_PLL_MUL_4
1206 * @arg @ref LL_RCC_PLL_MUL_6
1207 * @arg @ref LL_RCC_PLL_MUL_8
1208 * @arg @ref LL_RCC_PLL_MUL_12
1209 * @arg @ref LL_RCC_PLL_MUL_16
1210 * @arg @ref LL_RCC_PLL_MUL_24
1211 * @arg @ref LL_RCC_PLL_MUL_32
1212 * @arg @ref LL_RCC_PLL_MUL_48
1213 * @param PLLDiv This parameter can be one of the following values:
1214 * @arg @ref LL_RCC_PLL_DIV_2
1215 * @arg @ref LL_RCC_PLL_DIV_3
1216 * @arg @ref LL_RCC_PLL_DIV_4
1217 * @retval None
1218 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLMul,uint32_t PLLDiv)1219 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
1220 {
1221 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv);
1222 }
1223
1224 /**
1225 * @brief Configure PLL clock source
1226 * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource
1227 * @param PLLSource This parameter can be one of the following values:
1228 * @arg @ref LL_RCC_PLLSOURCE_HSI
1229 * @arg @ref LL_RCC_PLLSOURCE_HSE
1230 * @retval None
1231 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)1232 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
1233 {
1234 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
1235 }
1236
1237 /**
1238 * @brief Get the oscillator used as PLL clock source.
1239 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
1240 * @retval Returned value can be one of the following values:
1241 * @arg @ref LL_RCC_PLLSOURCE_HSI
1242 * @arg @ref LL_RCC_PLLSOURCE_HSE
1243 */
LL_RCC_PLL_GetMainSource(void)1244 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
1245 {
1246 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
1247 }
1248
1249 /**
1250 * @brief Get PLL multiplication Factor
1251 * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
1252 * @retval Returned value can be one of the following values:
1253 * @arg @ref LL_RCC_PLL_MUL_3
1254 * @arg @ref LL_RCC_PLL_MUL_4
1255 * @arg @ref LL_RCC_PLL_MUL_6
1256 * @arg @ref LL_RCC_PLL_MUL_8
1257 * @arg @ref LL_RCC_PLL_MUL_12
1258 * @arg @ref LL_RCC_PLL_MUL_16
1259 * @arg @ref LL_RCC_PLL_MUL_24
1260 * @arg @ref LL_RCC_PLL_MUL_32
1261 * @arg @ref LL_RCC_PLL_MUL_48
1262 */
LL_RCC_PLL_GetMultiplicator(void)1263 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
1264 {
1265 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
1266 }
1267
1268 /**
1269 * @brief Get Division factor for the main PLL and other PLL
1270 * @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider
1271 * @retval Returned value can be one of the following values:
1272 * @arg @ref LL_RCC_PLL_DIV_2
1273 * @arg @ref LL_RCC_PLL_DIV_3
1274 * @arg @ref LL_RCC_PLL_DIV_4
1275 */
LL_RCC_PLL_GetDivider(void)1276 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
1277 {
1278 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
1279 }
1280
1281 /**
1282 * @}
1283 */
1284
1285 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
1286 * @{
1287 */
1288
1289 /**
1290 * @brief Clear LSI ready interrupt flag
1291 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
1292 * @retval None
1293 */
LL_RCC_ClearFlag_LSIRDY(void)1294 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
1295 {
1296 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
1297 }
1298
1299 /**
1300 * @brief Clear LSE ready interrupt flag
1301 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
1302 * @retval None
1303 */
LL_RCC_ClearFlag_LSERDY(void)1304 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
1305 {
1306 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
1307 }
1308
1309 /**
1310 * @brief Clear MSI ready interrupt flag
1311 * @rmtoll CIR MSIRDYC LL_RCC_ClearFlag_MSIRDY
1312 * @retval None
1313 */
LL_RCC_ClearFlag_MSIRDY(void)1314 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
1315 {
1316 SET_BIT(RCC->CIR, RCC_CIR_MSIRDYC);
1317 }
1318
1319 /**
1320 * @brief Clear HSI ready interrupt flag
1321 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
1322 * @retval None
1323 */
LL_RCC_ClearFlag_HSIRDY(void)1324 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
1325 {
1326 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
1327 }
1328
1329 /**
1330 * @brief Clear HSE ready interrupt flag
1331 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
1332 * @retval None
1333 */
LL_RCC_ClearFlag_HSERDY(void)1334 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
1335 {
1336 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
1337 }
1338
1339 /**
1340 * @brief Clear PLL ready interrupt flag
1341 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
1342 * @retval None
1343 */
LL_RCC_ClearFlag_PLLRDY(void)1344 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
1345 {
1346 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
1347 }
1348
1349 /**
1350 * @brief Clear Clock security system interrupt flag
1351 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
1352 * @retval None
1353 */
LL_RCC_ClearFlag_HSECSS(void)1354 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
1355 {
1356 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
1357 }
1358
1359 #if defined(RCC_LSECSS_SUPPORT)
1360 /**
1361 * @brief Clear LSE Clock security system interrupt flag
1362 * @rmtoll CIR LSECSSC LL_RCC_ClearFlag_LSECSS
1363 * @retval None
1364 */
LL_RCC_ClearFlag_LSECSS(void)1365 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
1366 {
1367 SET_BIT(RCC->CIR, RCC_CIR_LSECSSC);
1368 }
1369
1370 #endif /* RCC_LSECSS_SUPPORT */
1371 /**
1372 * @brief Check if LSI ready interrupt occurred or not
1373 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
1374 * @retval State of bit (1 or 0).
1375 */
LL_RCC_IsActiveFlag_LSIRDY(void)1376 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
1377 {
1378 return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == RCC_CIR_LSIRDYF) ? 1UL : 0UL);
1379 }
1380
1381 /**
1382 * @brief Check if LSE ready interrupt occurred or not
1383 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
1384 * @retval State of bit (1 or 0).
1385 */
LL_RCC_IsActiveFlag_LSERDY(void)1386 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
1387 {
1388 return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == RCC_CIR_LSERDYF) ? 1UL : 0UL);
1389 }
1390
1391 /**
1392 * @brief Check if MSI ready interrupt occurred or not
1393 * @rmtoll CIR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
1394 * @retval State of bit (1 or 0).
1395 */
LL_RCC_IsActiveFlag_MSIRDY(void)1396 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
1397 {
1398 return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYF) == RCC_CIR_MSIRDYF) ? 1UL : 0UL);
1399 }
1400
1401 /**
1402 * @brief Check if HSI ready interrupt occurred or not
1403 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
1404 * @retval State of bit (1 or 0).
1405 */
LL_RCC_IsActiveFlag_HSIRDY(void)1406 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
1407 {
1408 return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == RCC_CIR_HSIRDYF) ? 1UL : 0UL);
1409 }
1410
1411 /**
1412 * @brief Check if HSE ready interrupt occurred or not
1413 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
1414 * @retval State of bit (1 or 0).
1415 */
LL_RCC_IsActiveFlag_HSERDY(void)1416 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
1417 {
1418 return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == RCC_CIR_HSERDYF) ? 1UL : 0UL);
1419 }
1420
1421 /**
1422 * @brief Check if PLL ready interrupt occurred or not
1423 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
1424 * @retval State of bit (1 or 0).
1425 */
LL_RCC_IsActiveFlag_PLLRDY(void)1426 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
1427 {
1428 return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == RCC_CIR_PLLRDYF) ? 1UL : 0UL);
1429 }
1430
1431 /**
1432 * @brief Check if Clock security system interrupt occurred or not
1433 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
1434 * @retval State of bit (1 or 0).
1435 */
LL_RCC_IsActiveFlag_HSECSS(void)1436 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
1437 {
1438 return ((READ_BIT(RCC->CIR, RCC_CIR_CSSF) == RCC_CIR_CSSF) ? 1UL : 0UL);
1439 }
1440
1441 #if defined(RCC_LSECSS_SUPPORT)
1442 /**
1443 * @brief Check if LSE Clock security system interrupt occurred or not
1444 * @rmtoll CIR LSECSSF LL_RCC_IsActiveFlag_LSECSS
1445 * @retval State of bit (1 or 0).
1446 */
LL_RCC_IsActiveFlag_LSECSS(void)1447 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
1448 {
1449 return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSF) == RCC_CIR_LSECSSF) ? 1UL : 0UL);
1450 }
1451 #endif /* RCC_LSECSS_SUPPORT */
1452
1453 /**
1454 * @brief Check if RCC flag Independent Watchdog reset is set or not.
1455 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
1456 * @retval State of bit (1 or 0).
1457 */
LL_RCC_IsActiveFlag_IWDGRST(void)1458 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
1459 {
1460 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
1461 }
1462
1463 /**
1464 * @brief Check if RCC flag Low Power reset is set or not.
1465 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
1466 * @retval State of bit (1 or 0).
1467 */
LL_RCC_IsActiveFlag_LPWRRST(void)1468 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
1469 {
1470 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
1471 }
1472
1473 /**
1474 * @brief Check if RCC flag is set or not.
1475 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
1476 * @retval State of bit (1 or 0).
1477 */
LL_RCC_IsActiveFlag_OBLRST(void)1478 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
1479 {
1480 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
1481 }
1482
1483 /**
1484 * @brief Check if RCC flag Pin reset is set or not.
1485 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
1486 * @retval State of bit (1 or 0).
1487 */
LL_RCC_IsActiveFlag_PINRST(void)1488 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
1489 {
1490 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
1491 }
1492
1493 /**
1494 * @brief Check if RCC flag POR/PDR reset is set or not.
1495 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
1496 * @retval State of bit (1 or 0).
1497 */
LL_RCC_IsActiveFlag_PORRST(void)1498 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
1499 {
1500 return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == RCC_CSR_PORRSTF) ? 1UL : 0UL);
1501 }
1502
1503 /**
1504 * @brief Check if RCC flag Software reset is set or not.
1505 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
1506 * @retval State of bit (1 or 0).
1507 */
LL_RCC_IsActiveFlag_SFTRST(void)1508 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
1509 {
1510 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
1511 }
1512
1513 /**
1514 * @brief Check if RCC flag Window Watchdog reset is set or not.
1515 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
1516 * @retval State of bit (1 or 0).
1517 */
LL_RCC_IsActiveFlag_WWDGRST(void)1518 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
1519 {
1520 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
1521 }
1522
1523 /**
1524 * @brief Set RMVF bit to clear the reset flags.
1525 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
1526 * @retval None
1527 */
LL_RCC_ClearResetFlags(void)1528 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
1529 {
1530 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
1531 }
1532
1533 /**
1534 * @}
1535 */
1536
1537 /** @defgroup RCC_LL_EF_IT_Management IT Management
1538 * @{
1539 */
1540
1541 /**
1542 * @brief Enable LSI ready interrupt
1543 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
1544 * @retval None
1545 */
LL_RCC_EnableIT_LSIRDY(void)1546 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
1547 {
1548 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
1549 }
1550
1551 /**
1552 * @brief Enable LSE ready interrupt
1553 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
1554 * @retval None
1555 */
LL_RCC_EnableIT_LSERDY(void)1556 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
1557 {
1558 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
1559 }
1560
1561 /**
1562 * @brief Enable MSI ready interrupt
1563 * @rmtoll CIR MSIRDYIE LL_RCC_EnableIT_MSIRDY
1564 * @retval None
1565 */
LL_RCC_EnableIT_MSIRDY(void)1566 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
1567 {
1568 SET_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
1569 }
1570
1571 /**
1572 * @brief Enable HSI ready interrupt
1573 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
1574 * @retval None
1575 */
LL_RCC_EnableIT_HSIRDY(void)1576 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
1577 {
1578 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
1579 }
1580
1581 /**
1582 * @brief Enable HSE ready interrupt
1583 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
1584 * @retval None
1585 */
LL_RCC_EnableIT_HSERDY(void)1586 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
1587 {
1588 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
1589 }
1590
1591 /**
1592 * @brief Enable PLL ready interrupt
1593 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
1594 * @retval None
1595 */
LL_RCC_EnableIT_PLLRDY(void)1596 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
1597 {
1598 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
1599 }
1600
1601 #if defined(RCC_LSECSS_SUPPORT)
1602 /**
1603 * @brief Enable LSE clock security system interrupt
1604 * @rmtoll CIR LSECSSIE LL_RCC_EnableIT_LSECSS
1605 * @retval None
1606 */
LL_RCC_EnableIT_LSECSS(void)1607 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
1608 {
1609 SET_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
1610 }
1611 #endif /* RCC_LSECSS_SUPPORT */
1612
1613 /**
1614 * @brief Disable LSI ready interrupt
1615 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
1616 * @retval None
1617 */
LL_RCC_DisableIT_LSIRDY(void)1618 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
1619 {
1620 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
1621 }
1622
1623 /**
1624 * @brief Disable LSE ready interrupt
1625 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
1626 * @retval None
1627 */
LL_RCC_DisableIT_LSERDY(void)1628 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
1629 {
1630 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
1631 }
1632
1633 /**
1634 * @brief Disable MSI ready interrupt
1635 * @rmtoll CIR MSIRDYIE LL_RCC_DisableIT_MSIRDY
1636 * @retval None
1637 */
LL_RCC_DisableIT_MSIRDY(void)1638 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
1639 {
1640 CLEAR_BIT(RCC->CIR, RCC_CIR_MSIRDYIE);
1641 }
1642
1643 /**
1644 * @brief Disable HSI ready interrupt
1645 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
1646 * @retval None
1647 */
LL_RCC_DisableIT_HSIRDY(void)1648 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
1649 {
1650 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
1651 }
1652
1653 /**
1654 * @brief Disable HSE ready interrupt
1655 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
1656 * @retval None
1657 */
LL_RCC_DisableIT_HSERDY(void)1658 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
1659 {
1660 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
1661 }
1662
1663 /**
1664 * @brief Disable PLL ready interrupt
1665 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
1666 * @retval None
1667 */
LL_RCC_DisableIT_PLLRDY(void)1668 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
1669 {
1670 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
1671 }
1672
1673 #if defined(RCC_LSECSS_SUPPORT)
1674 /**
1675 * @brief Disable LSE clock security system interrupt
1676 * @rmtoll CIR LSECSSIE LL_RCC_DisableIT_LSECSS
1677 * @retval None
1678 */
LL_RCC_DisableIT_LSECSS(void)1679 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
1680 {
1681 CLEAR_BIT(RCC->CIR, RCC_CIR_LSECSSIE);
1682 }
1683 #endif /* RCC_LSECSS_SUPPORT */
1684
1685 /**
1686 * @brief Checks if LSI ready interrupt source is enabled or disabled.
1687 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
1688 * @retval State of bit (1 or 0).
1689 */
LL_RCC_IsEnabledIT_LSIRDY(void)1690 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
1691 {
1692 return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == RCC_CIR_LSIRDYIE) ? 1UL : 0UL);
1693 }
1694
1695 /**
1696 * @brief Checks if LSE ready interrupt source is enabled or disabled.
1697 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
1698 * @retval State of bit (1 or 0).
1699 */
LL_RCC_IsEnabledIT_LSERDY(void)1700 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
1701 {
1702 return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == RCC_CIR_LSERDYIE) ? 1UL : 0UL);
1703 }
1704
1705 /**
1706 * @brief Checks if MSI ready interrupt source is enabled or disabled.
1707 * @rmtoll CIR MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
1708 * @retval State of bit (1 or 0).
1709 */
LL_RCC_IsEnabledIT_MSIRDY(void)1710 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
1711 {
1712 return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYIE) == RCC_CIR_MSIRDYIE) ? 1UL : 0UL);
1713 }
1714
1715 /**
1716 * @brief Checks if HSI ready interrupt source is enabled or disabled.
1717 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
1718 * @retval State of bit (1 or 0).
1719 */
LL_RCC_IsEnabledIT_HSIRDY(void)1720 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
1721 {
1722 return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == RCC_CIR_HSIRDYIE) ? 1UL : 0UL);
1723 }
1724
1725 /**
1726 * @brief Checks if HSE ready interrupt source is enabled or disabled.
1727 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
1728 * @retval State of bit (1 or 0).
1729 */
LL_RCC_IsEnabledIT_HSERDY(void)1730 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
1731 {
1732 return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == RCC_CIR_HSERDYIE) ? 1UL : 0UL);
1733 }
1734
1735 /**
1736 * @brief Checks if PLL ready interrupt source is enabled or disabled.
1737 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
1738 * @retval State of bit (1 or 0).
1739 */
LL_RCC_IsEnabledIT_PLLRDY(void)1740 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
1741 {
1742 return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == RCC_CIR_PLLRDYIE) ? 1UL : 0UL);
1743 }
1744
1745 #if defined(RCC_LSECSS_SUPPORT)
1746 /**
1747 * @brief Checks if LSECSS interrupt source is enabled or disabled.
1748 * @rmtoll CIR LSECSSIE LL_RCC_IsEnabledIT_LSECSS
1749 * @retval State of bit (1 or 0).
1750 */
LL_RCC_IsEnabledIT_LSECSS(void)1751 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
1752 {
1753 return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSIE) == RCC_CIR_LSECSSIE) ? 1UL : 0UL);
1754 }
1755 #endif /* RCC_LSECSS_SUPPORT */
1756
1757 /**
1758 * @}
1759 */
1760
1761 #if defined(USE_FULL_LL_DRIVER)
1762 /** @defgroup RCC_LL_EF_Init De-initialization function
1763 * @{
1764 */
1765 ErrorStatus LL_RCC_DeInit(void);
1766 /**
1767 * @}
1768 */
1769
1770 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
1771 * @{
1772 */
1773 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
1774 /**
1775 * @}
1776 */
1777 #endif /* USE_FULL_LL_DRIVER */
1778
1779 /**
1780 * @}
1781 */
1782
1783 /**
1784 * @}
1785 */
1786
1787 #endif /* RCC */
1788
1789 /**
1790 * @}
1791 */
1792
1793 #ifdef __cplusplus
1794 }
1795 #endif
1796
1797 #endif /* __STM32L1xx_LL_RCC_H */
1798
1799 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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