1 /**
2 ******************************************************************************
3 * @file tae32f53xx_ll_sysctrl.c
4 * @author MCD Application Team
5 * @brief SYSCTRL LL Module Driver.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© Copyright (c) 2020 Tai-Action.
11 * All rights reserved.</center></h2>
12 *
13 * This software is licensed by Tai-Action under BSD 3-Clause license,
14 * the "License"; You may not use this file except in compliance with the
15 * License. You may obtain a copy of the License at:
16 * opensource.org/licenses/BSD-3-Clause
17 *
18 ******************************************************************************
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "tae32f53xx_ll.h"
23
24
25 #define DBG_TAG "SYSCTRL"
26 #define DBG_LVL DBG_ERROR
27 #include "dbg/tae32f53xx_dbg.h"
28
29
30 /** @addtogroup TAE32F53xx_LL_Driver
31 * @{
32 */
33
34 /** @defgroup SYSCTRL_LL SYSCTRL LL
35 * @brief SYSCTRL LL Module Driver
36 * @{
37 */
38
39
40 /* Private define ------------------------------------------------------------*/
41 /* Private typedef -----------------------------------------------------------*/
42 /** @defgroup SYSCTRL_LL_Private_Types SYSCTRL LL Private Types
43 * @brief SYSCTRL LL Private Types
44 * @{
45 */
46
47 /**
48 * @brief SYSCTRL PLL0/1/2 Config Type Define
49 * @note pll_out_freq is before PLL Post Div
50 */
51 typedef struct __SYSCTRL_PLLCfgTypedef {
52 uint32_t pll_in_freq; /*!< PLL Input Freq */
53 uint32_t pll_out_freq; /*!< PLL Output Freq */
54 uint8_t pll_pre_div; /*!< PLL Pre-Div */
55 uint16_t fpll_int; /*!< FPLL Integer */
56 uint16_t fpll_frac; /*!< FPLL Fraction */
57 uint32_t pll_vco_band; /*!< PLL VCO Band */
58 uint32_t pll_vco_gain; /*!< PLL VCO Gain */
59 } SYSCTRL_PLLCfgTypedef;
60
61 /**
62 * @}
63 */
64
65
66 /* Private macro -------------------------------------------------------------*/
67 /* Private variables ---------------------------------------------------------*/
68 /** @defgroup SYSCTRL_LL_Private_Variables SYSCTRL LL Private Variables
69 * @brief SYSCTRL LL Private Variables
70 * @{
71 */
72
73 /**
74 * @brief SYSCLK PLL Config Const Array Definition
75 * @note VCO band&gain config are the same to PLL0/1/2
76 */
77 static const SYSCTRL_PLLCfgTypedef sysctrl_pll_cfg[] = {
78 {8000000, 100000000, 1, 6, 0x4000, SYSCTRL_PLL0_BAND_312M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->100M */
79 {8000000, 110000000, 1, 6, 0xe000, SYSCTRL_PLL0_BAND_312M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->110M */
80 {8000000, 120000000, 1, 7, 0x8000, SYSCTRL_PLL0_BAND_312M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->120M */
81 {8000000, 130000000, 1, 8, 0x2000, SYSCTRL_PLL0_BAND_312M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->130M */
82
83 {8000000, 140000000, 1, 8, 0xc000, SYSCTRL_PLL0_BAND_396M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->140M */
84 {8000000, 150000000, 1, 9, 0x6000, SYSCTRL_PLL0_BAND_396M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->150M */
85 {8000000, 160000000, 1, 10, 0, SYSCTRL_PLL0_BAND_396M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->160M */
86 {8000000, 170000000, 1, 10, 0xa000, SYSCTRL_PLL0_BAND_396M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->170M */
87
88 {8000000, 180000000, 1, 11, 0x4000, SYSCTRL_PLL0_BAND_466M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->180M */
89 {8000000, 190000000, 1, 11, 0xe000, SYSCTRL_PLL0_BAND_466M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->190M */
90 {8000000, 200000000, 1, 12, 0x8000, SYSCTRL_PLL0_BAND_466M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->200M */
91
92 {8000000, 210000000, 1, 13, 0x2000, SYSCTRL_PLL0_BAND_520M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->210M */
93 {8000000, 220000000, 1, 13, 0xc000, SYSCTRL_PLL0_BAND_520M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->220M */
94 {8000000, 230000000, 1, 14, 0x6000, SYSCTRL_PLL0_BAND_520M, SYSCTRL_PLL0_GVCO_2}, /*!<PLL0In->8M,PLL0Out->230M */
95 };
96
97 /**
98 * @}
99 */
100
101
102 /* Private function prototypes -----------------------------------------------*/
103 /** @defgroup SYSCTRL_LL_Private_Functions SYSCTRL LL Private Functions
104 * @brief SYSCTRL LL Private Functions
105 * @{
106 */
107 static void LL_SYSCTRL_XOSCCfg(SYSCTRL_TypeDef *Instance);
108 /**
109 * @}
110 */
111
112
113 /* Exported functions --------------------------------------------------------*/
114 /** @defgroup SYSCTRL_LL_Exported_Functions SYSCTRL LL Exported Functions
115 * @brief SYSCTRL LL Exported Functions
116 * @{
117 */
118
119 /** @defgroup SYSCTRL_LL_Exported_Functions_Group1 SYSCTRL Clock Config Functions
120 * @brief SYSCTRL Clock Config Functions
121 * @{
122 */
123
124 /**
125 * @brief SYSCTRL LL SYSCLK Init
126 * @param Instance Specifies SYSCTRL peripheral
127 * @param sysclk_cfg SYSCLK Config Pointer
128 * @return Status of the Initialization
129 */
LL_SYSCTRL_SysclkInit(SYSCTRL_TypeDef * Instance,SYSCTRL_SysclkUserCfgTypeDef * sysclk_cfg)130 LL_StatusETypeDef LL_SYSCTRL_SysclkInit(SYSCTRL_TypeDef *Instance, SYSCTRL_SysclkUserCfgTypeDef *sysclk_cfg)
131 {
132 uint16_t sysclk_div, remain;
133 SYSCTRL_PLLUserCfgTypeDef pll0_cfg;
134 LL_StatusETypeDef ret = LL_ERROR;
135
136 //Check params to be valid
137 if (Instance == NULL || sysclk_cfg == NULL) {
138 LOG_E("SYSCLK init params error!\n");
139 return LL_ERROR;
140 }
141
142 assert_param(sysclk_cfg->sysclk_freq);
143
144 //Auto Freq Config
145 if (sysclk_cfg->sysclk_src == SYSCLK_SRC_RC32K) { //SYSCLK Source RC32K
146 sysclk_cfg->sysclk_src_freq = LSI_VALUE;
147 } else if (sysclk_cfg->sysclk_src == SYSCLK_SRC_RC8M) { //SYSCLK Source RC8M
148 sysclk_cfg->sysclk_src_freq = HSI_VALUE;
149 } else if (sysclk_cfg->sysclk_src == SYSCLK_SRC_HOSC) { //SYSCLK Source HOSC
150 if (!sysclk_cfg->sysclk_src_freq) { //Hardware can AutoSwitch
151 sysclk_cfg->sysclk_src_freq = HSE_VALUE;
152 }
153 } else if (sysclk_cfg->sysclk_src == SYSCLK_SRC_PLL0DivClk) { //SYSCLK Source PLL0DivClk
154 if (sysclk_cfg->pll0clk_src == PLLCLK_SRC_XOSC) { //PLL0 CLK Source HOSC
155 if (!sysclk_cfg->pll0clk_src_freq) { //Hardware can AutoSwitch
156 sysclk_cfg->pll0clk_src_freq = HSE_VALUE;
157 }
158 } else if (sysclk_cfg->pll0clk_src == PLLCLK_SRC_RC8M) { //PLL0 CLK Source RC8M
159 sysclk_cfg->pll0clk_src_freq = HSI_VALUE;
160 }
161 }
162
163 //Check APB0/APB1 Clock Div to be valid
164 if (sysclk_cfg->apb0_clk_div == SYSCTRL_CLK_DIV_IVD) {
165 sysclk_cfg->apb0_clk_div = SYSCTRL_CLK_DIV_1;
166 }
167
168 if (sysclk_cfg->apb1_clk_div == SYSCTRL_CLK_DIV_IVD) {
169 sysclk_cfg->apb1_clk_div = SYSCTRL_CLK_DIV_1;
170 }
171
172 //Calculate SYSCLK division
173 if (sysclk_cfg->sysclk_src != SYSCLK_SRC_PLL0DivClk) {
174 sysclk_div = sysclk_cfg->sysclk_src_freq / sysclk_cfg->sysclk_freq;
175 remain = sysclk_cfg->sysclk_src_freq % sysclk_cfg->sysclk_freq;
176
177 if (!sysclk_div || remain) {
178 LOG_E("Can't division %d SYSCLK from %d Source CLK!\n", sysclk_cfg->sysclk_freq, sysclk_cfg->sysclk_src_freq);
179 return LL_ERROR;
180 }
181 }
182
183 //SYSCTRL CTRL Register Unlock
184 __LL_SYSCTRL_CTRLReg_Unlock(Instance);
185
186 //Config SYSCLK
187 switch (sysclk_cfg->sysclk_src) {
188 case SYSCLK_SRC_RC32K:
189 LOG_I("SYSCLK-[%d] source select RC32K.\n", sysclk_cfg->sysclk_freq);
190 __LL_SYSCTRL_SysClkSrc_Set(Instance, SYSCTRL_SYSCLK_SRC_RC32K);
191 __LL_SYSCTRL_SysClkDiv_Set(Instance, sysclk_div);
192 ret = LL_OK;
193 break;
194
195 case SYSCLK_SRC_RC8M:
196 LOG_I("SYSCLK-[%d] source select RC8M.\n", sysclk_cfg->sysclk_freq);
197 __LL_SYSCTRL_RC8M_En(Instance);
198 __LL_SYSCTRL_SysClkSrc_Set(Instance, SYSCTRL_SYSCLK_SRC_RC8M);
199 __LL_SYSCTRL_SysClkDiv_Set(Instance, sysclk_div);
200 ret = LL_OK;
201 break;
202
203 case SYSCLK_SRC_PLL0DivClk:
204 //SYSCLK PLL0 Config
205 pll0_cfg.pll_clk_src = sysclk_cfg->pll0clk_src;
206 pll0_cfg.pll_in_freq = sysclk_cfg->pll0clk_src_freq;
207 pll0_cfg.pll_user_freq = sysclk_cfg->sysclk_freq;
208 ret = LL_SYSCTRL_Pll0Cfg(Instance, &pll0_cfg);
209
210 //SYCTRL CTRL Reg Unlock because Pll0Cfg function has lock before return
211 __LL_SYSCTRL_CTRLReg_Unlock(Instance);
212
213 //SYSCLK Source Select PLL0DivClk, and SYSCLK Div set to default 1
214 if (ret == LL_OK) {
215 LOG_I("SYSCLK-[%d] source select PLL0DivClk.\n", sysclk_cfg->sysclk_freq);
216 __LL_SYSCTRL_SysClkSrc_Set(Instance, SYSCTRL_SYSCLK_SRC_PLLDivClk);
217 __LL_SYSCTRL_SysClkDiv_Set(Instance, SYSCTRL_CLK_DIV_1);
218 }
219
220 break;
221
222 case SYSCLK_SRC_HOSC:
223 LOG_I("SYSCLK-[%d] source select HOSC-[%d].\n", sysclk_cfg->sysclk_freq, sysclk_cfg->sysclk_src_freq);
224 LL_SYSCTRL_XOSCCfg(Instance);
225 __LL_SYSCTRL_SysClkSrc_Set(Instance, SYSCTRL_SYSCLK_SRC_HOSC);
226 __LL_SYSCTRL_SysClkDiv_Set(Instance, sysclk_div);
227 ret = LL_OK;
228 break;
229
230 default:
231 LOG_E("SYSCLK Source Select-[%d] Error!\n", sysclk_cfg->sysclk_src);
232 ret = LL_ERROR;
233 break;
234 }
235
236 if (ret == LL_OK) {
237 //APB0/APB1 Clock Div Config
238 __LL_SYSCTRL_APB0ClkDiv_Set(Instance, sysclk_cfg->apb0_clk_div);
239 __LL_SYSCTRL_APB1ClkDiv_Set(Instance, sysclk_cfg->apb1_clk_div);
240
241 //APB0/APB1/ABH0 Bus Clock Enable
242 __LL_SYSCTRL_APB0Clk_En(Instance);
243 __LL_SYSCTRL_APB1Clk_En(Instance);
244 __LL_SYSCTRL_AHBClk_En(Instance);
245
246 //APB0/APB1/ABH0 Soft Reset Release
247 __LL_SYSCTRL_APB0BusSoftRst_Release(Instance);
248 __LL_SYSCTRL_APB1BusSoftRst_Release(Instance);
249 __LL_SYSCTRL_AHBBusSoftRst_Release(Instance);
250
251 //RAM2/RAM1/RAM0 Bus Clock Enable
252 __LL_SYSCTRL_RAM2BusClk_En(Instance);
253 __LL_SYSCTRL_RAM1BusClk_En(Instance);
254 __LL_SYSCTRL_RAM0BusClk_En(Instance);
255 }
256
257 //SYSCTRL Register Lock
258 __LL_SYSCTRL_Reg_Lock(Instance);
259
260 return ret;
261 }
262
263 /**
264 * @brief SYSCTRL LL GPIOA Debounce Clock Config
265 * @param src GPIOA Debounce Clock Source
266 * @param div GPIOA Debounce Clock Div
267 * @return LL_StatusETypeDef
268 */
LL_SYSCTRL_GPIOA_DbcClkCfg(SYSCTRL_GPIOADbcClkSrcETypeDef src,SYSCTRL_ClkDivETypeDef div)269 LL_StatusETypeDef LL_SYSCTRL_GPIOA_DbcClkCfg(SYSCTRL_GPIOADbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
270 {
271 if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_256) {
272 LOG_E("GPIOA Debounce CLK div-[%d] config error!\n", div);
273 return LL_ERROR;
274 }
275
276 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
277 __LL_SYSCTRL_GPIOADbcSrc_Set(SYSCTRL, src);
278 __LL_SYSCTRL_GPIOADbcClkDiv_Set(SYSCTRL, div);
279 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
280
281 return LL_OK;
282 }
283
284 /**
285 * @brief SYSCTRL LL GPIOB Debounce Clock Config
286 * @param src GPIOB Debounce Clock Source
287 * @param div GPIOB Debounce Clock Div
288 * @return LL_StatusETypeDef
289 */
LL_SYSCTRL_GPIOB_DbcClkCfg(SYSCTRL_GPIOBDbcClkSrcETypeDef src,SYSCTRL_ClkDivETypeDef div)290 LL_StatusETypeDef LL_SYSCTRL_GPIOB_DbcClkCfg(SYSCTRL_GPIOBDbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
291 {
292 if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_256) {
293 LOG_E("GPIOB Debounce CLK div-[%d] config error!\n", div);
294 return LL_ERROR;
295 }
296
297 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
298 __LL_SYSCTRL_GPIOBDbcSrc_Set(SYSCTRL, src);
299 __LL_SYSCTRL_GPIOBDbcClkDiv_Set(SYSCTRL, div);
300 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
301
302 return LL_OK;
303 }
304
305 /**
306 * @brief SYSCTRL LL GPIOC Debounce Clock Config
307 * @param src GPIOC Debounce Clock Source
308 * @param div GPIOC Debounce Clock Div
309 * @return LL_StatusETypeDef
310 */
LL_SYSCTRL_GPIOC_DbcClkCfg(SYSCTRL_GPIOCDbcClkSrcETypeDef src,SYSCTRL_ClkDivETypeDef div)311 LL_StatusETypeDef LL_SYSCTRL_GPIOC_DbcClkCfg(SYSCTRL_GPIOCDbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
312 {
313 if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_256) {
314 LOG_E("GPIOC Debounce CLK div-[%d] config error!\n", div);
315 return LL_ERROR;
316 }
317
318 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
319 __LL_SYSCTRL_GPIOCDbcSrc_Set(SYSCTRL, src);
320 __LL_SYSCTRL_GPIOCDbcClkDiv_Set(SYSCTRL, div);
321 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
322
323 return LL_OK;
324 }
325
326 /**
327 * @brief SYSCTRL LL GPIOD Debounce Clock Config
328 * @param src GPIOD Debounce Clock Source
329 * @param div GPIOD Debounce Clock Div
330 * @return LL_StatusETypeDef
331 */
LL_SYSCTRL_GPIOD_DbcClkCfg(SYSCTRL_GPIODDbcClkSrcETypeDef src,SYSCTRL_ClkDivETypeDef div)332 LL_StatusETypeDef LL_SYSCTRL_GPIOD_DbcClkCfg(SYSCTRL_GPIODDbcClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
333 {
334 if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_256) {
335 LOG_E("GPIOD Debounce CLK div-[%d] config error!\n", div);
336 return LL_ERROR;
337 }
338
339 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
340 __LL_SYSCTRL_GPIODDbcSrc_Set(SYSCTRL, src);
341 __LL_SYSCTRL_GPIODDbcClkDiv_Set(SYSCTRL, div);
342 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
343
344 return LL_OK;
345 }
346
347 /**
348 * @brief SYSCTRL LL DFLASH Clock Config
349 * @param src DFLASH Clock Source
350 * @param div DFLASH Clock Div
351 * @return LL_StatusETypeDef
352 */
LL_SYSCTRL_DFLASH_ClkCfg(SYSCTRL_DflashClkSrcETypeDef src,SYSCTRL_ClkDivETypeDef div)353 LL_StatusETypeDef LL_SYSCTRL_DFLASH_ClkCfg(SYSCTRL_DflashClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
354 {
355 if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_16) {
356 LOG_E("DFLASH CLK div-[%d] config error!\n", div);
357 return LL_ERROR;
358 }
359
360 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
361 __LL_SYSCTRL_DFLASHMemClkSrc_Set(SYSCTRL, src);
362 __LL_SYSCTRL_DFLASHMemClkDiv_Set(SYSCTRL, div);
363 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
364
365 return LL_OK;
366 }
367
368 /**
369 * @brief SYSCTRL LL EFLASH Clock Config
370 * @param src EFLASH Clock Source
371 * @param div EFLASH Clock Div
372 * @return LL_StatusETypeDef
373 */
LL_SYSCTRL_EFLASH_ClkCfg(SYSCTRL_EflashClkSrcETypeDef src,SYSCTRL_ClkDivETypeDef div)374 LL_StatusETypeDef LL_SYSCTRL_EFLASH_ClkCfg(SYSCTRL_EflashClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
375 {
376 if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_16) {
377 LOG_E("EFLASH CLK div-[%d] config error!\n", div);
378 return LL_ERROR;
379 }
380
381 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
382 __LL_SYSCTRL_EFLASHMemClkSrc_Set(SYSCTRL, src);
383 __LL_SYSCTRL_EFLASHMemClkDiv_Set(SYSCTRL, div);
384 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
385
386 return LL_OK;
387 }
388
389 /**
390 * @brief SYSCTRL LL ADC Function Clock Config
391 * @param src ADC Function Clock Source
392 * @param div ADC Function Clock Div
393 * @return LL_StatusETypeDef
394 */
LL_SYSCTRL_ADC_FuncClkCfg(SYSCTRL_ADCFuncClkSrcETypeDef src,SYSCTRL_ClkDivETypeDef div)395 LL_StatusETypeDef LL_SYSCTRL_ADC_FuncClkCfg(SYSCTRL_ADCFuncClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
396 {
397 if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_4) {
398 LOG_E("ADC Function CLK div-[%d] config error!\n", div);
399 return LL_ERROR;
400 }
401
402 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
403 __LL_SYSCTRL_ADCFunClkSrc_Set(SYSCTRL, src);
404 __LL_SYSCTRL_ADCFunClkDiv_Set(SYSCTRL, div);
405 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
406
407 return LL_OK;
408 }
409
410 /**
411 * @brief SYSCTRL LL HRPWM Function Clock Config
412 * @param src HRPWM Function Clock Source
413 * @param div HRPWM Function Clock Div
414 * @return LL_StatusETypeDef
415 */
LL_SYSCTRL_HRPWM_FuncClkCfg(SYSCTRL_HRPWMFuncClkSrcETypeDef src,SYSCTRL_ClkDivETypeDef div)416 LL_StatusETypeDef LL_SYSCTRL_HRPWM_FuncClkCfg(SYSCTRL_HRPWMFuncClkSrcETypeDef src, SYSCTRL_ClkDivETypeDef div)
417 {
418 if (div <= SYSCTRL_CLK_DIV_IVD || div > SYSCTRL_CLK_DIV_4) {
419 LOG_E("HRPWM Function CLK div-[%d] config error!\n", div);
420 return LL_ERROR;
421 }
422
423 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
424 __LL_SYSCTRL_HRPWMFunClkSrc_Set(SYSCTRL, src);
425 __LL_SYSCTRL_HRPWMFunClkDiv_Set(SYSCTRL, div);
426 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
427
428 return LL_OK;
429 }
430
431 /**
432 * @brief SYSCTRL LL SYSCLK freq get
433 * @param None
434 * @return SYSCLK freq
435 */
LL_SYSCTRL_SysclkGet(void)436 uint32_t LL_SYSCTRL_SysclkGet(void)
437 {
438 return SystemCoreClock;
439 }
440
441 /**
442 * @brief SYSCTRL LL AHB Clock freq get
443 * @note AHB Clock is equal to SYSCLK
444 * @param None
445 * @return AHB Clock freq
446 */
LL_SYSCTRL_AHBClkGet(void)447 uint32_t LL_SYSCTRL_AHBClkGet(void)
448 {
449 return LL_SYSCTRL_SysclkGet();
450 }
451
452 /**
453 * @brief SYSCTRL LL APB0 Clock freq get
454 * @note APB0 Clock is Div from AHB
455 * @param None
456 * @return APB0 Clock freq
457 */
LL_SYSCTRL_APB0ClkGet(void)458 uint32_t LL_SYSCTRL_APB0ClkGet(void)
459 {
460 return LL_SYSCTRL_AHBClkGet() / __LL_SYSCTRL_APB0ClkDiv_Get(SYSCTRL);
461 }
462
463 /**
464 * @brief SYSCTRL LL APB1 Clock freq get
465 * @note APB1 Clock is Div from AHB
466 * @param None
467 * @return APB1 Clock freq
468 */
LL_SYSCTRL_APB1ClkGet(void)469 uint32_t LL_SYSCTRL_APB1ClkGet(void)
470 {
471 return LL_SYSCTRL_AHBClkGet() / __LL_SYSCTRL_APB1ClkDiv_Get(SYSCTRL);
472 }
473
474 /**
475 * @}
476 */
477
478
479 /** @defgroup SYSCTRL_LL_Exported_Functions_Group2 SYSCTRL PLL Config Functions
480 * @brief SYSCTRL PLL Config Functions
481 * @{
482 */
483
484 /**
485 * @brief SYSCTRL ll PLL0 Config
486 * @param Instance Specifies SYSCTRL peripheral
487 * @param pll0_cfg PLL0 Config Pointer
488 * @return LL_StatusETypeDef Config Result
489 */
LL_SYSCTRL_Pll0Cfg(SYSCTRL_TypeDef * Instance,SYSCTRL_PLLUserCfgTypeDef * pll0_cfg)490 LL_StatusETypeDef LL_SYSCTRL_Pll0Cfg(SYSCTRL_TypeDef *Instance, SYSCTRL_PLLUserCfgTypeDef *pll0_cfg)
491 {
492 uint8_t i, j;
493 SYSCTRL_ClkDivETypeDef post_div = SYSCTRL_CLK_DIV_IVD;
494
495 if (Instance == NULL || pll0_cfg == NULL) {
496 LOG_E("PLL0 config params error!\n");
497 return LL_ERROR;
498 }
499
500 for (i = 0; i < ARRAY_SIZE(sysctrl_pll_cfg); i++) {
501 if (sysctrl_pll_cfg[i].pll_in_freq == pll0_cfg->pll_in_freq) {
502 for (j = 2; j <= 16; j++) {
503 if ((sysctrl_pll_cfg[i].pll_out_freq / j) == pll0_cfg->pll_user_freq && \
504 !(sysctrl_pll_cfg[i].pll_out_freq % j)) {
505 post_div = (SYSCTRL_ClkDivETypeDef)j;
506 break;
507 }
508 }
509
510 if (post_div != SYSCTRL_CLK_DIV_IVD) {
511 break;
512 }
513 }
514 }
515
516 if (i == ARRAY_SIZE(sysctrl_pll_cfg)) {
517 LOG_E("Don't match pll0_in_freq-[%d] to generate pll0_out_freq-[%d], please add the config to sysctrl_pll_cfg array!\n", \
518 pll0_cfg->pll_in_freq, pll0_cfg->pll_user_freq);
519 return LL_ERROR;
520 }
521
522 //SYSCTRL CTRL Register Unlock
523 __LL_SYSCTRL_CTRLReg_Unlock(Instance);
524
525 switch (pll0_cfg->pll_clk_src) {
526 case PLLCLK_SRC_XOSC:
527 LL_SYSCTRL_XOSCCfg(Instance);
528
529 LOG_I("PLL0 CLK Source Select XOSC.\n");
530 __LL_SYSCTRL_PLL0_RefClk_Set(Instance, SYSCTRL_PLL0_REFCLK_XOSC);
531 break;
532
533 case PLLCLK_SRC_RC8M:
534 __LL_SYSCTRL_RC8M_En(Instance);
535
536 LOG_I("PLL0 CLK Source Select RC8M.\n");
537 __LL_SYSCTRL_PLL0_RefClk_Set(Instance, SYSCTRL_PLL0_REFCLK_RC8M);
538 break;
539
540 case PLLCLK_SRC_DFT:
541 LOG_I("PLL0 CLK Source Select DFT.\n");
542 __LL_SYSCTRL_PLL0_RefClk_Set(Instance, SYSCTRL_PLL0_REFCLK_DFT);
543 break;
544
545 default:
546 LOG_E("PLL0 CLK Source Select-[%d] Error!\n", pll0_cfg->pll_clk_src);
547 return LL_ERROR;
548 }
549
550 //PLL0 Pre-Div Config
551 if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_1) {
552 __LL_SYSCTRL_PLL0_PreDiv_1(Instance);
553 } else if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_2) {
554 __LL_SYSCTRL_PLL0_PreDiv_2(Instance);
555 } else {
556 LOG_E("PLL0 Pre-Div Config-[%d] Error!\n", sysctrl_pll_cfg[i].pll_pre_div);
557 }
558
559 //PLL0 Div Config
560 if (post_div >= SYSCTRL_CLK_DIV_2 && post_div <= SYSCTRL_CLK_DIV_16) {
561 __LL_SYSCTRL_PLL0_DIV_Set(Instance, post_div);
562 } else {
563 LOG_E("PLL0 Post Div Config-[%d] Error!\n", post_div);
564 }
565
566 //FPLL0 integer/fraction Config & Enable & Start
567 LL_FPLL_DivStart(FPLL0, sysctrl_pll_cfg[i].fpll_int, sysctrl_pll_cfg[i].fpll_frac);
568
569 //PLL0 VCO Band and Gain Config and Enable
570 __LL_SYSCTRL_PLL0_Band_Set(Instance, sysctrl_pll_cfg[i].pll_vco_band);
571 __LL_SYSCTRL_PLL0_GVCO_Set(Instance, sysctrl_pll_cfg[i].pll_vco_gain);
572 __LL_SYSCTRL_PLL0_En(Instance);
573
574 //Wait for PLL0 Lock
575 LOG_D("Wait for PLL0 lock output\n");
576
577 while (!__LL_SYSCTRL_PLL0_IsLocked(Instance))
578 ;
579
580 LOG_D("PLL0 lock Success\n");
581
582 //SYSCTRL Register Lock
583 __LL_SYSCTRL_Reg_Lock(Instance);
584
585 return LL_OK;
586 }
587
588 /**
589 * @brief SYSCTRL ll PLL1 Config
590 * @note PLL1 don't config post-div, which is used for ADC/HRPWM module generally
591 * @param Instance Specifies SYSCTRL peripheral
592 * @param pll1_cfg PLL1 Config Pointer
593 * @return LL_StatusETypeDef Config Result
594 */
LL_SYSCTRL_Pll1Cfg(SYSCTRL_TypeDef * Instance,SYSCTRL_PLLUserCfgTypeDef * pll1_cfg)595 LL_StatusETypeDef LL_SYSCTRL_Pll1Cfg(SYSCTRL_TypeDef *Instance, SYSCTRL_PLLUserCfgTypeDef *pll1_cfg)
596 {
597 uint8_t i;
598
599 if (Instance == NULL || pll1_cfg == NULL) {
600 LOG_E("PLL1 config params error!\n");
601 return LL_ERROR;
602 }
603
604 for (i = 0; i < ARRAY_SIZE(sysctrl_pll_cfg); i++) {
605 if (sysctrl_pll_cfg[i].pll_in_freq == pll1_cfg->pll_in_freq && \
606 sysctrl_pll_cfg[i].pll_out_freq == pll1_cfg->pll_user_freq) {
607 break;
608 }
609 }
610
611 if (i == ARRAY_SIZE(sysctrl_pll_cfg)) {
612 LOG_E("Don't match pll1_in_freq-[%d] to generate pll1_out_freq-[%d], please add the config to sysctrl_pll_cfg array!\n", \
613 pll1_cfg->pll_in_freq, pll1_cfg->pll_user_freq);
614 return LL_ERROR;
615 }
616
617 //SYSCTRL CTRL Register Unlock
618 __LL_SYSCTRL_CTRLReg_Unlock(Instance);
619
620 switch (pll1_cfg->pll_clk_src) {
621 case PLLCLK_SRC_XOSC:
622 LL_SYSCTRL_XOSCCfg(Instance);
623
624 LOG_I("PLL1 CLK Source Select XOSC.\n");
625 __LL_SYSCTRL_PLL1_RefClk_Set(Instance, SYSCTRL_PLL1_REFCLK_XOSC);
626 break;
627
628 case PLLCLK_SRC_RC8M:
629 __LL_SYSCTRL_RC8M_En(Instance);
630
631 LOG_I("PLL1 CLK Source Select RC8M.\n");
632 __LL_SYSCTRL_PLL1_RefClk_Set(Instance, SYSCTRL_PLL1_REFCLK_RC8M);
633 break;
634
635 case PLLCLK_SRC_DFT:
636 LOG_I("PLL1 CLK Source Select DFT.\n");
637 __LL_SYSCTRL_PLL1_RefClk_Set(Instance, SYSCTRL_PLL1_REFCLK_DFT);
638 break;
639
640 default:
641 LOG_E("PLL1 CLK Source Select-[%d] Error!\n", pll1_cfg->pll_clk_src);
642 return LL_ERROR;
643 }
644
645 //PLL1 Pre-Div Config
646 if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_1) {
647 __LL_SYSCTRL_PLL1_PreDiv_1(Instance);
648 } else if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_2) {
649 __LL_SYSCTRL_PLL1_PreDiv_2(Instance);
650 } else {
651 LOG_E("PLL1 Pre-Div Config-[%d] Error!\n", sysctrl_pll_cfg[i].pll_pre_div);
652 }
653
654 //FPLL1 integer/fraction Config & Enable & Start
655 LL_FPLL_DivStart(FPLL1, sysctrl_pll_cfg[i].fpll_int, sysctrl_pll_cfg[i].fpll_frac);
656
657 //PLL1 VCO Band and Gain Config and Enable
658 __LL_SYSCTRL_PLL1_Band_Set(Instance, sysctrl_pll_cfg[i].pll_vco_band);
659 __LL_SYSCTRL_PLL1_GVCO_Set(Instance, sysctrl_pll_cfg[i].pll_vco_gain);
660 __LL_SYSCTRL_PLL1_En(Instance);
661
662 //Wait for PLL1 Lock
663 LOG_D("Wait for PLL1 lock output\n");
664
665 while (!__LL_SYSCTRL_PLL1_IsLocked(Instance))
666 ;
667
668 LOG_D("PLL1 lock Success\n");
669
670 //SYSCTRL Register Lock
671 __LL_SYSCTRL_Reg_Lock(Instance);
672
673 return LL_OK;
674 }
675
676 /**
677 * @brief SYSCTRL ll PLL2 Config
678 * @param Instance Specifies SYSCTRL peripheral
679 * @param pll2_cfg PLL2 Config Pointer
680 * @return LL_StatusETypeDef Config Result
681 */
LL_SYSCTRL_Pll2Cfg(SYSCTRL_TypeDef * Instance,SYSCTRL_PLLUserCfgTypeDef * pll2_cfg)682 LL_StatusETypeDef LL_SYSCTRL_Pll2Cfg(SYSCTRL_TypeDef *Instance, SYSCTRL_PLLUserCfgTypeDef *pll2_cfg)
683 {
684 uint8_t i, j;
685 SYSCTRL_ClkDivETypeDef post_div = SYSCTRL_CLK_DIV_IVD;
686
687 if (Instance == NULL || pll2_cfg == NULL) {
688 LOG_E("PLL2 config params error!\n");
689 return LL_ERROR;
690 }
691
692 for (i = 0; i < ARRAY_SIZE(sysctrl_pll_cfg); i++) {
693 if (sysctrl_pll_cfg[i].pll_in_freq == pll2_cfg->pll_in_freq) {
694 for (j = 2; j <= 16; j++) {
695 if ((sysctrl_pll_cfg[i].pll_out_freq / j) == pll2_cfg->pll_user_freq && !(sysctrl_pll_cfg[i].pll_out_freq % j)) {
696 post_div = (SYSCTRL_ClkDivETypeDef)j;
697 break;
698 }
699 }
700
701 if (post_div != SYSCTRL_CLK_DIV_IVD) {
702 break;
703 }
704 }
705 }
706
707 if (i == ARRAY_SIZE(sysctrl_pll_cfg)) {
708 LOG_E("Don't match pll2_in_freq-[%d] to generate pll2_out_freq-[%d], please add the config to sysctrl_pll_cfg array!\n", \
709 pll2_cfg->pll_in_freq, pll2_cfg->pll_user_freq);
710 return LL_ERROR;
711 }
712
713 //SYSCTRL CTRL Register Unlock
714 __LL_SYSCTRL_CTRLReg_Unlock(Instance);
715
716 switch (pll2_cfg->pll_clk_src) {
717 case PLLCLK_SRC_XOSC:
718 LL_SYSCTRL_XOSCCfg(Instance);
719
720 LOG_I("PLL2 CLK Source Select XOSC.\n");
721 __LL_SYSCTRL_PLL2_RefClk_Set(Instance, SYSCTRL_PLL2_REFCLK_XOSC);
722 break;
723
724 case PLLCLK_SRC_RC8M:
725 __LL_SYSCTRL_RC8M_En(Instance);
726
727 LOG_I("PLL2 CLK Source Select RC8M.\n");
728 __LL_SYSCTRL_PLL2_RefClk_Set(Instance, SYSCTRL_PLL2_REFCLK_RC8M);
729 break;
730
731 case PLLCLK_SRC_DFT:
732 LOG_I("PLL2 CLK Source Select DFT.\n");
733 __LL_SYSCTRL_PLL2_RefClk_Set(Instance, SYSCTRL_PLL2_REFCLK_DFT);
734 break;
735
736 default:
737 LOG_E("PLL2 CLK Source Select-[%d] Error!\n", pll2_cfg->pll_clk_src);
738 return LL_ERROR;
739 }
740
741 //PLL2 Pre-Div Config
742 if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_1) {
743 __LL_SYSCTRL_PLL2_PreDiv_1(Instance);
744 } else if (sysctrl_pll_cfg[i].pll_pre_div == SYSCTRL_CLK_DIV_2) {
745 __LL_SYSCTRL_PLL2_PreDiv_2(Instance);
746 } else {
747 LOG_E("PLL2 Pre-Div Config-[%d] Error!\n", sysctrl_pll_cfg[i].pll_pre_div);
748 }
749
750 //PLL2 Div Config
751 if (post_div >= SYSCTRL_CLK_DIV_2 && post_div <= SYSCTRL_CLK_DIV_16) {
752 __LL_SYSCTRL_PLL2_DIV_Set(Instance, post_div);
753 } else {
754 LOG_E("PLL2 Post Div Config-[%d] Error!\n", post_div);
755 }
756
757 //FPLL2 integer/fraction Config & Enable & Start
758 LL_FPLL_DivStart(FPLL2, sysctrl_pll_cfg[i].fpll_int, sysctrl_pll_cfg[i].fpll_frac);
759
760 //PLL2 VCO Band and Gain Config and Enable
761 __LL_SYSCTRL_PLL2_Band_Set(Instance, sysctrl_pll_cfg[i].pll_vco_band);
762 __LL_SYSCTRL_PLL2_GVCO_Set(Instance, sysctrl_pll_cfg[i].pll_vco_gain);
763 __LL_SYSCTRL_PLL2_En(Instance);
764
765 //Wait for PLL2 Lock
766 LOG_D("Wait for PLL2 lock output\n");
767
768 while (!__LL_SYSCTRL_PLL2_IsLocked(Instance))
769 ;
770
771 LOG_D("PLL2 lock Success\n");
772
773 //SYSCTRL Register Lock
774 __LL_SYSCTRL_Reg_Lock(Instance);
775
776 return LL_OK;
777 }
778 /**
779 * @}
780 */
781
782 /** @defgroup SYSCTRL_LL_Exported_Functions_Group3 SYSCTRL Peripherals Clock and Reset control Functions
783 * @brief SYSCTRL Peripherals Clock and Reset control Functions
784 * @{
785 */
786
787 /**
788 * @brief SYSCTRL LSTIMER Bus Clock Enable and Reset Release
789 * @param None
790 * @return None
791 */
LL_SYSCTRL_LSTMR_ClkEnRstRelease(void)792 void LL_SYSCTRL_LSTMR_ClkEnRstRelease(void)
793 {
794 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
795 __LL_SYSCTRL_LSTIMERBusClk_En(SYSCTRL);
796 __LL_SYSCTRL_LSTIMERSoftRst_Release(SYSCTRL);
797 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
798 }
799
800 /**
801 * @brief SYSCTRL LSTIMER Bus Clock Disable and Reset Assert
802 * @param None
803 * @return None
804 */
LL_SYSCTRL_LSTMR_ClkDisRstAssert(void)805 void LL_SYSCTRL_LSTMR_ClkDisRstAssert(void)
806 {
807 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
808 __LL_SYSCTRL_LSTIMERBusClk_Dis(SYSCTRL);
809 __LL_SYSCTRL_LSTIMERSoftRst_Assert(SYSCTRL);
810 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
811 }
812
813 /**
814 * @brief SYSCTRL Uart1 Bus Clock Enable and Reset Release
815 * @param None
816 * @return None
817 */
LL_SYSCTRL_UART1_ClkEnRstRelease(void)818 void LL_SYSCTRL_UART1_ClkEnRstRelease(void)
819 {
820 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
821 __LL_SYSCTRL_UART1BusClk_En(SYSCTRL);
822 __LL_SYSCTRL_UART1SoftRst_Release(SYSCTRL);
823 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
824 }
825
826 /**
827 * @brief SYSCTRL Uart1 Bus Clock Disable and Reset Assert
828 * @param None
829 * @return None
830 */
LL_SYSCTRL_UART1_ClkDisRstAssert(void)831 void LL_SYSCTRL_UART1_ClkDisRstAssert(void)
832 {
833 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
834 __LL_SYSCTRL_UART1BusClk_Dis(SYSCTRL);
835 __LL_SYSCTRL_UART1SoftRst_Assert(SYSCTRL);
836 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
837 }
838
839 /**
840 * @brief SYSCTRL Uart0 Bus Clock Enable and Reset Release
841 * @param None
842 * @return None
843 */
LL_SYSCTRL_UART0_ClkEnRstRelease(void)844 void LL_SYSCTRL_UART0_ClkEnRstRelease(void)
845 {
846 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
847 __LL_SYSCTRL_UART0BusClk_En(SYSCTRL);
848 __LL_SYSCTRL_UART0SoftRst_Release(SYSCTRL);
849 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
850 }
851
852 /**
853 * @brief SYSCTRL Uart0 Bus Clock Disable and Reset Assert
854 * @param None
855 * @return None
856 */
LL_SYSCTRL_UART0_ClkDisRstAssert(void)857 void LL_SYSCTRL_UART0_ClkDisRstAssert(void)
858 {
859 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
860 __LL_SYSCTRL_UART0BusClk_Dis(SYSCTRL);
861 __LL_SYSCTRL_UART0SoftRst_Assert(SYSCTRL);
862 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
863 }
864
865 /**
866 * @brief SYSCTRL I2C1 Bus Clock Enable and Reset Release
867 * @param None
868 * @return None
869 */
LL_SYSCTRL_I2C1_ClkEnRstRelease(void)870 void LL_SYSCTRL_I2C1_ClkEnRstRelease(void)
871 {
872 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
873 __LL_SYSCTRL_I2C1BusClk_En(SYSCTRL);
874 __LL_SYSCTRL_I2C1SoftRst_Release(SYSCTRL);
875 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
876 }
877
878 /**
879 * @brief SYSCTRL I2C1 Bus Clock Disable and Reset Assert
880 * @param None
881 * @return None
882 */
LL_SYSCTRL_I2C1_ClkDisRstAssert(void)883 void LL_SYSCTRL_I2C1_ClkDisRstAssert(void)
884 {
885 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
886 __LL_SYSCTRL_I2C1BusClk_Dis(SYSCTRL);
887 __LL_SYSCTRL_I2C1SoftRst_Assert(SYSCTRL);
888 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
889 }
890
891 /**
892 * @brief SYSCTRL I2C0 Bus Clock Enable and Reset Release
893 * @param None
894 * @return None
895 */
LL_SYSCTRL_I2C0_ClkEnRstRelease(void)896 void LL_SYSCTRL_I2C0_ClkEnRstRelease(void)
897 {
898 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
899 __LL_SYSCTRL_I2C0BusClk_En(SYSCTRL);
900 __LL_SYSCTRL_I2C0SoftRst_Release(SYSCTRL);
901 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
902 }
903
904 /**
905 * @brief SYSCTRL I2C0 Bus Clock Disable and Reset Assert
906 * @param None
907 * @return None
908 */
LL_SYSCTRL_I2C0_ClkDisRstAssert(void)909 void LL_SYSCTRL_I2C0_ClkDisRstAssert(void)
910 {
911 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
912 __LL_SYSCTRL_I2C0BusClk_Dis(SYSCTRL);
913 __LL_SYSCTRL_I2C0SoftRst_Assert(SYSCTRL);
914 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
915 }
916
917 /**
918 * @brief SYSCTRL ECU Bus&Function Clock Enable and Reset Release
919 * @param None
920 * @return None
921 */
LL_SYSCTRL_ECU_ClkEnRstRelease(void)922 void LL_SYSCTRL_ECU_ClkEnRstRelease(void)
923 {
924 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
925 __LL_SYSCTRL_ECUBusClk_En(SYSCTRL);
926 __LL_SYSCTRL_ECUFunClk_En(SYSCTRL);
927 __LL_SYSCTRL_ECUSoftRst_Release(SYSCTRL);
928 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
929 }
930
931 /**
932 * @brief SYSCTRL ECU Bus&Function Clock Disable and Reset Assert
933 * @param None
934 * @return None
935 */
LL_SYSCTRL_ECU_ClkDisRstAssert(void)936 void LL_SYSCTRL_ECU_ClkDisRstAssert(void)
937 {
938 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
939 __LL_SYSCTRL_ECUBusClk_Dis(SYSCTRL);
940 __LL_SYSCTRL_ECUFunClk_Dis(SYSCTRL);
941 __LL_SYSCTRL_ECUSoftRst_Assert(SYSCTRL);
942 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
943 }
944
945 /**
946 * @brief SYSCTRL IIR4 Bus&Function Clock Enable and Reset Release
947 * @param None
948 * @return None
949 */
LL_SYSCTRL_IIR4_ClkEnRstRelease(void)950 void LL_SYSCTRL_IIR4_ClkEnRstRelease(void)
951 {
952 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
953 __LL_SYSCTRL_IIR4BusClk_En(SYSCTRL);
954 __LL_SYSCTRL_IIR4FunClk_En(SYSCTRL);
955 __LL_SYSCTRL_IIR4SoftRst_Release(SYSCTRL);
956 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
957 }
958
959 /**
960 * @brief SYSCTRL IIR4 Bus&Function Clock Disable and Reset Assert
961 * @param None
962 * @return None
963 */
LL_SYSCTRL_IIR4_ClkDisRstAssert(void)964 void LL_SYSCTRL_IIR4_ClkDisRstAssert(void)
965 {
966 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
967 __LL_SYSCTRL_IIR4BusClk_Dis(SYSCTRL);
968 __LL_SYSCTRL_IIR4FunClk_Dis(SYSCTRL);
969 __LL_SYSCTRL_IIR4SoftRst_Assert(SYSCTRL);
970 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
971 }
972
973 /**
974 * @brief SYSCTRL IIR3 Bus&Function Clock Enable and Reset Release
975 * @param None
976 * @return None
977 */
LL_SYSCTRL_IIR3_ClkEnRstRelease(void)978 void LL_SYSCTRL_IIR3_ClkEnRstRelease(void)
979 {
980 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
981 __LL_SYSCTRL_IIR3BusClk_En(SYSCTRL);
982 __LL_SYSCTRL_IIR3FunClk_En(SYSCTRL);
983 __LL_SYSCTRL_IIR3SoftRst_Release(SYSCTRL);
984 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
985 }
986
987 /**
988 * @brief SYSCTRL IIR3 Bus&Function Clock Disable and Reset Assert
989 * @param None
990 * @return None
991 */
LL_SYSCTRL_IIR3_ClkDisRstAssert(void)992 void LL_SYSCTRL_IIR3_ClkDisRstAssert(void)
993 {
994 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
995 __LL_SYSCTRL_IIR3BusClk_Dis(SYSCTRL);
996 __LL_SYSCTRL_IIR3FunClk_Dis(SYSCTRL);
997 __LL_SYSCTRL_IIR3SoftRst_Assert(SYSCTRL);
998 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
999 }
1000
1001 /**
1002 * @brief SYSCTRL IIR2 Bus&Function Clock Enable and Reset Release
1003 * @param None
1004 * @return None
1005 */
LL_SYSCTRL_IIR2_ClkEnRstRelease(void)1006 void LL_SYSCTRL_IIR2_ClkEnRstRelease(void)
1007 {
1008 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1009 __LL_SYSCTRL_IIR2BusClk_En(SYSCTRL);
1010 __LL_SYSCTRL_IIR2FunClk_En(SYSCTRL);
1011 __LL_SYSCTRL_IIR2SoftRst_Release(SYSCTRL);
1012 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1013 }
1014
1015 /**
1016 * @brief SYSCTRL IIR2 Bus&Function Clock Disable and Reset Assert
1017 * @param None
1018 * @return None
1019 */
LL_SYSCTRL_IIR2_ClkDisRstAssert(void)1020 void LL_SYSCTRL_IIR2_ClkDisRstAssert(void)
1021 {
1022 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1023 __LL_SYSCTRL_IIR2BusClk_Dis(SYSCTRL);
1024 __LL_SYSCTRL_IIR2FunClk_Dis(SYSCTRL);
1025 __LL_SYSCTRL_IIR2SoftRst_Assert(SYSCTRL);
1026 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1027 }
1028
1029 /**
1030 * @brief SYSCTRL IIR1 Bus&Function Clock Enable and Reset Release
1031 * @param None
1032 * @return None
1033 */
LL_SYSCTRL_IIR1_ClkEnRstRelease(void)1034 void LL_SYSCTRL_IIR1_ClkEnRstRelease(void)
1035 {
1036 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1037 __LL_SYSCTRL_IIR1BusClk_En(SYSCTRL);
1038 __LL_SYSCTRL_IIR1FunClk_En(SYSCTRL);
1039 __LL_SYSCTRL_IIR1SoftRst_Release(SYSCTRL);
1040 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1041 }
1042
1043 /**
1044 * @brief SYSCTRL IIR1 Bus&Function Clock Disable and Reset Assert
1045 * @param None
1046 * @return None
1047 */
LL_SYSCTRL_IIR1_ClkDisRstAssert(void)1048 void LL_SYSCTRL_IIR1_ClkDisRstAssert(void)
1049 {
1050 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1051 __LL_SYSCTRL_IIR1BusClk_Dis(SYSCTRL);
1052 __LL_SYSCTRL_IIR1FunClk_Dis(SYSCTRL);
1053 __LL_SYSCTRL_IIR1SoftRst_Assert(SYSCTRL);
1054 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1055 }
1056
1057 /**
1058 * @brief SYSCTRL IIR0 Bus&Function Clock Enable and Reset Release
1059 * @param None
1060 * @return None
1061 */
LL_SYSCTRL_IIR0_ClkEnRstRelease(void)1062 void LL_SYSCTRL_IIR0_ClkEnRstRelease(void)
1063 {
1064 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1065 __LL_SYSCTRL_IIR0BusClk_En(SYSCTRL);
1066 __LL_SYSCTRL_IIR0FunClk_En(SYSCTRL);
1067 __LL_SYSCTRL_IIR0SoftRst_Release(SYSCTRL);
1068 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1069 }
1070
1071 /**
1072 * @brief SYSCTRL IIR0 Bus&Function Clock Disable and Reset Assert
1073 * @param None
1074 * @return None
1075 */
LL_SYSCTRL_IIR0_ClkDisRstAssert(void)1076 void LL_SYSCTRL_IIR0_ClkDisRstAssert(void)
1077 {
1078 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1079 __LL_SYSCTRL_IIR0BusClk_Dis(SYSCTRL);
1080 __LL_SYSCTRL_IIR0FunClk_Dis(SYSCTRL);
1081 __LL_SYSCTRL_IIR0SoftRst_Assert(SYSCTRL);
1082 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1083 }
1084
1085 /**
1086 * @brief SYSCTRL DALI Bus&Function Clock Enable and Reset Release
1087 * @param None
1088 * @return None
1089 */
LL_SYSCTRL_DALI_ClkEnRstRelease(void)1090 void LL_SYSCTRL_DALI_ClkEnRstRelease(void)
1091 {
1092 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1093 __LL_SYSCTRL_DALIBusClk_En(SYSCTRL);
1094 __LL_SYSCTRL_DALISoftRst_Release(SYSCTRL);
1095 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1096 }
1097
1098 /**
1099 * @brief SYSCTRL DALI Bus&Function Clock Disable and Reset Assert
1100 * @param None
1101 * @return None
1102 */
LL_SYSCTRL_DALI_ClkDisRstAssert(void)1103 void LL_SYSCTRL_DALI_ClkDisRstAssert(void)
1104 {
1105 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1106 __LL_SYSCTRL_DALIBusClk_Dis(SYSCTRL);
1107 __LL_SYSCTRL_DALISoftRst_Assert(SYSCTRL);
1108 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1109 }
1110
1111 /**
1112 * @brief SYSCTRL FPLL2 Reset Release
1113 * @param None
1114 * @return None
1115 */
LL_SYSCTRL_FPLL2_RstRelease(void)1116 void LL_SYSCTRL_FPLL2_RstRelease(void)
1117 {
1118 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1119 __LL_SYSCTRL_FPLL2SoftRst_Release(SYSCTRL);
1120 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1121 }
1122
1123 /**
1124 * @brief SYSCTRL FPLL2 Reset Assert
1125 * @param None
1126 * @return None
1127 */
LL_SYSCTRL_FPLL2_RstAssert(void)1128 void LL_SYSCTRL_FPLL2_RstAssert(void)
1129 {
1130 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1131 __LL_SYSCTRL_FPLL2SoftRst_Assert(SYSCTRL);
1132 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1133 }
1134
1135 /**
1136 * @brief SYSCTRL FPLL1 Reset Release
1137 * @param None
1138 * @return None
1139 */
LL_SYSCTRL_FPLL1_RstRelease(void)1140 void LL_SYSCTRL_FPLL1_RstRelease(void)
1141 {
1142 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1143 __LL_SYSCTRL_FPLL1SoftRst_Release(SYSCTRL);
1144 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1145 }
1146
1147 /**
1148 * @brief SYSCTRL FPLL1 Reset Assert
1149 * @param None
1150 * @return None
1151 */
LL_SYSCTRL_FPLL1_RstAssert(void)1152 void LL_SYSCTRL_FPLL1_RstAssert(void)
1153 {
1154 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1155 __LL_SYSCTRL_FPLL1SoftRst_Assert(SYSCTRL);
1156 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1157 }
1158
1159 /**
1160 * @brief SYSCTRL FPLL0 Reset Release
1161 * @param None
1162 * @return None
1163 */
LL_SYSCTRL_FPLL0_RstRelease(void)1164 void LL_SYSCTRL_FPLL0_RstRelease(void)
1165 {
1166 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1167 __LL_SYSCTRL_FPLL0SoftRst_Release(SYSCTRL);
1168 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1169 }
1170
1171 /**
1172 * @brief SYSCTRL FPLL0 Reset Assert
1173 * @param None
1174 * @return None
1175 */
LL_SYSCTRL_FPLL0_RstAssert(void)1176 void LL_SYSCTRL_FPLL0_RstAssert(void)
1177 {
1178 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1179 __LL_SYSCTRL_FPLL0SoftRst_Assert(SYSCTRL);
1180 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1181 }
1182
1183 /**
1184 * @brief SYSCTRL USB Bus&Function Clock Enable and Reset Release
1185 * @param None
1186 * @return None
1187 */
LL_SYSCTRL_USB_ClkEnRstRelease(void)1188 void LL_SYSCTRL_USB_ClkEnRstRelease(void)
1189 {
1190 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1191 __LL_SYSCTRL_USBBusClk_En(SYSCTRL);
1192 __LL_SYSCTRL_USBFunClk_En(SYSCTRL);
1193 __LL_SYSCTRL_USBSoftRst_Release(SYSCTRL);
1194 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1195 }
1196
1197 /**
1198 * @brief SYSCTRL USB Bus&Function Clock Disable and Reset Assert
1199 * @param None
1200 * @return None
1201 */
LL_SYSCTRL_USB_ClkDisRstAssert(void)1202 void LL_SYSCTRL_USB_ClkDisRstAssert(void)
1203 {
1204 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1205 __LL_SYSCTRL_USBBusClk_Dis(SYSCTRL);
1206 __LL_SYSCTRL_USBFunClk_Dis(SYSCTRL);
1207 __LL_SYSCTRL_USBSoftRst_Assert(SYSCTRL);
1208 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1209 }
1210
1211 /**
1212 * @brief SYSCTRL DFLASH Bus&Memory Clock Enable and Reset Release
1213 * @param None
1214 * @return None
1215 */
LL_SYSCTRL_DFLASH_ClkEnRstRelease(void)1216 void LL_SYSCTRL_DFLASH_ClkEnRstRelease(void)
1217 {
1218 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1219 __LL_SYSCTRL_DFLASHBusClk_En(SYSCTRL);
1220 __LL_SYSCTRL_DFLASHMemClk_En(SYSCTRL);
1221 __LL_SYSCTRL_DFLASHSoftRst_Release(SYSCTRL);
1222 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1223 }
1224
1225 /**
1226 * @brief SYSCTRL DFLASH Bus&Memory Clock Disable and Reset Assert
1227 * @param None
1228 * @return None
1229 */
LL_SYSCTRL_DFLASH_ClkDisRstAssert(void)1230 void LL_SYSCTRL_DFLASH_ClkDisRstAssert(void)
1231 {
1232 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1233 __LL_SYSCTRL_DFLASHBusClk_Dis(SYSCTRL);
1234 __LL_SYSCTRL_DFLASHMemClk_Dis(SYSCTRL);
1235 __LL_SYSCTRL_DFLASHSoftRst_Assert(SYSCTRL);
1236 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1237 }
1238
1239 /**
1240 * @brief SYSCTRL EFLASH Bus&Memory Clock Enable and Reset Release
1241 * @param None
1242 * @return None
1243 */
LL_SYSCTRL_EFLASH_ClkEnRstRelease(void)1244 void LL_SYSCTRL_EFLASH_ClkEnRstRelease(void)
1245 {
1246 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1247 __LL_SYSCTRL_EFLASHBusClk_En(SYSCTRL);
1248 __LL_SYSCTRL_EFLASHMemClk_En(SYSCTRL);
1249 __LL_SYSCTRL_EFLASHSoftRst_Release(SYSCTRL);
1250 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1251 }
1252
1253 /**
1254 * @brief SYSCTRL EFLASH Bus&Memory Clock Disable and Reset Assert
1255 * @param None
1256 * @return None
1257 */
LL_SYSCTRL_EFLASH_ClkDisRstAssert(void)1258 void LL_SYSCTRL_EFLASH_ClkDisRstAssert(void)
1259 {
1260 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1261 __LL_SYSCTRL_EFLASHBusClk_Dis(SYSCTRL);
1262 __LL_SYSCTRL_EFLASHMemClk_Dis(SYSCTRL);
1263 __LL_SYSCTRL_EFLASHSoftRst_Assert(SYSCTRL);
1264 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1265 }
1266
1267 /**
1268 * @brief SYSCTRL HRPWM Bus&Function Clock Enable and Reset Release
1269 * @param None
1270 * @return None
1271 */
LL_SYSCTRL_HRPWM_ClkEnRstRelease(void)1272 void LL_SYSCTRL_HRPWM_ClkEnRstRelease(void)
1273 {
1274 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1275 __LL_SYSCTRL_HRPWMBusClk_En(SYSCTRL);
1276 __LL_SYSCTRL_HRPWMFunClk_En(SYSCTRL);
1277 __LL_SYSCTRL_HRPWMSoftRst_Release(SYSCTRL);
1278 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1279 }
1280
1281 /**
1282 * @brief SYSCTRL HRPWM Bus&Function Clock Disable and Reset Assert
1283 * @param None
1284 * @return None
1285 */
LL_SYSCTRL_HRPWM_ClkDisRstAssert(void)1286 void LL_SYSCTRL_HRPWM_ClkDisRstAssert(void)
1287 {
1288 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1289 __LL_SYSCTRL_HRPWMBusClk_Dis(SYSCTRL);
1290 __LL_SYSCTRL_HRPWMFunClk_Dis(SYSCTRL);
1291 __LL_SYSCTRL_HRPWMSoftRst_Assert(SYSCTRL);
1292 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1293 }
1294
1295 /**
1296 * @brief SYSCTRL ADC Bus&Function Clock Enable and Reset Release
1297 * @param None
1298 * @return None
1299 */
LL_SYSCTRL_ADC_ClkEnRstRelease(void)1300 void LL_SYSCTRL_ADC_ClkEnRstRelease(void)
1301 {
1302 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1303 __LL_SYSCTRL_ADCBusClk_En(SYSCTRL);
1304 __LL_SYSCTRL_ADCFunClk_En(SYSCTRL);
1305 __LL_SYSCTRL_ADCSoftRst_Release(SYSCTRL);
1306 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1307 }
1308
1309 /**
1310 * @brief SYSCTRL ADC Bus&Function Clock Disable and Reset Assert
1311 * @param None
1312 * @return None
1313 */
LL_SYSCTRL_ADC_ClkDisRstAssert(void)1314 void LL_SYSCTRL_ADC_ClkDisRstAssert(void)
1315 {
1316 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1317 __LL_SYSCTRL_ADCBusClk_Dis(SYSCTRL);
1318 __LL_SYSCTRL_ADCFunClk_Dis(SYSCTRL);
1319 __LL_SYSCTRL_ADCSoftRst_Assert(SYSCTRL);
1320 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1321 }
1322
1323 /**
1324 * @brief SYSCTRL DAC Bus Clock Enable and Reset Release
1325 * @param None
1326 * @return None
1327 */
LL_SYSCTRL_DAC_ClkEnRstRelease(void)1328 void LL_SYSCTRL_DAC_ClkEnRstRelease(void)
1329 {
1330 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1331 __LL_SYSCTRL_DACBusClk_En(SYSCTRL);
1332 __LL_SYSCTRL_DACSoftRst_Release(SYSCTRL);
1333 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1334 }
1335
1336 /**
1337 * @brief SYSCTRL DAC Bus Clock Disable and Reset Assert
1338 * @param None
1339 * @return None
1340 */
LL_SYSCTRL_DAC_ClkDisRstAssert(void)1341 void LL_SYSCTRL_DAC_ClkDisRstAssert(void)
1342 {
1343 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1344 __LL_SYSCTRL_DACBusClk_Dis(SYSCTRL);
1345 __LL_SYSCTRL_DACSoftRst_Assert(SYSCTRL);
1346 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1347 }
1348
1349 /**
1350 * @brief SYSCTRL CMP Bus Clock Enable and Reset Release
1351 * @param None
1352 * @return None
1353 */
LL_SYSCTRL_CMP_ClkEnRstRelease(void)1354 void LL_SYSCTRL_CMP_ClkEnRstRelease(void)
1355 {
1356 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1357 __LL_SYSCTRL_CMPBusClk_En(SYSCTRL);
1358 __LL_SYSCTRL_CMPSoftRst_Release(SYSCTRL);
1359 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1360 }
1361
1362 /**
1363 * @brief SYSCTRL CMP Bus Clock Disable and Reset Assert
1364 * @param None
1365 * @return None
1366 */
LL_SYSCTRL_CMP_ClkDisRstAssert(void)1367 void LL_SYSCTRL_CMP_ClkDisRstAssert(void)
1368 {
1369 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1370 __LL_SYSCTRL_CMPBusClk_Dis(SYSCTRL);
1371 __LL_SYSCTRL_CMPSoftRst_Assert(SYSCTRL);
1372 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1373 }
1374
1375 /**
1376 * @brief SYSCTRL GPIOD Bus Clock Enable and Reset Release
1377 * @param None
1378 * @return None
1379 */
LL_SYSCTRL_GPIOD_ClkEnRstRelease(void)1380 void LL_SYSCTRL_GPIOD_ClkEnRstRelease(void)
1381 {
1382 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1383 __LL_SYSCTRL_GPIODBusClk_En(SYSCTRL);
1384 __LL_SYSCTRL_GPIODSoftRst_Release(SYSCTRL);
1385 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1386 }
1387
1388 /**
1389 * @brief SYSCTRL GPIOD Bus Clock Disable and Reset Assert
1390 * @param None
1391 * @return None
1392 */
LL_SYSCTRL_GPIOD_ClkDisRstAssert(void)1393 void LL_SYSCTRL_GPIOD_ClkDisRstAssert(void)
1394 {
1395 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1396 __LL_SYSCTRL_GPIODBusClk_Dis(SYSCTRL);
1397 __LL_SYSCTRL_GPIODSoftRst_Assert(SYSCTRL);
1398 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1399 }
1400
1401 /**
1402 * @brief SYSCTRL GPIOC Bus Clock Enable and Reset Release
1403 * @param None
1404 * @return None
1405 */
LL_SYSCTRL_GPIOC_ClkEnRstRelease(void)1406 void LL_SYSCTRL_GPIOC_ClkEnRstRelease(void)
1407 {
1408 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1409 __LL_SYSCTRL_GPIOCBusClk_En(SYSCTRL);
1410 __LL_SYSCTRL_GPIOCSoftRst_Release(SYSCTRL);
1411 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1412 }
1413
1414 /**
1415 * @brief SYSCTRL GPIOC Bus Clock Disable and Reset Assert
1416 * @param None
1417 * @return None
1418 */
LL_SYSCTRL_GPIOC_ClkDisRstAssert(void)1419 void LL_SYSCTRL_GPIOC_ClkDisRstAssert(void)
1420 {
1421 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1422 __LL_SYSCTRL_GPIOCBusClk_Dis(SYSCTRL);
1423 __LL_SYSCTRL_GPIOCSoftRst_Assert(SYSCTRL);
1424 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1425 }
1426
1427 /**
1428 * @brief SYSCTRL GPIOB Bus Clock Enable and Reset Release
1429 * @param None
1430 * @return None
1431 */
LL_SYSCTRL_GPIOB_ClkEnRstRelease(void)1432 void LL_SYSCTRL_GPIOB_ClkEnRstRelease(void)
1433 {
1434 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1435 __LL_SYSCTRL_GPIOBBusClk_En(SYSCTRL);
1436 __LL_SYSCTRL_GPIOBSoftRst_Release(SYSCTRL);
1437 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1438 }
1439
1440 /**
1441 * @brief SYSCTRL GPIOB Bus Clock Disable and Reset Assert
1442 * @param None
1443 * @return None
1444 */
LL_SYSCTRL_GPIOB_ClkDisRstAssert(void)1445 void LL_SYSCTRL_GPIOB_ClkDisRstAssert(void)
1446 {
1447 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1448 __LL_SYSCTRL_GPIOBBusClk_Dis(SYSCTRL);
1449 __LL_SYSCTRL_GPIOBSoftRst_Assert(SYSCTRL);
1450 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1451 }
1452
1453 /**
1454 * @brief SYSCTRL GPIOA Bus Clock Enable and Reset Release
1455 * @param None
1456 * @return None
1457 */
LL_SYSCTRL_GPIOA_ClkEnRstRelease(void)1458 void LL_SYSCTRL_GPIOA_ClkEnRstRelease(void)
1459 {
1460 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1461 __LL_SYSCTRL_GPIOABusClk_En(SYSCTRL);
1462 __LL_SYSCTRL_GPIOASoftRst_Release(SYSCTRL);
1463 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1464 }
1465
1466 /**
1467 * @brief SYSCTRL GPIOA Bus Clock Disable and Reset Assert
1468 * @param None
1469 * @return None
1470 */
LL_SYSCTRL_GPIOA_ClkDisRstAssert(void)1471 void LL_SYSCTRL_GPIOA_ClkDisRstAssert(void)
1472 {
1473 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1474 __LL_SYSCTRL_GPIOABusClk_Dis(SYSCTRL);
1475 __LL_SYSCTRL_GPIOASoftRst_Assert(SYSCTRL);
1476 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1477 }
1478
1479 /**
1480 * @brief SYSCTRL HSTIMER Bus Clock Enable and Reset Release
1481 * @param None
1482 * @return None
1483 */
LL_SYSCTRL_HSTMR_ClkEnRstRelease(void)1484 void LL_SYSCTRL_HSTMR_ClkEnRstRelease(void)
1485 {
1486 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1487 __LL_SYSCTRL_HSTIMERBusClk_En(SYSCTRL);
1488 __LL_SYSCTRL_HSTIMERSoftRst_Release(SYSCTRL);
1489 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1490 }
1491
1492 /**
1493 * @brief SYSCTRL HSTIMER Bus Clock Disable and Reset Assert
1494 * @param None
1495 * @return None
1496 */
LL_SYSCTRL_HSTMR_ClkDisRstAssert(void)1497 void LL_SYSCTRL_HSTMR_ClkDisRstAssert(void)
1498 {
1499 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1500 __LL_SYSCTRL_HSTIMERBusClk_Dis(SYSCTRL);
1501 __LL_SYSCTRL_HSTIMERSoftRst_Assert(SYSCTRL);
1502 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1503 }
1504
1505 /**
1506 * @brief SYSCTRL CAN Bus&Function Clock Enable and Reset Release
1507 * @param None
1508 * @return None
1509 */
LL_SYSCTRL_CAN_ClkEnRstRelease(void)1510 void LL_SYSCTRL_CAN_ClkEnRstRelease(void)
1511 {
1512 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1513 __LL_SYSCTRL_CANBusClk_En(SYSCTRL);
1514 __LL_SYSCTRL_CANFunClk_En(SYSCTRL);
1515 __LL_SYSCTRL_CANSoftRst_Release(SYSCTRL);
1516 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1517 }
1518
1519 /**
1520 * @brief SYSCTRL CAN Bus&Function Clock Disable and Reset Assert
1521 * @param None
1522 * @return None
1523 */
LL_SYSCTRL_CAN_ClkDisRstAssert(void)1524 void LL_SYSCTRL_CAN_ClkDisRstAssert(void)
1525 {
1526 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1527 __LL_SYSCTRL_CANBusClk_Dis(SYSCTRL);
1528 __LL_SYSCTRL_CANFunClk_Dis(SYSCTRL);
1529 __LL_SYSCTRL_CANSoftRst_Assert(SYSCTRL);
1530 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1531 }
1532
1533 /**
1534 * @brief SYSCTRL DMA Bus Clock Enable and Reset Release
1535 * @param None
1536 * @return None
1537 */
LL_SYSCTRL_DMA_ClkEnRstRelease(void)1538 void LL_SYSCTRL_DMA_ClkEnRstRelease(void)
1539 {
1540 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1541 __LL_SYSCTRL_DMABusClk_En(SYSCTRL);
1542 __LL_SYSCTRL_DMASoftRst_Release(SYSCTRL);
1543 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1544 }
1545
1546 /**
1547 * @brief SYSCTRL DMA Bus Clock Disable and Reset Assert
1548 * @param None
1549 * @return None
1550 */
LL_SYSCTRL_DMA_ClkDisRstAssert(void)1551 void LL_SYSCTRL_DMA_ClkDisRstAssert(void)
1552 {
1553 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1554 __LL_SYSCTRL_DMABusClk_Dis(SYSCTRL);
1555 __LL_SYSCTRL_DMASoftRst_Assert(SYSCTRL);
1556 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1557 }
1558
1559
1560 /**
1561 * @brief SYSCTRL LL all peripheral reset assert
1562 * @note All peripheral include system bus(AHB/APB0/APB1)
1563 * @param None
1564 * @return None
1565 */
LL_SYSCTRL_AllPeriphRstAssert(void)1566 void LL_SYSCTRL_AllPeriphRstAssert(void)
1567 {
1568 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1569 __LL_SYSCTRL_SysSoftRstAll_Assert(SYSCTRL);
1570 __LL_SYSCTRL_APB0SoftRstAll_Assert(SYSCTRL);
1571 __LL_SYSCTRL_APB1SoftRstAll_Assert(SYSCTRL);
1572 __LL_SYSCTRL_AHBSoftRstAll_Assert(SYSCTRL);
1573 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1574 }
1575
1576 /**
1577 * @brief SYSCTRL LL all peripheral reset release
1578 * @note All peripheral include system bus(AHB/APB0/APB1)
1579 * @param None
1580 * @return None
1581 */
LL_SYSCTRL_AllPeriphRstRelease(void)1582 void LL_SYSCTRL_AllPeriphRstRelease(void)
1583 {
1584 __LL_SYSCTRL_CTRLReg_Unlock(SYSCTRL);
1585 __LL_SYSCTRL_SysSoftRstAll_Release(SYSCTRL);
1586 __LL_SYSCTRL_APB0SoftRstAll_Release(SYSCTRL);
1587 __LL_SYSCTRL_APB1SoftRstAll_Release(SYSCTRL);
1588 __LL_SYSCTRL_AHBSoftRstAll_Release(SYSCTRL);
1589 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1590 }
1591 /**
1592 * @}
1593 */
1594
1595 /** @defgroup SYSCTRL_LL_Exported_Functions_Group4 SYSCTRL Misc Config Functions
1596 * @brief SYSCTRL Misc Config Functions
1597 * @{
1598 */
1599
1600 /**
1601 * @brief SYSCTRL LL PMU Config
1602 * @param None
1603 * @return None
1604 */
LL_SYSCTRL_PMUCfg(void)1605 void LL_SYSCTRL_PMUCfg(void)
1606 {
1607 __LL_SYSCTRL_FLSReg_Unlock(SYSCTRL);
1608 __LL_SYSCTRL_CUR_RES_Set(SYSCTRL, 0);
1609 __LL_SYSCTRL_BGR_DRD_Dis(SYSCTRL);
1610 __LL_SYSCTRL_BGR_Filter_En(SYSCTRL);
1611 __LL_SYSCTRL_Reg_Lock(SYSCTRL);
1612 }
1613
1614 /**
1615 * @}
1616 */
1617
1618 /**
1619 * @}
1620 */
1621
1622 /* Private functions ---------------------------------------------------------*/
1623 /** @addtogroup SYSCTRL_LL_Private_Functions
1624 * @{
1625 */
1626
1627 /**
1628 * @brief SYSCTRL LL XOSC Config
1629 * @param Instance Specifies SYSCTRL peripheral
1630 * @note Must unlock SYSCTRL CTRL Reg before call this function
1631 * @return None
1632 */
LL_SYSCTRL_XOSCCfg(SYSCTRL_TypeDef * Instance)1633 static void LL_SYSCTRL_XOSCCfg(SYSCTRL_TypeDef *Instance)
1634 {
1635 //Check SYSCTRL CTRL Reg unlock or not
1636 if (!__LL_SYSCTRL_IsCTRLRegUnlock(Instance)) {
1637 LOG_E("SYSCTRL CTRL Reg is Lock, please unlock it before call this function!\n");
1638 return;
1639 }
1640
1641 __LL_SYSCTRL_XOSC_En(Instance);
1642 }
1643 /**
1644 * @}
1645 */
1646
1647
1648 /**
1649 * @}
1650 */
1651
1652 /**
1653 * @}
1654 */
1655
1656
1657 /************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
1658
1659