1 /**
2 ******************************************************************************
3 * @file tae32f53xx_ll_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX LL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15
16 [..]
17 *** How to configure Interrupts using CORTEX LL driver ***
18 ===========================================================
19 [..]
20 This section provides functions allowing to configure the NVIC interrupts (IRQ).
21 The Cortex-M3 exceptions are managed by CMSIS functions.
22
23 (#) Configure the NVIC Priority Grouping using LL_NVIC_SetPriorityGrouping()
24 function according to the following table.
25 (#) Configure the priority of the selected IRQ Channels using LL_NVIC_SetPriority().
26 (#) Enable the selected IRQ Channels using LL_NVIC_EnableIRQ().
27 (#) please refer to programming manual for details in how to configure priority.
28
29 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
30 The pending IRQ priority will be managed only by the sub priority.
31
32 -@- IRQ priority order (sorted by highest to lowest priority):
33 (+@) Lowest preemption priority
34 (+@) Lowest sub priority
35 (+@) Lowest hardware priority (IRQ number)
36
37 [..]
38 *** How to configure Systick using CORTEX LL driver ***
39 ========================================================
40 [..]
41 Setup SysTick Timer for time base.
42
43 (+) The LL_SYSTICK_Config()function calls the SysTick_Config() function which
44 is a CMSIS function that:
45 (++) Configures the SysTick Reload register with value passed as function parameter.
46 (++) Configures the SysTick IRQ priority to the lowest value 0x07.
47 (++) Resets the SysTick Counter register.
48 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
49 (++) Enables the SysTick Interrupt.
50 (++) Starts the SysTick Counter.
51
52 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
53 LL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
54 LL_SYSTICK_Config() function call. The LL_SYSTICK_CLKSourceConfig() function is defined below.
55
56 (+) You can change the SysTick IRQ priority by calling the
57 LL_NVIC_SetPriority(SysTick_IRQn,...) function just after the LL_SYSTICK_Config() function
58 call. The LL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
59
60 (+) To adjust the SysTick time base, use the following formula:
61
62 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
63 (++) Reload Value is the parameter to be passed for LL_SYSTICK_Config() function
64 (++) Reload Value should not exceed 0xFFFFFF
65
66 @endverbatim
67 ******************************************************************************
68 * @attention
69 *
70 * <h2><center>© Copyright (c) 2020 Tai-Action.
71 * All rights reserved.</center></h2>
72 *
73 * This software is licensed by Tai-Action under BSD 3-Clause license,
74 * the "License"; You may not use this file except in compliance with the
75 * License. You may obtain a copy of the License at:
76 * opensource.org/licenses/BSD-3-Clause
77 *
78 ******************************************************************************
79 */
80
81 /* Includes ------------------------------------------------------------------*/
82 #include "tae32f53xx_ll.h"
83
84
85 #define DBG_TAG "Cortex LL"
86 #define DBG_LVL DBG_ERROR
87 #include "dbg/tae32f53xx_dbg.h"
88
89
90 /**
91 * @addtogroup TAE32F53xx_LL_Driver
92 * @{
93 */
94
95 /** @defgroup CORTEX_LL CORTEX LL
96 * @brief CORTEX LL module driver
97 * @{
98 */
99
100 #ifdef LL_CORTEX_MODULE_ENABLED
101
102 /* Private typedef -----------------------------------------------------------*/
103 /* Private define ------------------------------------------------------------*/
104 /* Private macro -------------------------------------------------------------*/
105 /* Private variables ---------------------------------------------------------*/
106 /* Private function prototypes -----------------------------------------------*/
107 /* Exported functions --------------------------------------------------------*/
108 /** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
109 * @brief CORTEX LL Exported Functions
110 * @{
111 */
112
113 /** @defgroup CORTEX_LL_Exported_Functions_Group1 NVIC Priority Config Functions
114 * @brief NVIC Priority Config Functions
115 * @{
116 */
117
118 /** @brief Sets the priority grouping field (preemption priority and subpriority)
119 * using the required unlock sequence.
120 * @param PriorityGroup: The priority grouping bits length.
121 * This parameter can be one of the following values:
122 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
123 * 3 bits for subpriority
124 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
125 * 2 bits for subpriority
126 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
127 * 1 bits for subpriority
128 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
129 * 0 bit for subpriority
130 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
131 * The pending IRQ priority will be managed only by the subpriority.
132 * @return None
133 */
LL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)134 void LL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
135 {
136 /* Check the parameters */
137 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
138
139 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
140 NVIC_SetPriorityGrouping(PriorityGroup);
141 }
142
143 /**
144 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
145 * @return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
146 */
LL_NVIC_GetPriorityGrouping(void)147 uint32_t LL_NVIC_GetPriorityGrouping(void)
148 {
149 /* Get the PRIGROUP[10:8] field value */
150 return NVIC_GetPriorityGrouping();
151 }
152
153 /**
154 * @brief Sets the priority of an interrupt.
155 * @param IRQn: External interrupt number.
156 * This parameter can be an enumerator of IRQn_Type enumeration
157 * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file tae32f53xx.h)
158 * @param PreemptPriority: The preemption priority for the IRQn channel.
159 * This parameter can be a value between 0 and 7
160 * A lower priority value indicates a higher priority
161 * @param SubPriority: the subpriority level for the IRQ channel.
162 * This parameter can be a value between 0 and 7
163 * A lower priority value indicates a higher priority.
164 * @note The table below gives the allowed values of the pre-emption priority and subpriority according
165 * to the Priority Grouping configuration performed by LL_NVIC_SetPriorityGrouping() function.
166 * =========================================================================================
167 * NVIC_PriorityGroup | PreemptPriority | SubPriority | Description
168 * =========================================================================================
169 * NVIC_PRIORITYGROUP_0 | 0 | 0-7 | 0 bit for pre-emption priority
170 * | | | 3 bits for subpriority
171 * -----------------------------------------------------------------------------------------
172 * NVIC_PRIORITYGROUP_1 | 0-1 | 0-3 | 1 bit for pre-emption priority
173 * | | | 2 bits for subpriority
174 * -----------------------------------------------------------------------------------------
175 * NVIC_PRIORITYGROUP_2 | 0-3 | 0-1 | 2 bits for pre-emption priority
176 * | | | 1 bits for subpriority
177 * -----------------------------------------------------------------------------------------
178 * NVIC_PRIORITYGROUP_3 | 0-7 | 0 | 3 bits for pre-emption priority
179 * | | | 0 bit for subpriority
180 * =========================================================================================
181 * @return None
182 */
LL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)183 void LL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
184 {
185 uint32_t prioritygroup = 0x00U;
186
187 /* Check the parameters */
188 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
189 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
190
191 prioritygroup = NVIC_GetPriorityGrouping();
192
193 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
194 }
195
196 /**
197 * @brief Gets the priority of an interrupt.
198 * @param IRQn: External interrupt number.
199 * This parameter can be an enumerator of IRQn_Type enumeration
200 * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
201 * @param PriorityGroup: the priority grouping bits length.
202 * This parameter can be one of the following values:
203 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
204 * 3 bits for subpriority
205 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
206 * 2 bits for subpriority
207 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
208 * 1 bits for subpriority
209 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
210 * 0 bits for subpriority
211 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
212 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
213 * @return None
214 */
LL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)215 void LL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
216 {
217 /* Check the parameters */
218 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
219
220 /* Get priority for Cortex-M system or device specific interrupts */
221 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
222 }
223 /**
224 * @}
225 */
226
227
228 /** @defgroup CORTEX_LL_Exported_Functions_Group2 NVIC Enable and Pending Config Functions
229 * @brief NVIC Enable and Pending Config Functions
230 * @{
231 */
232
233 /**
234 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
235 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
236 * function should be called before.
237 * @param IRQn External interrupt number.
238 * This parameter can be an enumerator of IRQn_Type enumeration
239 * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
240 * @return None
241 */
LL_NVIC_EnableIRQ(IRQn_Type IRQn)242 void LL_NVIC_EnableIRQ(IRQn_Type IRQn)
243 {
244 /* Check the parameters */
245 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
246
247 /* Enable interrupt */
248 NVIC_EnableIRQ(IRQn);
249 }
250
251 /**
252 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
253 * @param IRQn External interrupt number.
254 * This parameter can be an enumerator of IRQn_Type enumeration
255 * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
256 * @return None
257 */
LL_NVIC_DisableIRQ(IRQn_Type IRQn)258 void LL_NVIC_DisableIRQ(IRQn_Type IRQn)
259 {
260 /* Check the parameters */
261 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
262
263 /* Disable interrupt */
264 NVIC_DisableIRQ(IRQn);
265 }
266
267 /**
268 * @brief Sets Pending bit of an external interrupt.
269 * @param IRQn External interrupt number
270 * This parameter can be an enumerator of IRQn_Type enumeration
271 * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
272 * @return None
273 */
LL_NVIC_SetPendingIRQ(IRQn_Type IRQn)274 void LL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
275 {
276 /* Check the parameters */
277 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
278
279 /* Set interrupt pending */
280 NVIC_SetPendingIRQ(IRQn);
281 }
282
283 /**
284 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
285 * and returns the pending bit for the specified interrupt).
286 * @param IRQn External interrupt number.
287 * This parameter can be an enumerator of IRQn_Type enumeration
288 * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
289 * @return pending status
290 * @retval 0 Interrupt status is not pending.
291 * @retval 1 Interrupt status is pending.
292 */
LL_NVIC_GetPendingIRQ(IRQn_Type IRQn)293 uint32_t LL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
294 {
295 /* Check the parameters */
296 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
297
298 /* Return 1 if pending else 0 */
299 return NVIC_GetPendingIRQ(IRQn);
300 }
301
302 /**
303 * @brief Clears the pending bit of an external interrupt.
304 * @param IRQn External interrupt number.
305 * This parameter can be an enumerator of IRQn_Type enumeration
306 * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
307 * @return None
308 */
LL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)309 void LL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
310 {
311 /* Check the parameters */
312 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
313
314 /* Clear pending interrupt */
315 NVIC_ClearPendingIRQ(IRQn);
316 }
317
318 /**
319 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
320 * @param IRQn External interrupt number
321 * This parameter can be an enumerator of IRQn_Type enumeration
322 * (For the complete TAE32F53xx Devices IRQ Channels list, please refer to the appropriate CMSIS device file (tae32f53xx.h))
323 * @return status: - 0 Interrupt status is not pending.
324 * - 1 Interrupt status is pending.
325 */
LL_NVIC_GetActive(IRQn_Type IRQn)326 uint32_t LL_NVIC_GetActive(IRQn_Type IRQn)
327 {
328 /* Check the parameters */
329 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
330
331 /* Return 1 if active else 0 */
332 return NVIC_GetActive(IRQn);
333 }
334
335 /**
336 * @brief Initiates a system reset request to reset the MCU.
337 * @param None
338 * @return None
339 */
LL_NVIC_SystemReset(void)340 void LL_NVIC_SystemReset(void)
341 {
342 /* System Reset */
343 NVIC_SystemReset();
344 }
345 /**
346 * @}
347 */
348
349
350 /** @defgroup CORTEX_LL_Exported_Functions_Group3 SYSTICK Config Functions
351 * @brief SYSTICK Config Functions
352 * @{
353 */
354
355 /**
356 * @brief Configures the SysTick clock source.
357 * @param CLKSource: specifies the SysTick clock source.
358 * This parameter can be one of the following values:
359 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
360 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
361 * @return None
362 */
LL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)363 void LL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
364 {
365 /* Check the parameters */
366 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
367
368 if (CLKSource == SYSTICK_CLKSOURCE_HCLK) {
369 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
370 } else {
371 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
372 }
373 }
374
375 /**
376 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
377 * Counter is in free running mode to generate periodic interrupts.
378 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
379 * @retval status: - 0 Function succeeded.
380 * - 1 Function failed.
381 */
LL_SYSTICK_Config(uint32_t TicksNumb)382 uint32_t LL_SYSTICK_Config(uint32_t TicksNumb)
383 {
384 return SysTick_Config(TicksNumb);
385 }
386 /**
387 * @}
388 */
389
390
391 /** @defgroup CORTEX_LL_Exported_Functions_Interrupt CORTEX Interrupt management
392 * @brief CORTEX Interrupt management
393 *
394 @verbatim
395 ==============================================================================
396 ##### Interrupt Management #####
397 ==============================================================================
398 [..]
399 This section provides CORTEX interrupt handler functions.
400 @endverbatim
401 * @{
402 */
403
404 /**
405 * @brief This function handles SYSTICK interrupts requests.
406 * @param None
407 * @return None
408 */
LL_SYSTICK_IRQHandler(void)409 void LL_SYSTICK_IRQHandler(void)
410 {
411 LL_SYSTICK_Callback();
412 }
413
414 /**
415 * @brief SYSTICK callback.
416 * @param None
417 * @retval None
418 */
LL_SYSTICK_Callback(void)419 __WEAK void LL_SYSTICK_Callback(void)
420 {
421 /* NOTE : This function Should not be modified, when the callback is needed,
422 the LL_SYSTICK_Callback could be implemented in the user file
423 */
424 }
425 /**
426 * @}
427 */
428
429
430 /**
431 * @}
432 */
433
434 /* Private functions ---------------------------------------------------------*/
435
436
437 #endif /* LL_CORTEX_MODULE_ENABLE */
438
439 /**
440 * @}
441 */
442
443 /**
444 * @}
445 */
446
447 /************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
448
449