1 /*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018/11/29 Bernard the first version
9 */
10
11 #include <rthw.h>
12 #include <rtthread.h>
13
14 #include "board.h"
15 #include "drv_uart.h"
16
17 #include "pin_mux.h"
18 #include "clock_config.h"
19
20 #include <fsl_clock.h>
21 #include <fsl_intmux.h>
22
LPIT0_IRQHandler(void)23 void LPIT0_IRQHandler(void)
24 {
25 rt_tick_increase();
26
27 SystemClearSystickFlag();
28 }
29
rt_hw_systick_init(void)30 int rt_hw_systick_init(void)
31 {
32 CLOCK_SetIpSrc(kCLOCK_Lpit0, kCLOCK_IpSrcFircAsync);
33
34 SystemSetupSystick (RT_TICK_PER_SECOND, 0);
35 SystemClearSystickFlag();
36
37 return 0;
38 }
39
40 const scg_lpfll_config_t g_appScgLpFllConfig_BOARD_BootClockRUN = {
41 .enableMode = kSCG_LpFllEnable, /* LPFLL clock disabled */
42 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: Clock output is disabled */
43 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
44 .div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
45 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
46 .trimConfig = NULL,
47 };
48
rt_hw_board_init(void)49 void rt_hw_board_init(void)
50 {
51 BOARD_InitPins();
52 BOARD_BootClockRUN();
53 /* Init LPFLL */
54 CLOCK_InitLpFll(&g_appScgLpFllConfig_BOARD_BootClockRUN);
55
56 INTMUX_Init(INTMUX0);
57 INTMUX_EnableInterrupt(INTMUX0, 0, PORTC_IRQn);
58
59 /* initialize hardware interrupt */
60 rt_hw_uart_init();
61 rt_hw_systick_init();
62
63 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
64 /* set console device */
65 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
66 #endif
67
68 #ifdef RT_USING_HEAP
69 /* initialize memory system */
70 rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
71 #endif
72
73 #ifdef RT_USING_COMPONENTS_INIT
74 rt_components_board_init();
75 #endif
76 }
77