1 /* 2 * Copyright (c) 2022 OpenLuat & AirM2M 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy of 5 * this software and associated documentation files (the "Software"), to deal in 6 * the Software without restriction, including without limitation the rights to 7 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 8 * the Software, and to permit persons to whom the Software is furnished to do so, 9 * subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in all 12 * copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 16 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 17 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 18 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22 23 24 #ifndef __AIR105_H__ 25 #define __AIR105_H__ 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 /* ToDo: replace '<Device>' with your device name; add your doxyGen comment */ 32 /** @addtogroup <Device>_Definitions <Device> Definitions 33 This file defines all structures and symbols for <Device>: 34 - registers and bitfields 35 - peripheral base address 36 - peripheral ID 37 - Peripheral definitions 38 @{ 39 */ 40 41 42 /******************************************************************************/ 43 /* Processor and Core Peripherals */ 44 /******************************************************************************/ 45 /** @addtogroup <Device>_CMSIS Device CMSIS Definitions 46 Configuration of the Cortex-M# Processor and Core Peripherals 47 @{ 48 */ 49 /* 50 * ========================================================================== 51 * ---------- Interrupt Number Definition ----------------------------------- 52 * ========================================================================== 53 */ 54 typedef enum IRQn 55 { 56 /****** Cortex-M# Processor Exceptions Numbers ***************************************************/ 57 58 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device */ 59 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 60 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ 61 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ 62 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ 63 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ 64 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ 65 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ 66 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ 67 68 /****** Device Specific Interrupt Numbers ********************************************************/ 69 /* ToDo: add here your device specific external interrupt numbers 70 according the interrupt handlers defined in startup_Device.s 71 eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ 72 DMA_IRQn = 0, 73 USB_IRQn = 1, 74 USBDMA_IRQn = 2, 75 LCD_IRQn = 3, 76 SCI0_IRQn = 4, 77 UART0_IRQn = 5, 78 UART1_IRQn = 6, 79 SPI0_IRQn = 7, 80 CRYPT0_IRQn = 8, 81 TIM0_0_IRQn = 9, 82 TIM0_1_IRQn = 10, 83 TIM0_2_IRQn = 11, 84 TIM0_3_IRQn = 12, 85 EXTI0_IRQn = 13, 86 EXTI1_IRQn = 14, 87 EXTI2_IRQn = 15, 88 RTC_IRQn = 16, 89 SENSOR_IRQn = 17, 90 TRNG_IRQn = 18, 91 ADC0_IRQn = 19, 92 SSC_IRQn = 20, 93 TIM0_4_IRQn = 21, 94 TIM0_5_IRQn = 22, 95 KBD_IRQn = 23, 96 MSR_IRQn = 24, 97 EXTI3_IRQn = 25, 98 SPI1_IRQn = 26, 99 SPI2_IRQn = 27, 100 101 SCI2_IRQn = 29, 102 103 UART2_IRQn = 32, 104 UART3_IRQn = 33, 105 QSPI_IRQn = 35, 106 I2C0_IRQn = 36, 107 EXTI4_IRQn = 37, 108 EXTI5_IRQn = 38, 109 TIM0_6_IRQn = 39, 110 TIM0_7_IRQn = 40, 111 DCMI_IRQn = 42, 112 113 QR_IRQn = 46, 114 GPU_IRQn = 47, 115 116 AWD_IRQn = 49, 117 DAC_IRQn = 50, 118 SPI5_IRQn = 51 119 } IRQn_Type; 120 121 122 /* 123 * ========================================================================== 124 * ----------- Processor and Core Peripheral Section ------------------------ 125 * ========================================================================== 126 */ 127 128 /* Configuration of the Cortex-M# Processor and Core Peripherals */ 129 /* ToDo: set the defines according your Device */ 130 /* ToDo: define the correct core revision 131 __CM0_REV if your device is a CORTEX-M0 device 132 __CM3_REV if your device is a CORTEX-M3 device 133 __CM4_REV if your device is a CORTEX-M4 device */ 134 //#define __CM3_REV 0x0201 /*!< Core Revision r2p1 */ 135 //#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ 136 #define __CM4_REV 0x0001 /*!< Core Revision r2p0 */ 137 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 138 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 139 #define __MPU_PRESENT 1 /*!< MPU present or not */ 140 /* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4 */ 141 #define __FPU_PRESENT 1 /*!< FPU present or not */ 142 143 /*@}*/ /* end of group <Device>_CMSIS */ 144 145 146 /* ToDo: include the correct core_cm#.h file 147 core_cm0.h if your device is a CORTEX-M0 device 148 core_cm3.h if your device is a CORTEX-M3 device 149 core_cm4.h if your device is a CORTEX-M4 device */ 150 #include "core_cm4.h" /* Cortex-M# processor and core peripherals */ 151 /* ToDo: include your system_<Device>.h file 152 replace '<Device>' with your device name */ 153 #include "system_air105.h" /* <Device> System include file */ 154 155 156 /******************************************************************************/ 157 /* Device Specific Peripheral registers structures */ 158 /******************************************************************************/ 159 /** @addtogroup <Device>_Peripherals <Device> Peripherals 160 <Device> Device Specific Peripheral registers structures 161 @{ 162 */ 163 164 #if defined ( __CC_ARM ) 165 #pragma anon_unions 166 #endif 167 168 #include <stdint.h> 169 170 /** @addtogroup Exported_types 171 * @{ 172 */ 173 174 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 175 176 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 177 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 178 179 typedef enum {FALSE = 0, TRUE = !FALSE} Boolean; 180 181 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 182 183 /* ToDo: add here your device specific peripheral access structure typedefs 184 following is an example for a timer */ 185 #define BIT0 (0x00000001U) 186 #define BIT1 (0x00000002U) 187 #define BIT2 (0x00000004U) 188 #define BIT3 (0x00000008U) 189 #define BIT4 (0x00000010U) 190 #define BIT5 (0x00000020U) 191 #define BIT6 (0x00000040U) 192 #define BIT7 (0x00000080U) 193 #define BIT8 (0x00000100U) 194 #define BIT9 (0x00000200U) 195 #define BIT10 (0x00000400U) 196 #define BIT11 (0x00000800U) 197 #define BIT12 (0x00001000U) 198 #define BIT13 (0x00002000U) 199 #define BIT14 (0x00004000U) 200 #define BIT15 (0x00008000U) 201 #define BIT16 (0x00010000U) 202 #define BIT17 (0x00020000U) 203 #define BIT18 (0x00040000U) 204 #define BIT19 (0x00080000U) 205 #define BIT20 (0x00100000U) 206 #define BIT21 (0x00200000U) 207 #define BIT22 (0x00400000U) 208 #define BIT23 (0x00800000U) 209 #define BIT24 (0x01000000U) 210 #define BIT25 (0x02000000U) 211 #define BIT26 (0x04000000U) 212 #define BIT27 (0x08000000U) 213 #define BIT28 (0x10000000U) 214 #define BIT29 (0x20000000U) 215 #define BIT30 (0x40000000U) 216 #define BIT31 (0x80000000U) 217 218 #define BIT(n) (1UL << (n)) 219 220 typedef struct 221 { 222 __IO uint32_t FREQ_SEL; 223 __IO uint32_t CG_CTRL1; 224 __IO uint32_t CG_CTRL2; 225 __O uint32_t SOFT_RST1; 226 __O uint32_t SOFT_RST2; 227 __IO uint32_t LOCK_R; 228 __IO uint32_t PHER_CTRL; 229 __I uint32_t SYS_RSVD[(0x2C-0x1C) >> 2]; 230 __I uint32_t HCLK_1MS_VAL; 231 __I uint32_t PCLK_1MS_VAL; 232 __IO uint32_t ANA_CTRL; 233 __IO uint32_t DMA_CHAN; 234 __IO uint32_t SCI0_GLF; 235 __IO uint32_t SW_RSV1; 236 __IO uint32_t SW_RSV2; 237 __IO uint32_t CARD_RSVD; 238 __IO uint32_t LDO25_CR; 239 __IO uint32_t DMA_CHAN1; 240 __I uint32_t SYS_RSVD2[(0x100-0x54) >> 2]; 241 __IO uint32_t MSR_CR1; 242 __IO uint32_t MSR_CR2; 243 __IO uint32_t USBPHY_CR1; 244 __IO uint32_t USBPHY_CR2; 245 __IO uint32_t USBPHY_CR3; 246 __IO uint32_t ISO7816_CR; 247 __IO uint32_t LDO_CR; 248 __IO uint32_t CHG_CSR; 249 __I uint32_t SYS_RSVD3[(0x204-0x120) >> 2]; 250 __IO uint32_t RSVD_POR; 251 __I uint32_t SYS_RSVD4[(0x3EC-0x208) >> 2]; 252 __IO uint32_t PM2_WK_FLAG; 253 __IO uint32_t CALIB_CSR; 254 __IO uint32_t DBG_CR; 255 __IO uint32_t CHIP_ID; 256 } SYSCTRL_TypeDef; 257 258 typedef struct 259 { 260 union 261 { 262 __I uint32_t RBR; 263 __O uint32_t THR; 264 __IO uint32_t DLL; 265 } OFFSET_0; 266 union 267 { 268 __IO uint32_t DLH; 269 __IO uint32_t IER; 270 } OFFSET_4; 271 union 272 { 273 __I uint32_t IIR; 274 __O uint32_t FCR; 275 } OFFSET_8; 276 __IO uint32_t LCR; 277 __IO uint32_t MCR; 278 __I uint32_t LSR; 279 __I uint32_t MSR; 280 __IO uint32_t SCR; 281 __IO uint32_t LPDLL; 282 __IO uint32_t LPDLH; 283 __I uint32_t RES0[2]; 284 union 285 { 286 __I uint32_t SRBR[16]; 287 __O uint32_t STHR[16]; 288 } OFFSET_48; 289 __IO uint32_t FAR; 290 __I uint32_t TFR; 291 __O uint32_t RFW; 292 __I uint32_t USR; 293 __I uint32_t TFL; 294 __I uint32_t RFL; 295 __O uint32_t SRR; 296 __IO uint32_t SRTS; 297 __IO uint32_t SBCR; 298 __IO uint32_t SDMAM; 299 __IO uint32_t SFE; 300 __IO uint32_t SRT; 301 __IO uint32_t STET; 302 __IO uint32_t HTX; 303 __O uint32_t DMASA; 304 __I uint32_t RES1[18]; 305 __I uint32_t CPR; 306 __I uint32_t UCV; 307 __I uint32_t CTR; 308 309 } UART_TypeDef; 310 311 typedef struct 312 { 313 __IO uint16_t CTRLR0; 314 uint16_t RESERVED0; 315 __IO uint16_t CTRLR1; 316 uint16_t RESERVED1; 317 __IO uint32_t SSIENR; 318 __IO uint32_t MWCR; 319 __IO uint32_t SER; 320 __IO uint32_t BAUDR; 321 __IO uint32_t TXFTLR; 322 __IO uint32_t RXFTLR; 323 __I uint32_t TXFLR; 324 __I uint32_t RXFLR; 325 __I uint32_t SR; 326 __IO uint32_t IMR; 327 __I uint32_t ISR; 328 __I uint32_t RISR; 329 __I uint32_t TXOICR; 330 __I uint32_t RXOICR; 331 __I uint32_t RXUICR; 332 __I uint32_t MSTICR; 333 __IO uint32_t ICR; 334 __IO uint32_t DMACR; 335 __IO uint32_t DMATDLR; 336 __IO uint32_t DMARDLR; 337 __I uint32_t IDR; 338 __I uint32_t SSI_COMP_VERSION; 339 __IO uint32_t DR; 340 __IO uint32_t DR_Array[35]; 341 __IO uint32_t RX_SAMPLE_DLY; 342 } SPI_TypeDef; 343 344 typedef struct 345 { 346 __IO uint32_t FCU_CMD; 347 __O uint32_t ADDRES; 348 __IO uint32_t BYTE_NUM; 349 __O uint32_t WR_FIFO; 350 __I uint32_t RD_FIFO; 351 __IO uint32_t DEVICE_PARA; 352 __IO uint32_t REG_WDATA; 353 __O uint32_t REG_RDATA; 354 __IO uint32_t INT_MASK; 355 __IO uint32_t INT_UMASK; 356 __IO uint32_t INT_MASK_STATUS; 357 __IO uint32_t INT_STATUS; 358 __IO uint32_t INT_RAWSTATUS; 359 __IO uint32_t INT_CLEAR; 360 __IO uint32_t CACHE_INTF_CMD; 361 __IO uint32_t DMA_CNTL; 362 __IO uint32_t FIFO_CNTL; 363 } QSPI_TypeDef; 364 365 typedef struct 366 { 367 __IO uint32_t CACHE_I0; 368 __IO uint32_t CACHE_I1; 369 __IO uint32_t CACHE_I2; 370 __IO uint32_t CACHE_I3; 371 __IO uint32_t CACHE_K0; 372 __IO uint32_t CACHE_K1; 373 __IO uint32_t CACHE_K2; 374 __IO uint32_t CACHE_K3; 375 __IO uint32_t CACHE_CS; 376 __IO uint32_t CACHE_REF; 377 __I uint32_t CACHE_RSVD0[(0x40-0x28) >> 2]; 378 __IO uint32_t CACHE_CONFIG; 379 __I uint32_t CACHE_RSVD1[(0x74-0x44) >> 2]; 380 __IO uint32_t CACHE_SADDR; 381 __IO uint32_t CACHE_EADDR; 382 383 } CACHE_TypeDef; 384 385 typedef struct 386 { 387 __IO uint32_t CR0; /*!< HSPIM Control register0 */ 388 __IO uint32_t FLCR; /*!< HSPIM Flow Control register */ 389 __IO uint32_t FLSR; /*!< HSPIM Flow Status register */ 390 __IO uint32_t FCR; /*!< HSPIM FIFO Control register */ 391 __I uint32_t RDR; /*!< HSPIM Read Data register */ 392 __O uint32_t WDR; /*!< HSPIM Write Data register */ 393 __I uint32_t SR; /*!< HSPIM Status register */ 394 __IO uint32_t CR1; /*!< HSPIM Control register1 */ 395 __IO uint32_t FSR; /*!< HSPIM FIFO Status register */ 396 __IO uint32_t DCR; /*!< HSPIM DMA Control register */ 397 __I uint32_t TISR; /*!< HSPIM TX Interrput Status register */ 398 __I uint32_t RISR; /*!< HSPIM RX Interrput Status register */ 399 }HSPIM_TypeDef; 400 401 typedef struct 402 { 403 __IO uint32_t SMU_CTRL; 404 __IO uint32_t FPM_CTRL; 405 __O uint32_t INTR_STAT; 406 __IO uint32_t INTR_CTRL; 407 __IO uint32_t RESERVED1[12]; 408 __IO uint32_t SMU_OP1; 409 __IO uint32_t SMU_OP2; 410 __O uint32_t SMU_RES; 411 __IO uint32_t RESERVED2[13]; 412 __IO float MATRIX1_00; 413 __IO float MATRIX1_01; 414 __IO float MATRIX1_02; 415 __IO float MATRIX1_10; 416 __IO float MATRIX1_11; 417 __IO float MATRIX1_12; 418 __IO float MATRIX1_20; 419 __IO float MATRIX1_21; 420 __IO float MATRIX1_22; 421 __IO uint32_t RESERVED3[7]; 422 __IO float MATRIX2_00; 423 __IO float MATRIX2_01; 424 __IO float MATRIX2_02; 425 __IO uint32_t RESERVED4[13]; 426 __IO uint32_t TABLE1_LEN; 427 __IO uint32_t TABLE2_LEN; 428 __IO uint32_t ACC; 429 __IO uint32_t POSITION; 430 __IO uint32_t VAL3; 431 __IO uint32_t RESERVED5[443]; 432 __IO uint32_t TABLE1_RAM; 433 __IO uint32_t RESERVED6[255]; 434 __IO uint32_t TABLE2_RAM; 435 __IO uint32_t RESERVED7[63]; 436 }QRCODE_TypeDef; 437 438 439 typedef struct 440 { 441 __IO uint32_t WDT_CR; 442 __IO uint32_t RESERVED0; 443 __I uint32_t WDT_CCVR; 444 __O uint32_t WDT_CRR; 445 __I uint32_t WDT_STAT; 446 __I uint32_t WDT_EOI; 447 __I uint32_t RESERVED1; 448 __IO uint32_t WDT_RLD; 449 __I uint32_t RESERVED[53]; 450 __I uint32_t WDT_COMP_PARAMS_1; 451 __I uint32_t WDT_COMP_VERSION; 452 __I uint32_t WDT_COMP_TYPE; 453 } WDT_TypeDef; 454 455 typedef struct 456 { 457 __IO uint32_t CRC_CSR; 458 __O uint32_t CRC_INI; 459 union 460 { 461 __I uint32_t DOUT; 462 __O uint8_t DIN; 463 } CRC_DATA; 464 } CRC_TypeDef; 465 466 typedef struct 467 { 468 __IO uint32_t LoadCount; 469 __I uint32_t CurrentValue; 470 __IO uint32_t ControlReg; 471 __IO uint32_t EOI; 472 __I uint32_t IntStatus; 473 } TIM_TypeDef; 474 475 #define TIM_NUM 8 476 typedef struct 477 { 478 TIM_TypeDef TIM[TIM_NUM]; 479 __I uint32_t TIM_IntStatus; 480 __I uint32_t TIM_EOI; 481 __I uint32_t TIM_RawIntStatus; 482 __I uint32_t TIM_Comp; 483 __IO uint32_t TIM_ReloadCount[TIM_NUM]; 484 } TIM_Module_TypeDef; 485 486 typedef struct 487 { 488 __IO uint32_t ADC_CR1; 489 __I uint32_t ADC_SR; 490 __IO uint32_t ADC_FIFO; 491 __I uint32_t ADC_DATA; 492 __I uint32_t ADC_FIFO_FL; 493 __IO uint32_t ADC_FIFO_THR; 494 __IO uint32_t ADC_CR2; 495 } ADC_TypeDef; 496 497 typedef struct 498 { 499 __IO uint32_t DAC_CR1; 500 __IO uint32_t DAC_DATA; 501 __IO uint32_t DAC_TIMER; 502 __I uint32_t DAC_FIFO_FL; 503 __IO uint32_t DAC_FIFO_THR; 504 } DAC_TypeDef; 505 506 typedef struct 507 { 508 __IO uint32_t AWD_CR1; 509 __IO uint32_t AWD_CR2; 510 __I uint32_t AWD_SR; 511 } AWD_TypeDef; 512 513 typedef struct 514 { 515 __IO uint32_t IODR; 516 __IO uint32_t BSRR; 517 __IO uint32_t OEN; 518 __IO uint32_t PUE; 519 } GPIO_TypeDef; 520 521 typedef struct 522 { 523 __IO uint32_t INTP_TYPE; 524 __IO uint32_t INTP_STA; 525 } GPIO_INTP_TypeDef; 526 527 #define GPIO_GROUP_NUM 6 528 typedef struct 529 { 530 GPIO_TypeDef GPIO[GPIO_GROUP_NUM]; 531 __I uint32_t RSVD0[(0x114 - 0x060)>>2]; 532 __I uint32_t INTP[GPIO_GROUP_NUM]; 533 __I uint32_t RSVD1[(0x180 - 0x12C)>>2]; 534 __IO uint32_t ALT[GPIO_GROUP_NUM]; 535 __I uint32_t RSVD2[(0x200 - 0x198)>>2]; 536 __IO uint32_t SYS_CR1; 537 __I uint32_t RSVD3[(0x220 - 0x204)>>2]; 538 __IO uint32_t WAKE_TYPE_EN; 539 __IO uint32_t WAKE_P0_EN; 540 __IO uint32_t WAKE_P1_EN; 541 __IO uint32_t WAKE_P2_EN; 542 __IO uint32_t WAKE_P3_EN; 543 __I uint32_t RSVD5[(0x800 - 0x234)>>2]; 544 GPIO_INTP_TypeDef INTP_TYPE_STA[GPIO_GROUP_NUM]; 545 } GPIO_MODULE_TypeDef; 546 547 548 typedef struct 549 { 550 __IO uint32_t FLAG[(0x0174 - 0x00164) >> 2]; 551 } FLAG_TypeDef; 552 553 #define BPK_KEY_NUM 16 554 typedef struct 555 { 556 __IO uint32_t KEY[BPK_KEY_NUM]; 557 __I uint32_t BPK_RSVD0[(0x80-0x40)>>2]; 558 __IO uint32_t BPK_RDY; 559 __IO uint32_t BPK_CLR; 560 __IO uint32_t BPK_LRA; 561 __IO uint32_t BPK_LWA; 562 __I uint32_t BPK_RSVD1; 563 __IO uint32_t BPK_LR; 564 __IO uint32_t BPK_SCR; 565 __IO uint32_t BPK_POWER; 566 567 __IO uint32_t RTC_CS; 568 __IO uint32_t RTC_REF; 569 __IO uint32_t RTC_ARM; 570 __I uint32_t RTC_TIM; 571 __O uint32_t RTC_INTCLR; 572 __IO uint32_t OSC32K_CR; 573 __IO uint32_t RTC_ATTA_TIM; 574 575 __IO uint32_t BPK_RR; 576 __IO uint32_t SEN_EXT_TYPE; 577 __IO uint32_t SEN_EXT_CFG; 578 __IO uint32_t SEN_SOFT_EN; 579 __IO uint32_t SEN_STATE; 580 __IO uint32_t SEN_BRIDGE; 581 __IO uint32_t SEN_SOFT_ATTACK; 582 __IO uint32_t SEN_SOFT_LOCK; 583 __IO uint32_t SEN_ATTACK_CNT; 584 __IO uint32_t SEN_ATTACK_TYP; 585 __IO uint32_t SEN_VG_DETECT; 586 __IO uint32_t SEN_RNG_INI; 587 __IO uint32_t RESERVED3[(0x0104 - 0x00EC) >> 2]; 588 __IO uint32_t SEN_EN[19]; 589 __IO uint32_t SEN_EXTS_START; 590 __IO uint32_t SEN_LOCK; 591 __IO uint32_t SEN_ANA0; 592 __IO uint32_t SEN_ANA1; 593 __IO uint32_t SEN_ATTCLR; 594 FLAG_TypeDef SEN_FLAG; 595 __IO uint32_t SEN_DEBUG; 596 __I uint32_t BPU_RSVD4[(0x200- 0x178) >> 2]; 597 __IO uint32_t BPK_RAM[(0x600-0x200) >> 2]; 598 } BPU_TypeDef; 599 600 typedef struct 601 { 602 __IO uint32_t KEY[BPK_KEY_NUM]; 603 __I uint32_t BPK_RSVD0[(0x80-0x40) >> 2]; 604 __IO uint32_t BPK_RDY; 605 __IO uint32_t BPK_CLR; 606 __IO uint32_t BPK_LRA; 607 __IO uint32_t BPK_LWA; 608 __I uint32_t BPK_RSVD1; 609 __IO uint32_t BPK_LR; 610 __IO uint32_t BPK_SCR; 611 __IO uint32_t BPK_POWER; 612 } BPK_TypeDef; 613 614 typedef struct 615 { 616 __IO uint32_t RTC_CS; 617 __IO uint32_t RTC_REF; 618 __IO uint32_t RTC_ARM; 619 __I uint32_t RTC_TIM; 620 __O uint32_t RTC_INTCLR; 621 __IO uint32_t OSC32K_CR; 622 __IO uint32_t RTC_ATTA_TIM; 623 } RTC_TypeDef; 624 625 #define EXT_SENSOR_NUM 8 626 #define INNER_SENSOR_NUM 7 627 typedef struct 628 { 629 __IO uint32_t BPK_RR; 630 __IO uint32_t SEN_EXT_TYPE; 631 __IO uint32_t SEN_EXT_CFG; 632 __IO uint32_t SEN_SOFT_EN; 633 __IO uint32_t SEN_STATE; 634 __IO uint32_t SEN_BRIDGE; 635 __IO uint32_t SEN_SOFT_ATTACK; 636 __IO uint32_t SEN_SOFT_LOCK; 637 __IO uint32_t SEN_ATTACK_CNT; 638 __IO uint32_t SEN_ATTACK_TYP; 639 __IO uint32_t SEN_VG_DETECT; 640 __IO uint32_t SEN_RNG_INI; 641 __IO uint32_t RESERVED3[(0x0104-0x00EC) >> 2]; 642 __IO uint32_t SEN_EN[19]; 643 __IO uint32_t SEN_EXTS_START; 644 __IO uint32_t SEN_LOCK; 645 __IO uint32_t SEN_ANA0; 646 __IO uint32_t SEN_ANA1; 647 __IO uint32_t SEN_ATTCLR; 648 FLAG_TypeDef SEN_FLAG; 649 __IO uint32_t SEN_DEBUG; 650 __I uint32_t RESERVED4[(0x200- 0x178) >> 2]; 651 __IO uint32_t BPK_RAM[(0x600-0x200) >> 2]; 652 } SEN_TypeDef; 653 654 655 typedef struct 656 { 657 __IO uint32_t RNG_CSR; 658 __IO uint32_t RNG_DATA[1]; 659 __I uint32_t RES; 660 __IO uint32_t RNG_ANA; 661 __IO uint32_t RNG_PN; 662 __IO uint32_t RNG_INDEX; 663 } TRNG_TypeDef; 664 665 typedef struct 666 { 667 __IO uint32_t IC_CON; 668 __IO uint32_t IC_TAR; 669 __IO uint32_t IC_SAR; 670 __IO uint32_t IC_HS_MADDR; 671 __IO uint32_t IC_DATA_CMD; 672 __IO uint32_t IC_SS_SCL_HCNT; 673 __IO uint32_t IC_SS_SCL_LCNT; 674 __IO uint32_t IC_FS_SCL_HCNT; 675 __IO uint32_t IC_FS_SCL_LCNT; 676 __IO uint32_t IC_HS_SCL_HCNT; 677 __IO uint32_t IC_HS_SCL_LCNT; 678 __I uint32_t IC_INTR_STAT; 679 __IO uint32_t IC_INTR_MASK; 680 __I uint32_t IC_RAW_INTR_STAT; 681 __IO uint32_t IC_RX_TL; 682 __IO uint32_t IC_TX_TL; 683 __I uint32_t IC_CLR_INTR; 684 __I uint32_t IC_CLR_RX_UNDER; 685 __I uint32_t IC_CLR_RX_OVER; 686 __I uint32_t IC_CLR_TX_OVER; 687 __I uint32_t IC_CLR_RD_REQ; 688 __I uint32_t IC_CLR_TX_ABRT; 689 __I uint32_t IC_CLR_RX_DONE; 690 __I uint32_t IC_CLR_ACTIVITY; 691 __I uint32_t IC_CLR_STOP_DET; 692 __I uint32_t IC_CLR_START_DET; 693 __I uint32_t IC_CLR_GEN_CALL; 694 __IO uint32_t IC_ENABLE; 695 __I uint32_t IC_STATUS; 696 __I uint32_t IC_TXFLR; 697 __I uint32_t IC_RXFLR; 698 __IO uint32_t IC_SDA_HOLD; 699 __I uint32_t IC_TX_ABRT_SOURCE; 700 __IO uint32_t IC_SLV_DATA_NACK_ONLY; 701 __IO uint32_t IC_DMA_CR; 702 __IO uint32_t IC_DMA_TDLR; 703 __IO uint32_t IC_DMA_RDLR; 704 __IO uint32_t IC_SDA_SETUP; 705 __IO uint32_t IC_ACK_GENERAL_CALL; 706 __I uint32_t IC_ENABLE_STATUS; 707 __IO uint32_t IC_FS_SPKLEN; 708 __IO uint32_t IC_HS_SPKLEN; 709 } I2C_TypeDef; 710 711 typedef struct 712 { 713 __IO uint32_t KCU_CTRL0; 714 __IO uint32_t KCU_CTRL1; 715 __I uint32_t KCU_STATUS; 716 __I uint32_t KCU_EVENT; 717 __IO uint32_t KCU_RNG; 718 } KCU_TypeDef; 719 720 typedef struct 721 { 722 __IO uint32_t SAR_L; 723 __IO uint32_t SAR_H; 724 __IO uint32_t DAR_L; 725 __IO uint32_t DAR_H; 726 __IO uint32_t LLP_L; 727 __IO uint32_t LLP_H; 728 __IO uint32_t CTL_L; 729 __IO uint32_t CTL_H; 730 __IO uint32_t SSTAT_L; 731 __IO uint32_t SSTAT_H; 732 __IO uint32_t DSTAT_L; 733 __IO uint32_t DSTAT_H; 734 __IO uint32_t SSTATAR_L; 735 __IO uint32_t SSTATAR_H; 736 __IO uint32_t DSTATAR_L; 737 __IO uint32_t DSTATAR_H; 738 __IO uint32_t CFG_L; 739 __IO uint32_t CFG_H; 740 __IO uint32_t SGR_L; 741 __IO uint32_t SGR_H; 742 __IO uint32_t DSR_L; 743 __IO uint32_t DSR_H; 744 } DMA_TypeDef; 745 746 typedef struct 747 { 748 DMA_TypeDef DMA_Channel[8]; 749 750 __I uint32_t RawTfr_L; 751 __I uint32_t RawTfr_H; 752 __I uint32_t RawBlock_L; 753 __I uint32_t RawBlock_H; 754 __I uint32_t RawSrcTran_L; 755 __I uint32_t RawSrcTran_H; 756 __I uint32_t RawDstTran_L; 757 __I uint32_t RawDstTran_H; 758 __I uint32_t RawErr_L; 759 __I uint32_t RawErr_H; 760 761 __I uint32_t StatusTfr_L; 762 __I uint32_t StatusTfr_H; 763 __I uint32_t StatusBlock_L; 764 __I uint32_t StatusBlock_H; 765 __I uint32_t StatusSrcTran_L; 766 __I uint32_t StatusSrcTran_H; 767 __I uint32_t StatusDstTran_L; 768 __I uint32_t StatusDstTran_H; 769 __I uint32_t StatusErr_L; 770 __I uint32_t StatusErr_H; 771 772 __IO uint32_t MaskTfr_L; 773 __IO uint32_t MaskTfr_H; 774 __IO uint32_t MaskBlock_L; 775 __IO uint32_t MaskBlock_H; 776 __IO uint32_t MaskSrcTran_L; 777 __IO uint32_t MaskSrcTran_H; 778 __IO uint32_t MaskDstTran_L; 779 __IO uint32_t MaskDstTran_H; 780 __IO uint32_t MaskErr_L; 781 __IO uint32_t MaskErr_H; 782 783 __O uint32_t ClearTfr_L; 784 __O uint32_t ClearTfr_H; 785 __O uint32_t ClearBlock_L; 786 __O uint32_t ClearBlock_H; 787 __O uint32_t ClearSrcTran_L; 788 __O uint32_t ClearSrcTran_H; 789 __O uint32_t ClearDstTran_L; 790 __O uint32_t ClearDstTran_H; 791 __O uint32_t ClearErr_L; 792 __O uint32_t ClearErr_H; 793 794 __I uint32_t StatusInt_L; 795 __I uint32_t StatusInt_H; 796 797 __IO uint32_t ReqSrcReg_L; 798 __IO uint32_t ReqSrcReg_H; 799 __IO uint32_t ReqDstReg_L; 800 __IO uint32_t ReqDstReg_H; 801 __IO uint32_t SglReqSrcReg_L; 802 __IO uint32_t SglReqSrcReg_H; 803 __IO uint32_t SglReqDstReg_L; 804 __IO uint32_t SglReqDstReg_H; 805 __IO uint32_t LstSrcReg_L; 806 __IO uint32_t LstSrcReg_H; 807 __IO uint32_t LstDstReg_L; 808 __IO uint32_t LstDstReg_H; 809 810 __IO uint32_t DmaCfgReg_L; 811 __IO uint32_t DmaCfgReg_H; 812 __IO uint32_t ChEnReg_L; 813 __IO uint32_t ChEnReg_H; 814 __I uint32_t DmaIdReg_L; 815 __I uint32_t DmaIdReg_H; 816 __IO uint32_t DmaTestReg_L; 817 __IO uint32_t DmaTestReg_H; 818 819 __IO uint32_t RESERVED2[4]; 820 821 __I uint32_t DMA_COMP_PARAMS_6_L; 822 __I uint32_t DMA_COMP_PARAMS_6_H; 823 __I uint32_t DMA_COMP_PARAMS_5_L; 824 __I uint32_t DMA_COMP_PARAMS_5_H; 825 __I uint32_t DMA_COMP_PARAMS_4_L; 826 __I uint32_t DMA_COMP_PARAMS_4_H; 827 __I uint32_t DMA_COMP_PARAMS_3_L; 828 __I uint32_t DMA_COMP_PARAMS_3_H; 829 __I uint32_t DMA_COMP_PARAMS_2_L; 830 __I uint32_t DMA_COMP_PARAMS_2_H; 831 __I uint32_t DMA_COMP_PARAMS_1_L; 832 __I uint32_t DMA_COMP_PARAMS_1_H; 833 __I uint32_t DMA_Component_ID_Register_L; 834 __I uint32_t DMA_Component_ID_Register_H; 835 836 } DMA_MODULE_TypeDef; 837 838 typedef struct 839 { 840 __IO uint32_t lcdi_ctrl; 841 __IO uint32_t lcdi_cycle; 842 __IO uint32_t lcdi_status; 843 __IO uint32_t lcdi_data; 844 __IO uint32_t lcdi_fifolevel; 845 __IO uint32_t lcdi_fifothr; 846 } LCD_TypeDef; 847 848 typedef struct 849 { 850 __IO uint32_t SCI_DATA; 851 __IO uint32_t SCI_CR0; 852 __IO uint32_t SCI_CR1; 853 __IO uint32_t SCI_CR2; 854 __IO uint32_t SCI_IER; 855 __IO uint32_t SCI_RETRY; 856 __IO uint32_t SCI_TIDE; 857 __IO uint32_t SCI_TXCOUNT; 858 __IO uint32_t SCI_RXCOUNT; 859 __I uint32_t SCI_FR; 860 __IO uint32_t SCI_RXTIME; 861 __IO uint32_t SCI_ISTAT; 862 __IO uint32_t SCI_STABLE; 863 __IO uint32_t SCI_ATIME; 864 __IO uint32_t SCI_DTIME; 865 866 __IO uint32_t SCI_ATRSTIME; 867 __IO uint32_t SCI_ATRDTIME; 868 __IO uint32_t SCI_BLKTIME; 869 __IO uint32_t SCI_CHTIME; 870 __IO uint32_t SCI_CLKICC; 871 __IO uint32_t SCI_BAUD; 872 __IO uint32_t SCI_VALUE; 873 __IO uint32_t SCI_CHGUARD; 874 __IO uint32_t SCI_BLKGUARD; 875 __IO uint32_t SCI_SYNCCR; 876 __IO uint32_t SCI_SYNCDATA; 877 __IO uint32_t SCI_RAWSTAT; 878 __IO uint32_t SCI_IIR; 879 __I uint32_t SCI_RES1[4]; 880 __I uint32_t SCI_RES2[32]; 881 } SCI_TypeDef; 882 883 884 885 /** 886 * @brief DCMI&IMG COP 887 */ 888 889 typedef struct 890 { 891 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ 892 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ 893 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ 894 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ 895 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ 896 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ 897 __IO uint32_t RESERVED1[2]; 898 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ 899 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ 900 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ 901 } DCMI_TypeDef; 902 typedef struct 903 { 904 __IO uint32_t RESERVED[(0x2000-0x0000)/4]; 905 __IO uint32_t CFG; 906 __IO uint32_t CS; 907 __IO uint32_t PROT; 908 __IO uint32_t ADDR; 909 __IO uint32_t PDATA; 910 __IO uint32_t RO; 911 __IO uint32_t ROL; 912 __IO uint32_t RSVD; 913 __IO uint32_t TIM; 914 __IO uint32_t TIM_EN; 915 } OTP_TypeDef; 916 917 typedef struct 918 { 919 __IO uint32_t RESERVED0[(0x0008-0x0000) >> 2]; 920 __IO uint32_t SSC_CR3; 921 __O uint32_t RESERVED1[(0x0104-0x000C) >> 2]; 922 __IO uint32_t SSC_SR; 923 __IO uint32_t SSC_SR_CLR; 924 __IO uint32_t SSC_ACK; 925 __O uint32_t RESERVED2[(0x0184-0x0110) >> 2]; 926 __IO uint32_t DATARAM_SCR; 927 __O uint32_t RESERVED3[(0x01FC-0x0188) >> 2]; 928 __IO uint32_t BPU_RWC; 929 __O uint32_t RESERVED4[(0x03EC-0x0200) >> 2]; 930 __IO uint32_t MAIN_SEN_LOCK; 931 __IO uint32_t MAIN_SEN_EN; 932 } SSC_TypeDef; 933 934 typedef struct 935 { 936 __IO uint32_t TST_JTAG; 937 __IO uint32_t TST_ROM; 938 __IO uint32_t TST_FLASH; 939 } MH_SMCU_TST_TypeDef; 940 941 942 #if defined ( __CC_ARM ) 943 #pragma no_anon_unions 944 #endif 945 946 /*@}*/ /* end of group <Device>_Peripherals */ 947 948 949 /******************************************************************************/ 950 /* Peripheral memory map */ 951 /******************************************************************************/ 952 /* ToDo: add here your device peripherals base addresses 953 following is an example for timer */ 954 /** @addtogroup <Device>_MemoryMap <Device> Memory Mapping 955 @{ 956 */ 957 958 /* Peripheral and SRAM base address */ 959 #define AIR105_FLASH_BASE (0x01000000UL) /*!< (FLASH ) Base Address */ 960 #define AIR105_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ 961 #define AIR105_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ 962 963 #define AIR105_SRAM_SIZE (0xA0000) 964 965 #define AIR105_OTP_BASE (0x40008000UL) 966 #define AIR105_OTP_SIZE (1UL << 13) 967 968 /* Peripheral memory map */ 969 #define AIR105_AHB_BASE (AIR105_PERIPH_BASE) 970 #define AIR105_APB0_BASE (AIR105_PERIPH_BASE + 0x10000) 971 #define AIR105_APB1_BASE (AIR105_PERIPH_BASE + 0x20000) 972 #define AIR105_APB2_BASE (AIR105_PERIPH_BASE + 0x30000) 973 #define AIR105_APB3_BASE (AIR105_PERIPH_BASE + 0x40000) 974 975 #define SSC_BASE (AIR105_AHB_BASE + 0x0000) 976 #define TST_BASE (AIR105_AHB_BASE + 0x03F4) 977 #define DMA_BASE (AIR105_AHB_BASE + 0x0800) 978 #define USB_BASE (AIR105_AHB_BASE + 0x0C00) 979 #define LCD_BASE (AIR105_AHB_BASE + 0x1000) 980 #define OTP_BASE (AIR105_AHB_BASE + 0x8000) 981 #define DCMI_BASE (AIR105_AHB_BASE + 0x60000) 982 #define CACHE_BASE (AIR105_AHB_BASE + 0x80000) 983 #define QRCODE_BASE (AIR105_AHB_BASE + 0x90000) 984 #define GPU_BASE (AIR105_AHB_BASE + 0xA1000) 985 #define QSPI_BASE (AIR105_AHB_BASE + 0xA2000) 986 #define HSPI_BASE (AIR105_AHB_BASE + 0xA3000) 987 988 #define SCI0_BASE (AIR105_APB0_BASE) 989 #define CRC_BASE (AIR105_APB0_BASE + 0x2000) 990 #define TIMM0_BASE (AIR105_APB0_BASE + 0x3000) 991 #define ADC_BASE (AIR105_APB0_BASE + 0x4000) 992 #define DAC_BASE (AIR105_APB0_BASE + 0x4100) 993 #define AWD_BASE (AIR105_APB0_BASE + 0x4200) 994 #define SCI2_BASE (AIR105_APB0_BASE + 0x5000) 995 #define UART0_BASE (AIR105_APB0_BASE + 0x6000) 996 #define UART1_BASE (AIR105_APB0_BASE + 0x7000) 997 #define SPIM1_BASE (AIR105_APB0_BASE + 0x8000) 998 #define SPIM2_BASE (AIR105_APB0_BASE + 0x9000) 999 #define SPIM0_BASE (AIR105_APB0_BASE + 0xA000) 1000 #define SPIS0_BASE (AIR105_APB0_BASE + 0xB000) 1001 #define WDG_BASE (AIR105_APB0_BASE + 0xC000) 1002 #define GPIO_BASE (AIR105_APB0_BASE + 0xD000) 1003 #define TRNG_BASE (AIR105_APB0_BASE + 0xE000) 1004 #define SYSCTRL_BASE (AIR105_APB0_BASE + 0xF000) 1005 1006 #define MSR_BASE (AIR105_APB1_BASE) 1007 1008 #define BPU_BASE (AIR105_APB2_BASE) 1009 1010 1011 #define UART2_BASE (AIR105_APB3_BASE + 0x4000) 1012 #define UART3_BASE (AIR105_APB3_BASE + 0x5000) 1013 #define KEYBOARD_BASE (AIR105_APB3_BASE + 0x8000) 1014 #define I2C0_BASE (AIR105_APB3_BASE + 0x9000) 1015 1016 #define HSPIM_BASE (AIR105_AHB_BASE + 0xA3020) 1017 1018 /*@}*/ /* end of group <Device>_MemoryMap */ 1019 1020 1021 /******************************************************************************/ 1022 /* Peripheral declaration */ 1023 /******************************************************************************/ 1024 /* ToDo: add here your device peripherals pointer definitions 1025 following is an example for timer */ 1026 1027 /** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration 1028 @{ 1029 */ 1030 #define SYSCTRL ((SYSCTRL_TypeDef *) SYSCTRL_BASE) 1031 1032 #define UART0 ((UART_TypeDef *) UART0_BASE) 1033 #define UART1 ((UART_TypeDef *) UART1_BASE) 1034 #define UART2 ((UART_TypeDef *) UART2_BASE) 1035 #define UART3 ((UART_TypeDef *) UART3_BASE) 1036 1037 #define SPIM0 ((SPI_TypeDef *) SPIM0_BASE) 1038 #define SPIM1 ((SPI_TypeDef *) SPIM1_BASE) 1039 #define SPIM2 ((SPI_TypeDef *) SPIM2_BASE) 1040 1041 #define SPIS0 ((SPI_TypeDef *) SPIS0_BASE) 1042 1043 #define QSPI ((QSPI_TypeDef *) QSPI_BASE) 1044 1045 #define HSPIM ((HSPIM_TypeDef *) HSPIM_BASE) 1046 #define CACHE ((CACHE_TypeDef *)CACHE_BASE) 1047 #define QRCODE ((QRCODE_TypeDef *)QRCODE_BASE) 1048 #define GPU ((GPU_TypeDef *)GPU_BASE) 1049 #define SCI0 ((SCI_TypeDef *) SCI0_BASE) 1050 #define SCI2 ((SCI_TypeDef *) SCI2_BASE) 1051 1052 #define TIMM0 ((TIM_Module_TypeDef *)TIMM0_BASE) 1053 1054 #define ADC0 ((ADC_TypeDef *)ADC_BASE) 1055 #define DAC ((DAC_TypeDef *)DAC_BASE) 1056 #define AWD ((AWD_TypeDef *)AWD_BASE) 1057 1058 #define TRNG ((TRNG_TypeDef *)TRNG_BASE) 1059 #define LCD ((LCD_TypeDef *)LCD_BASE) 1060 #define KCU ((KCU_TypeDef *)KEYBOARD_BASE) 1061 #define CRC ((CRC_TypeDef *)CRC_BASE) 1062 #define OTP ((OTP_TypeDef *)OTP_BASE) 1063 1064 #define I2C0 ((I2C_TypeDef *)I2C0_BASE) 1065 1066 #define DMA ((DMA_MODULE_TypeDef *)DMA_BASE) 1067 #define DMA_Channel_0 ((DMA_TypeDef *)DMA_BASE) 1068 #define DMA_Channel_1 ((DMA_TypeDef *)(DMA_BASE + 0x58)) 1069 #define DMA_Channel_2 ((DMA_TypeDef *)(DMA_BASE + 0x58*2)) 1070 #define DMA_Channel_3 ((DMA_TypeDef *)(DMA_BASE + 0x58*3)) 1071 #define DMA_Channel_4 ((DMA_TypeDef *)(DMA_BASE + 0x58*4)) 1072 #define DMA_Channel_5 ((DMA_TypeDef *)(DMA_BASE + 0x58*5)) 1073 #define DMA_Channel_6 ((DMA_TypeDef *)(DMA_BASE + 0x58*6)) 1074 #define DMA_Channel_7 ((DMA_TypeDef *)(DMA_BASE + 0x58*7)) 1075 1076 1077 #define GPIO ((GPIO_MODULE_TypeDef *)GPIO_BASE) 1078 #define GPIOA ((GPIO_TypeDef *)GPIO_BASE) 1079 #define GPIOB ((GPIO_TypeDef *)(GPIO_BASE + 0x0010)) 1080 #define GPIOC ((GPIO_TypeDef *)(GPIO_BASE + 0x0020)) 1081 #define GPIOD ((GPIO_TypeDef *)(GPIO_BASE + 0x0030)) 1082 #define GPIOE ((GPIO_TypeDef *)(GPIO_BASE + 0x0040)) 1083 #define GPIOF ((GPIO_TypeDef *)(GPIO_BASE + 0x0050)) 1084 #define GPIO_GROUP ((GPIO_TypeDef *)GPIO_BASE) 1085 #define GPIO_ALT_GROUP ((__IO uint32_t *)(GPIO_BASE + 0x180)) 1086 #define GPIO_WKEN_TYPE_EN ((__IO uint32_t *)(GPIO_BASE + 0x220)) 1087 #define GPIO_WKEN_P0_EN ((__IO uint32_t *)(GPIO_BASE + 0x224)) 1088 #define GPIO_WKEN_P1_EN ((__IO uint32_t *)(GPIO_BASE + 0x228)) 1089 #define GPIO_WKEN_P2_EN ((__IO uint32_t *)(GPIO_BASE + 0x22C)) 1090 1091 #define WDT ((WDT_TypeDef *)WDG_BASE) 1092 #define SSC ((SSC_TypeDef *)SSC_BASE) 1093 #define TST ((MH_SMCU_TST_TypeDef *)TST_BASE) 1094 1095 #define DCMI ((DCMI_TypeDef *)DCMI_BASE) 1096 #define BPU ((BPU_TypeDef *)BPU_BASE) 1097 #define BPK ((BPK_TypeDef *)BPU_BASE) 1098 #define RTC ((RTC_TypeDef *)(BPU_BASE + 0xA0)) 1099 #define SENSOR ((SEN_TypeDef *)(BPU_BASE + 0xBC)) 1100 #define SEN_FLAG ((FLAG_TypeDef*)(BPU_BASE + 0x164)) 1101 1102 1103 /** @addtogroup Exported_constants 1104 * @{ 1105 */ 1106 1107 /** @addtogroup Peripheral_Registers_Bits_Definition 1108 * @{ 1109 */ 1110 1111 /******************************************************************************/ 1112 /* Peripheral Registers_Bits_Definition */ 1113 /******************************************************************************/ 1114 1115 /******************************************************************************/ 1116 /* */ 1117 /* System Control Unit */ 1118 /* */ 1119 /******************************************************************************/ 1120 1121 /******************* Bit definition for FREQ_SEL register *******************/ 1122 #define SYSCTRL_FREQ_SEL_XTAL_Pos (16) 1123 #define SYSCTRL_FREQ_SEL_XTAL_Mask (0x1F << SYSCTRL_FREQ_SEL_XTAL_Pos) 1124 #define SYSCTRL_FREQ_SEL_XTAL_108Mhz (0x08 << SYSCTRL_FREQ_SEL_XTAL_Pos) 1125 #define SYSCTRL_FREQ_SEL_XTAL_120Mhz (0x09 << SYSCTRL_FREQ_SEL_XTAL_Pos) 1126 #define SYSCTRL_FREQ_SEL_XTAL_132Mhz (0x0a << SYSCTRL_FREQ_SEL_XTAL_Pos) 1127 #define SYSCTRL_FREQ_SEL_XTAL_144Mhz (0x0b << SYSCTRL_FREQ_SEL_XTAL_Pos) 1128 #define SYSCTRL_FREQ_SEL_XTAL_156Mhz (0x0c << SYSCTRL_FREQ_SEL_XTAL_Pos) 1129 #define SYSCTRL_FREQ_SEL_XTAL_168Mhz (0x0d << SYSCTRL_FREQ_SEL_XTAL_Pos) 1130 #define SYSCTRL_FREQ_SEL_XTAL_180Mhz (0x0e << SYSCTRL_FREQ_SEL_XTAL_Pos) 1131 #define SYSCTRL_FREQ_SEL_XTAL_192Mhz (0x0f << SYSCTRL_FREQ_SEL_XTAL_Pos) 1132 #define SYSCTRL_FREQ_SEL_XTAL_204Mhz (0x10 << SYSCTRL_FREQ_SEL_XTAL_Pos) 1133 1134 #define SYSCTRL_FREQ_SEL_CLOCK_SOURCE_Pos (12) 1135 #define SYSCTRL_FREQ_SEL_CLOCK_SOURCE_Mask (0x01 << SYSCTRL_FREQ_SEL_CLOCK_SOURCE_Pos) 1136 #define SYSCTRL_FREQ_SEL_CLOCK_SOURCE_EXT (0x00 << SYSCTRL_FREQ_SEL_CLOCK_SOURCE_Pos) 1137 #define SYSCTRL_FREQ_SEL_CLOCK_SOURCE_INC (0x01 << SYSCTRL_FREQ_SEL_CLOCK_SOURCE_Pos) 1138 1139 #define SYSCTRL_FREQ_SEL_PLL_DIV_Pos (8) 1140 #define SYSCTRL_FREQ_SEL_PLL_DIV_Mask (0x03 << SYSCTRL_FREQ_SEL_PLL_DIV_Pos) 1141 #define SYSCTRL_FREQ_SEL_PLL_DIV_1_0 (0x00 << SYSCTRL_FREQ_SEL_PLL_DIV_Pos) 1142 #define SYSCTRL_FREQ_SEL_PLL_DIV_1_2 (0x01 << SYSCTRL_FREQ_SEL_PLL_DIV_Pos) 1143 #define SYSCTRL_FREQ_SEL_PLL_DIV_1_4 (0x02 << SYSCTRL_FREQ_SEL_PLL_DIV_Pos) 1144 1145 #define SYSCTRL_FREQ_SEL_HCLK_DIV_Pos (4) 1146 #define SYSCTRL_FREQ_SEL_HCLK_DIV_Mask (0x01 << SYSCTRL_FREQ_SEL_HCLK_DIV_Pos) 1147 #define SYSCTRL_FREQ_SEL_HCLK_DIV_1_0 (0x00 << SYSCTRL_FREQ_SEL_HCLK_DIV_Pos) 1148 #define SYSCTRL_FREQ_SEL_HCLK_DIV_1_2 (0x01 << SYSCTRL_FREQ_SEL_HCLK_DIV_Pos) 1149 1150 #define SYSCTRL_FREQ_SEL_PCLK_DIV_Pos (0) 1151 #define SYSCTRL_FREQ_SEL_PCLK_DIV_Mask (0x01 << SYSCTRL_FREQ_SEL_PCLK_DIV_Pos) 1152 #define SYSCTRL_FREQ_SEL_PCLK_DIV_1_2 (0x00 << SYSCTRL_FREQ_SEL_PCLK_DIV_Pos) 1153 #define SYSCTRL_FREQ_SEL_PCLK_DIV_1_4 (0x01 << SYSCTRL_FREQ_SEL_PCLK_DIV_Pos) 1154 1155 /******************* Bit definition for CG_CTRL2 register *******************/ 1156 #define SYSCTRL_AHBPeriph_DMA ((uint32_t)0x20000000) 1157 #define SYSCTRL_AHBPeriph_USB ((uint32_t)0x10000000) 1158 #define SYSCTRL_AHBPeriph_QR ((uint32_t)0x00000020) 1159 #define SYSCTRL_AHBPeriph_OTP ((uint32_t)0x00000008) 1160 #define SYSCTRL_AHBPeriph_GPU ((uint32_t)0x00000004) 1161 #define SYSCTRL_AHBPeriph_LCD ((uint32_t)0x00000002) 1162 #define SYSCTRL_AHBPeriph_CRYPT ((uint32_t)0x00000001) 1163 #define SYSCTRL_AHBPeriph_ALL ((uint32_t)0x3000002F) 1164 #define IS_SYSCTRL_AHB_PERIPH(PERIPH) ((((PERIPH) & ~SYSCTRL_AHBPeriph_ALL) == 0x00) && ((PERIPH) != 0x00)) 1165 1166 /******************* Bit definition for CG_CTRL1 register *******************/ 1167 #define SYSCTRL_APBPeriph_TRNG ((uint32_t)0x80000000) 1168 #define SYSCTRL_APBPeriph_ADC ((uint32_t)0x40000000) 1169 #define SYSCTRL_APBPeriph_CRC ((uint32_t)0x20000000) 1170 #define SYSCTRL_APBPeriph_KBD ((uint32_t)0x08000000) 1171 #define SYSCTRL_APBPeriph_BPU ((uint32_t)0x04000000) 1172 #define SYSCTRL_APBPeriph_DCMIS ((uint32_t)0x00800000) 1173 #define SYSCTRL_APBPeriph_TIMM0 ((uint32_t)0x00200000) 1174 #define SYSCTRL_APBPeriph_GPIO ((uint32_t)0x00100000) 1175 #define SYSCTRL_APBPeriph_I2C0 ((uint32_t)0x00040000) 1176 #define SYSCTRL_APBPeriph_SCI2 ((uint32_t)0x00010000) 1177 #define SYSCTRL_APBPeriph_SCI0 ((uint32_t)0x00004000) 1178 #define SYSCTRL_APBPeriph_HSPI ((uint32_t)0x00002000) 1179 #define SYSCTRL_APBPeriph_SPI2 ((uint32_t)0x00000400) 1180 #define SYSCTRL_APBPeriph_SPI1 ((uint32_t)0x00000200) 1181 #define SYSCTRL_APBPeriph_SPI0 ((uint32_t)0x00000100) 1182 #define SYSCTRL_APBPeriph_UART3 ((uint32_t)0x00000008) 1183 #define SYSCTRL_APBPeriph_UART2 ((uint32_t)0x00000004) 1184 #define SYSCTRL_APBPeriph_UART1 ((uint32_t)0x00000002) 1185 #define SYSCTRL_APBPeriph_UART0 ((uint32_t)0x00000001) 1186 #define SYSCTRL_APBPeriph_ALL ((uint32_t)0xECB5670F) 1187 #define IS_SYSCTRL_APB_PERIPH(PERIPH) ((((PERIPH) & ~SYSCTRL_APBPeriph_ALL) == 0x00) && ((PERIPH) != 0x00)) 1188 1189 /******************* Bit definition for SOFT_RST2 register *******************/ 1190 #define SYSCTRL_GLB_RESET ((uint32_t)0x80000000) 1191 #define SYSCTRL_CM3_RESET ((uint32_t)0x40000000) 1192 #define SYSCTRL_DMA_RESET ((uint32_t)0x20000000) 1193 #define SYSCTRL_USB_RESET ((uint32_t)0x10000000) 1194 #define SYSCTRL_QR_RESET ((uint32_t)0x00000020) 1195 #define SYSCTRL_OTP_RESET ((uint32_t)0x00000008) 1196 #define SYSCTRL_GPU_RESET ((uint32_t)0x00000004) 1197 #define SYSCTRL_LCD_RESET ((uint32_t)0x00000002) 1198 #define SYSCTRL_CRYPT_RESET ((uint32_t)0x00000001) 1199 #define SYSCTRL_AHBPeriph_RESET_ALL ((uint32_t)0xF000002F) 1200 #define IS_SYSCTRL_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & ~SYSCTRL_AHBPeriph_RESET_ALL) == 0x00) && ((PERIPH) != 0x00)) 1201 1202 /******************* Bit definition for PHER_CTRL register *******************/ 1203 #define SYSCTRL_PHER_CTRL_SPI0_SLV_EN ((uint32_t)0x01000000) /* 0:MASTER 1:SLAVE */ 1204 #define SYSCTRL_PHER_CTRL_SCI2_VCCEN_INV ((uint32_t)0x00400000) 1205 #define SYSCTRL_PHER_CTRL_SCI0_VCCEN_INV ((uint32_t)0x00100000) 1206 #define SYSCTRL_PHER_CTRL_SCI2_CDET_INV ((uint32_t)0x00040000) 1207 #define SYSCTRL_PHER_CTRL_SCI0_CDET_INV ((uint32_t)0x00010000) 1208 1209 /******************* Bit definition for DMA_CHAN REGISTER ********************/ 1210 #define SYSCTRL_PHER_CTRL_DMA_CH0_IF_Pos (0) 1211 #define SYSCTRL_PHER_CTRL_DMA_CH0_IF_Mask (0x3FU<<SYSCTRL_PHER_CTRL_DMA_CH0_IF_Pos) 1212 1213 #define SYSCTRL_PHER_CTRL_DMA_CH1_IF_Pos (8) 1214 #define SYSCTRL_PHER_CTRL_DMA_CH1_IF_Mask (0x3FU<<SYSCTRL_PHER_CTRL_DMA_CH1_IF_Pos) 1215 1216 #define SYSCTRL_PHER_CTRL_DMA_CH2_IF_Pos (16) 1217 #define SYSCTRL_PHER_CTRL_DMA_CH2_IF_Mask (0x3FU<<SYSCTRL_PHER_CTRL_DMA_CH2_IF_Pos) 1218 1219 #define SYSCTRL_PHER_CTRL_DMA_CH3_IF_Pos (24) 1220 #define SYSCTRL_PHER_CTRL_DMA_CH3_IF_Mask (0x3FU<<SYSCTRL_PHER_CTRL_DMA_CH3_IF_Pos) 1221 1222 #define SYSCTRL_PHER_CTRL_DMA_CH4_IF_Pos (0) 1223 #define SYSCTRL_PHER_CTRL_DMA_CH4_IF_Mask (0x3FU<<SYSCTRL_PHER_CTRL_DMA_CH4_IF_Pos) 1224 1225 #define SYSCTRL_PHER_CTRL_DMA_CH5_IF_Pos (8) 1226 #define SYSCTRL_PHER_CTRL_DMA_CH5_IF_Mask (0x3FU<<SYSCTRL_PHER_CTRL_DMA_CH5_IF_Pos) 1227 1228 #define SYSCTRL_PHER_CTRL_DMA_CH6_IF_Pos (16) 1229 #define SYSCTRL_PHER_CTRL_DMA_CH6_IF_Mask (0x3FU<<SYSCTRL_PHER_CTRL_DMA_CH6_IF_Pos) 1230 1231 #define SYSCTRL_PHER_CTRL_DMA_CH7_IF_Pos (24) 1232 #define SYSCTRL_PHER_CTRL_DMA_CH7_IF_Mask (0x3FU<<SYSCTRL_PHER_CTRL_DMA_CH7_IF_Pos) 1233 1234 1235 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_DCMI_TX (0x00) 1236 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_LCD (0x01) 1237 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART0_TX (0x02) 1238 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART0_RX (0x03) 1239 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART1_TX (0x04) 1240 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART1_RX (0x05) 1241 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_DAC (0x06) 1242 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_SPI0_TX (0x0A) 1243 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_SPI0_RX (0x0B) 1244 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_SPI1_TX (0x0C) 1245 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_SPI1_RX (0x0D) 1246 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_SPI2_TX (0x0E) 1247 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_SPI2_RX (0x0F) 1248 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART2_TX (0x14) 1249 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART2_RX (0x15) 1250 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART3_TX (0x16) 1251 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART3_RX (0x17) 1252 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_I2C_TX (0x18) 1253 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_I2C_RX (0x19) 1254 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_QSPI_TX (0x1A) 1255 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_HSPI_RX (0x20) 1256 #define SYSCTRL_PHER_CTRL_DMA_CHx_IF_HSPI_TX (0x21) 1257 1258 /******************************************************************************/ 1259 /* */ 1260 /* Universal Asynchronous Receiver Transmitter */ 1261 /* */ 1262 /******************************************************************************/ 1263 1264 /******************* Bit definition for UART_RBR register *******************/ 1265 #define UART_RBR_RBR ((uint32_t)0x01FF) /*!< Data value */ 1266 1267 /******************* Bit definition for UART_THR register *******************/ 1268 #define UART_THR_THR ((uint32_t)0x01FF) /*!< Data value */ 1269 1270 /******************* Bit definition for UART_DLH register *******************/ 1271 #define UART_DLH_DLH ((uint32_t)0x0FF) 1272 1273 /******************* Bit definition for UART_DLL register *******************/ 1274 #define UART_DLL_DLL ((uint32_t)0x0FF) 1275 1276 /******************* Bit definition for UART_IER register *******************/ 1277 #define UART_IER_ERBFI ((uint32_t)0x0001) 1278 #define UART_IER_ETBEI ((uint32_t)0x0002) 1279 #define UART_IER_ELSI ((uint32_t)0x0004) 1280 #define UART_IER_EDSSI ((uint32_t)0x0008) 1281 #define UART_IER_PTIME ((uint32_t)0x0080) 1282 1283 /******************* Bit definition for UART_IIR register *******************/ 1284 #define UART_IIR_IID ((uint32_t)0x0007) 1285 #define UART_IIR_IID_0 ((uint32_t)0x0001) 1286 #define UART_IIR_IID_1 ((uint32_t)0x0002) 1287 #define UART_IIR_IID_2 ((uint32_t)0x0004) 1288 #define UART_IIR_IID_3 ((uint32_t)0x0008) 1289 #define UART_IIR_FIFOSE ((uint32_t)0x0060) 1290 #define UART_IIR_FIFOSE_0 ((uint32_t)0x0020) 1291 #define UART_IIR_FIFOSE_1 ((uint32_t)0x0040) 1292 1293 /******************* Bit definition for UART_FCR register *******************/ 1294 #define UART_FCR_FIFOE ((uint32_t)0x0001) 1295 #define UART_FCR_RFIFOR ((uint32_t)0x0002) 1296 #define UART_FCR_XFIFOR ((uint32_t)0x0004) 1297 #define UART_FCR_DMAM ((uint32_t)0x0008) 1298 #define UART_FCR_TET ((uint32_t)0x0030) 1299 #define UART_FCR_TET_0 ((uint32_t)0x0010) 1300 #define UART_FCR_TET_1 ((uint32_t)0x0020) 1301 #define UART_FCR_RCVER ((uint32_t)0x00C0) 1302 #define UART_FCR_RCVER_0 ((uint32_t)0x0040) 1303 #define UART_FCR_RCVER_1 ((uint32_t)0x0080) 1304 1305 /******************* Bit definition for UART_LCR register *******************/ 1306 #define UART_LCR_DLS ((uint32_t)0x0003) 1307 #define UART_LCR_DLS_0 ((uint32_t)0x0001) 1308 #define UART_LCR_DLS_1 ((uint32_t)0x0002) 1309 #define UART_LCR_STOP ((uint32_t)0x0004) 1310 #define UART_LCR_PEN ((uint32_t)0x0008) 1311 #define UART_LCR_EPS ((uint32_t)0x0010) 1312 #define UART_LCR_SP ((uint32_t)0x0020) 1313 #define UART_LCR_BC ((uint32_t)0x0040) 1314 #define UART_LCR_DLAB ((uint32_t)0x0080) 1315 1316 /******************* Bit definition for UART_MCR register *******************/ 1317 #define UART_MCR_DTR ((uint32_t)0x0001) 1318 #define UART_MCR_RTS ((uint32_t)0x0002) 1319 #define UART_MCR_OUT1 ((uint32_t)0x0004) 1320 #define UART_MCR_OUT2 ((uint32_t)0x0008) 1321 #define UART_MCR_LB ((uint32_t)0x0010) 1322 #define UART_MCR_AFCE ((uint32_t)0x0020) 1323 #define UART_MCR_SIRE ((uint32_t)0x0040) 1324 1325 /******************* Bit definition for UART_LSR register *******************/ 1326 #define UART_LSR_DR ((uint32_t)0x0001) 1327 #define UART_LSR_OE ((uint32_t)0x0002) 1328 #define UART_LSR_PE ((uint32_t)0x0004) 1329 #define UART_LSR_FE ((uint32_t)0x0008) 1330 #define UART_LSR_BI ((uint32_t)0x0010) 1331 #define UART_LSR_THRE ((uint32_t)0x0020) 1332 #define UART_LSR_TEMT ((uint32_t)0x0040) 1333 #define UART_LSR_PFE ((uint32_t)0x0080) 1334 1335 /******************* Bit definition for UART_MSR register *******************/ 1336 #define UART_MSR_DCTS ((uint32_t)0x0001) 1337 #define UART_MSR_DDSR ((uint32_t)0x0002) 1338 #define UART_MSR_TERI ((uint32_t)0x0004) 1339 #define UART_MSR_DDCD ((uint32_t)0x0008) 1340 #define UART_MSR_CTS ((uint32_t)0x0010) 1341 #define UART_MSR_DSR ((uint32_t)0x0020) 1342 #define UART_MSR_RI ((uint32_t)0x0040) 1343 #define UART_MSR_DCD ((uint32_t)0x0080) 1344 1345 /******************* Bit definition for UART_SRBR register *******************/ 1346 #define UART_SRBR_SRBR ((uint32_t)0x01FF) /*!< Data value */ 1347 1348 /******************* Bit definition for UART_STHR register *******************/ 1349 #define UART_STHR_STHR ((uint32_t)0x01FF) /*!< Data value */ 1350 1351 /******************* Bit definition for UART_FAR register *******************/ 1352 #define UART_FAR_FAR ((uint32_t)0x0001) 1353 1354 /******************* Bit definition for UART_TFR register *******************/ 1355 #define UART_TFR_TFR ((uint32_t)0x00FF) 1356 1357 /******************* Bit definition for UART_RFW register *******************/ 1358 #define UART_RFW_RFWD ((uint32_t)0x00FF) 1359 #define UART_RFW_RFPE ((uint32_t)0x0100) 1360 #define UART_RFW_RFFE ((uint32_t)0x0200) 1361 1362 /******************* Bit definition for UART_USR register *******************/ 1363 #define UART_USR_BUSY ((uint32_t)0x0001) 1364 #define UART_USR_TFNF ((uint32_t)0x0002) 1365 #define UART_USR_TFE ((uint32_t)0x0004) 1366 #define UART_USR_RFNE ((uint32_t)0x0008) 1367 #define UART_USR_RFF ((uint32_t)0x0010) 1368 1369 /******************* Bit definition for UART_TFL register *******************/ 1370 #define UART_TFL_TFL ((uint32_t)0x000F) 1371 1372 /******************* Bit definition for UART_RFL register *******************/ 1373 #define UART_RFL_RFL ((uint32_t)0x000F) 1374 1375 /******************* Bit definition for UART_SRR register *******************/ 1376 #define UART_SRR_UR ((uint32_t)0x0001) 1377 #define UART_SRR_RFR ((uint32_t)0x0002) 1378 #define UART_SRR_XFR ((uint32_t)0x0004) 1379 1380 /******************* Bit definition for UART_SRR register *******************/ 1381 #define UART_SRR_UR ((uint32_t)0x0001) 1382 1383 /******************* Bit definition for UART_SRTS register *******************/ 1384 #define UART_SRTS_SRTS ((uint32_t)0x0001) 1385 1386 /******************* Bit definition for UART_SBCR register *******************/ 1387 #define UART_SBCR_SBCR ((uint32_t)0x0001) 1388 1389 /******************* Bit definition for UART_SDMAM register *******************/ 1390 #define UART_SDMAM_SDMAM ((uint32_t)0x0001) 1391 1392 /******************* Bit definition for UART_SFE register *******************/ 1393 #define UART_SFE_SFE ((uint32_t)0x0001) 1394 1395 /******************* Bit definition for UART_SRT register *******************/ 1396 #define UART_SRT_SRT ((uint32_t)0x0003) 1397 #define UART_SRT_SRT_0 ((uint32_t)0x0001) 1398 #define UART_SRT_SRT_1 ((uint32_t)0x0002) 1399 1400 /******************* Bit definition for UART_STET register *******************/ 1401 #define UART_STET_STET ((uint32_t)0x0003) 1402 #define UART_STET_STET_0 ((uint32_t)0x0001) 1403 #define UART_STET_STET_1 ((uint32_t)0x0002) 1404 1405 /******************* Bit definition for UART_HTX register *******************/ 1406 #define UART_HTX_HTX ((uint32_t)0x0001) 1407 1408 /******************* Bit definition for UART_DMASA register *******************/ 1409 #define UART_DMASA_DMASA ((uint32_t)0x0001) 1410 1411 /******************************************************************************/ 1412 /* */ 1413 /* General Purpose and Alternate Function I/O */ 1414 /* */ 1415 /******************************************************************************/ 1416 1417 /*!<****************** Bit definition for GPIO_IODR register *******************/ 1418 #define DEEP_SLEEP_WKUP_EN_SENSOR (BIT14) 1419 #define DEEP_SLEEP_WKUP_EN_MSR (BIT13) 1420 #define DEEP_SLEEP_WKUP_EN_RTC (BIT12) 1421 #define DEEP_SLEEP_WKUP_EN_KBD (BIT11) 1422 #define DEEP_SLEEP_WKUP_EN_GPIO (BIT0) 1423 1424 1425 /******************************************************************************/ 1426 /* */ 1427 /* Serial Peripheral Interface */ 1428 /* */ 1429 /******************************************************************************/ 1430 1431 /***************** Bit definition for SPI_CTRLR0 register *******************/ 1432 #define SPI_CTRLR0_DFS ((uint32_t)0x000F) 1433 #define SPI_CTRLR0_DFS_0 ((uint32_t)0x0001) 1434 #define SPI_CTRLR0_DFS_1 ((uint32_t)0x0002) 1435 #define SPI_CTRLR0_DFS_2 ((uint32_t)0x0004) 1436 #define SPI_CTRLR0_DFS_3 ((uint32_t)0x0008) 1437 #define SPI_CTRLR0_FRF ((uint32_t)0x0030) 1438 #define SPI_CTRLR0_FRF_0 ((uint32_t)0x0010) 1439 #define SPI_CTRLR0_FRF_1 ((uint32_t)0x0020) 1440 #define SPI_CTRLR0_SCPH ((uint32_t)0x0040) 1441 #define SPI_CTRLR0_SCPOL ((uint32_t)0x0080) 1442 #define SPI_CTRLR0_TMOD ((uint32_t)0x0300) 1443 #define SPI_CTRLR0_TMOD_0 ((uint32_t)0x0100) 1444 #define SPI_CTRLR0_TMOD_1 ((uint32_t)0x0200) 1445 #define SPI_CTRLR0_SLV_OE ((uint32_t)0x0400) 1446 #define SPI_CTRLR0_SRL ((uint32_t)0x0800) 1447 #define SPI_CTRLR0_CFS ((uint32_t)0xF000) 1448 1449 /***************** Bit definition for SPI_CTRLR1 register *******************/ 1450 #define SPI_CTRLR0_NDF ((uint32_t)0xFFFF) 1451 1452 /***************** Bit definition for SPI_SSIENR register *******************/ 1453 #define SPI_SSIENR_SSIENR ((uint32_t)0x0001) 1454 1455 /***************** Bit definition for SPI_MWCR register *********************/ 1456 #define SPI_MWCR_MWMOD ((uint32_t)0x0001) 1457 #define SPI_MWCR_MDD ((uint32_t)0x0002) 1458 #define SPI_MWCR_MHS ((uint32_t)0x0004) 1459 1460 /***************** Bit definition for SPI_SER register **********************/ 1461 #define SPI_SER_SER ((uint32_t)0x000F) 1462 #define SPI_SER_0 ((uint32_t)0x0001) 1463 #define SPI_SER_1 ((uint32_t)0x0002) 1464 #define SPI_SER_2 ((uint32_t)0x0004) 1465 #define SPI_SER_3 ((uint32_t)0x0008) 1466 1467 /***************** Bit definition for SPI_BAUDR register ********************/ 1468 #define SPI_BAUDR_BAUDR ((uint32_t)0xFFFF) 1469 1470 /***************** Bit definition for SPI_TXFTLR register *******************/ 1471 #define SPI_TXFTLR_TFT ((uint32_t)0x000F) 1472 /***************** Bit definition for SPI_RXFTLR register *******************/ 1473 #define SPI_RXFTLR_RFT ((uint32_t)0x000F) 1474 /***************** Bit definition for SPI_TXFLR register ********************/ 1475 #define SPI_TXFLR_TXTFL ((uint32_t)0x001F) 1476 /***************** Bit definition for SPI_RXFLR register ********************/ 1477 #define SPI_RXFLR_RXTFL ((uint32_t)0x001F) 1478 1479 /***************** Bit definition for SPI_SR register ***********************/ 1480 #define SPI_SR_BUSY ((uint32_t)0x0001) 1481 #define SPI_SR_TFNF ((uint32_t)0x0002) 1482 #define SPI_SR_TFE ((uint32_t)0x0004) 1483 #define SPI_SR_RFNE ((uint32_t)0x0008) 1484 #define SPI_SR_RFF ((uint32_t)0x0010) 1485 #define SPI_SR_TXE ((uint32_t)0x0020) 1486 #define SPI_SR_DCOL ((uint32_t)0x0040) 1487 /***************** Bit definition for SPI_IMR register **********************/ 1488 #define SPI_IMR_TXEIM ((uint32_t)0x0001) 1489 #define SPI_IMR_TXOIM ((uint32_t)0x0002) 1490 #define SPI_IMR_RXUIM ((uint32_t)0x0004) 1491 #define SPI_IMR_RXOIM ((uint32_t)0x0008) 1492 #define SPI_IMR_RXFIM ((uint32_t)0x0010) 1493 #define SPI_IMR_MSTIM ((uint32_t)0x0020) 1494 /***************** Bit definition for SPI_ISR register **********************/ 1495 #define SPI_ISR_TXEIS ((uint32_t)0x0001) 1496 #define SPI_ISR_TXOIS ((uint32_t)0x0002) 1497 #define SPI_ISR_RXUIS ((uint32_t)0x0004) 1498 #define SPI_ISR_RXOIS ((uint32_t)0x0008) 1499 #define SPI_ISR_RXFIS ((uint32_t)0x0010) 1500 #define SPI_ISR_MSTIS ((uint32_t)0x0020) 1501 /***************** Bit definition for SPI_RISR register *********************/ 1502 #define SPI_RISR_TXEIR ((uint32_t)0x0001) 1503 #define SPI_RISR_TXOIR ((uint32_t)0x0002) 1504 #define SPI_RISR_RXUIR ((uint32_t)0x0004) 1505 #define SPI_RISR_RXOIR ((uint32_t)0x0008) 1506 #define SPI_RISR_RXFIR ((uint32_t)0x0010) 1507 #define SPI_RISR_MSTIR ((uint32_t)0x0020) 1508 /***************** Bit definition for SPI_TXOICR register *******************/ 1509 #define SPI_TXOICR_TXOICR ((uint32_t)0x0001) 1510 /***************** Bit definition for SPI_RXOICR register *******************/ 1511 #define SPI_RXOICR_RXOICR ((uint32_t)0x0001) 1512 /***************** Bit definition for SPI_RXUICR register *******************/ 1513 #define SPI_RXUICR_RXUICR ((uint32_t)0x0001) 1514 /***************** Bit definition for SPI_MSTICR register *******************/ 1515 #define SPI_MSTICR_MSTICR ((uint32_t)0x0001) 1516 1517 /***************** Bit definition for SPI_DMACR register ********************/ 1518 #define SPI_DMACR_RDMAE ((uint32_t)0x0001) 1519 #define SPI_DMACR_TDMAE ((uint32_t)0x0002) 1520 /***************** Bit definition for SPI_DMATDLR register ******************/ 1521 #define SPI_DMATDLR_DMATDLR ((uint32_t)0x000F) 1522 /***************** Bit definition for SPI_DMARDLR register ******************/ 1523 #define SPI_DMATDLR_DMARDLR ((uint32_t)0x000F) 1524 /***************** Bit definition for SPI_DMARDLR register ******************/ 1525 #define SPI_DMATDLR_DMARDLR ((uint32_t)0x000F) 1526 1527 /***************** Bit definition for SPI_DR register ***********************/ 1528 #define SPI_DR_DR ((uint32_t)0xFFFF) 1529 /************** Bit definition for SPI_RX_SAMPLE_DLY register ***************/ 1530 #define SPI_RX_SAMPLE_DLY ((uint32_t)0xFFFF) 1531 1532 1533 /******************************************************************************/ 1534 /* */ 1535 /* Inter-integrated Circuit Interface */ 1536 /* */ 1537 /******************************************************************************/ 1538 1539 /******************* Bit definition for IC_CON register *********************/ 1540 #define I2C_IC_CON_MASTER_MODE ((uint32_t)0x0001) 1541 #define I2C_IC_CON_SPEED ((uint32_t)0x0006) 1542 #define I2C_IC_CON_SPEED_0 ((uint32_t)0x0002) 1543 #define I2C_IC_CON_SPEED_1 ((uint32_t)0x0004) 1544 #define I2C_IC_CON_10BITADDR_SLAVE ((uint32_t)0x0008) 1545 #define I2C_IC_CON_10BITADDR_MASTER ((uint32_t)0x0010) 1546 #define I2C_IC_CON_RESTART_EN ((uint32_t)0x0020) 1547 #define I2C_IC_CON_SLAVE_DISABLE ((uint32_t)0x0040) 1548 1549 /******************* Bit definition for IC_TAR register *********************/ 1550 #define I2C_IC_TAR_TAR ((uint32_t)0x03FF) 1551 #define I2C_IC_TAR_GC_OR_START ((uint32_t)0x0400) 1552 #define I2C_IC_TAR_SPECIAL ((uint32_t)0x0800) 1553 #define I2C_IC_TAR_10BITADDR_MASTER ((uint32_t)0x1000) 1554 1555 /******************* Bit definition for IC_SAR register *********************/ 1556 #define I2C_IC_SAR_SAR ((uint32_t)0x03FF) 1557 1558 /******************* Bit definition for IC_HS_MADDR register ****************/ 1559 #define I2C_IC_HS_MADDR_MAR ((uint32_t)0x0007) 1560 #define I2C_IC_HS_MADDR_MAR_0 ((uint32_t)0x0001) 1561 #define I2C_IC_HS_MADDR_MAR_1 ((uint32_t)0x0002) 1562 #define I2C_IC_HS_MADDR_MAR_2 ((uint32_t)0x0004) 1563 1564 /******************* Bit definition for IC_DATA_CMD register ****************/ 1565 #define I2C_IC_DATA_CMD_DAT ((uint32_t)0x00FF) 1566 #define I2C_IC_DATA_CMD_CMD ((uint32_t)0x0100) 1567 #define I2C_IC_DATA_CMD_STOP ((uint32_t)0x0200) 1568 #define I2C_IC_DATA_CMD_RESTART ((uint32_t)0x0400) 1569 1570 /******************* Bit definition for IC_SS_SCL_HCNT register *************/ 1571 #define I2C_IC_SS_SCL_HCNT_HCNT ((uint32_t)0xFFFF) 1572 1573 /******************* Bit definition for IC_SS_SCL_LCNT register *************/ 1574 #define I2C_IC_SS_SCL_LCNT_LCNT ((uint32_t)0xFFFF) 1575 1576 /******************* Bit definition for IC_FS_SCL_HCNT register *************/ 1577 #define I2C_IC_FS_SCL_HCNT_HCNT ((uint32_t)0xFFFF) 1578 1579 /******************* Bit definition for IC_FS_SCL_LCNT register *************/ 1580 #define I2C_IC_FS_SCL_LCNT_LCNT ((uint32_t)0xFFFF) 1581 1582 /******************* Bit definition for IC_HS_SCL_HCNT register *************/ 1583 #define I2C_IC_HS_SCL_HCNT_HCNT ((uint32_t)0xFFFF) 1584 1585 /******************* Bit definition for IC_HS_SCL_LCNT register *************/ 1586 #define I2C_IC_HS_SCL_LCNT_LCNT ((uint32_t)0xFFFF) 1587 1588 /******************* Bit definition for IC_INTR_STAT register ***************/ 1589 #define I2C_IC_INTR_STAT_R_RX_UNDER ((uint32_t)0x0001) 1590 #define I2C_IC_INTR_STAT_R_RX_OVER ((uint32_t)0x0002) 1591 #define I2C_IC_INTR_STAT_R_RX_FULL ((uint32_t)0x0004) 1592 #define I2C_IC_INTR_STAT_R_TX_OVER ((uint32_t)0x0008) 1593 #define I2C_IC_INTR_STAT_R_TX_EMPTY ((uint32_t)0x0010) 1594 #define I2C_IC_INTR_STAT_R_RD_REQ ((uint32_t)0x0020) 1595 #define I2C_IC_INTR_STAT_R_TX_ABRT ((uint32_t)0x0040) 1596 #define I2C_IC_INTR_STAT_R_RX_DONE ((uint32_t)0x0080) 1597 #define I2C_IC_INTR_STAT_R_ACTIVITY ((uint32_t)0x0100) 1598 #define I2C_IC_INTR_STAT_R_STOP_DET ((uint32_t)0x0200) 1599 #define I2C_IC_INTR_STAT_R_START_DET ((uint32_t)0x0400) 1600 #define I2C_IC_INTR_STAT_R_GEN_CALL ((uint32_t)0x0800) 1601 1602 /******************* Bit definition for IC_INTR_MASK register ***************/ 1603 #define I2C_IC_INTR_MASK_M_RX_UNDER ((uint32_t)0x0001) 1604 #define I2C_IC_INTR_MASK_M_RX_OVER ((uint32_t)0x0002) 1605 #define I2C_IC_INTR_MASK_M_RX_FULL ((uint32_t)0x0004) 1606 #define I2C_IC_INTR_MASK_M_TX_OVER ((uint32_t)0x0008) 1607 #define I2C_IC_INTR_MASK_M_TX_EMPTY ((uint32_t)0x0010) 1608 #define I2C_IC_INTR_MASK_M_RD_REQ ((uint32_t)0x0020) 1609 #define I2C_IC_INTR_MASK_M_TX_ABRT ((uint32_t)0x0040) 1610 #define I2C_IC_INTR_MASK_M_RX_DONE ((uint32_t)0x0080) 1611 #define I2C_IC_INTR_MASK_M_ACTIVITY ((uint32_t)0x0100) 1612 #define I2C_IC_INTR_MASK_M_STOP_DET ((uint32_t)0x0200) 1613 #define I2C_IC_INTR_MASK_M_START_DET ((uint32_t)0x0400) 1614 #define I2C_IC_INTR_MASK_M_GEN_CALL ((uint32_t)0x0800) 1615 1616 /******************* Bit definition for IC_RAW_INTR_STAT register ***********/ 1617 #define I2C_IC_RAW_INTR_STAT_RX_UNDER ((uint32_t)0x0001) 1618 #define I2C_IC_RAW_INTR_STAT_RX_OVER ((uint32_t)0x0002) 1619 #define I2C_IC_RAW_INTR_STAT_RX_FULL ((uint32_t)0x0004) 1620 #define I2C_IC_RAW_INTR_STAT_TX_OVER ((uint32_t)0x0008) 1621 #define I2C_IC_RAW_INTR_STAT_TX_EMPTY ((uint32_t)0x0010) 1622 #define I2C_IC_RAW_INTR_STAT_RD_REQ ((uint32_t)0x0020) 1623 #define I2C_IC_RAW_INTR_STAT_TX_ABRT ((uint32_t)0x0040) 1624 #define I2C_IC_RAW_INTR_STAT_RX_DONE ((uint32_t)0x0080) 1625 #define I2C_IC_RAW_INTR_STAT_ACTIVITY ((uint32_t)0x0100) 1626 #define I2C_IC_RAW_INTR_STAT_STOP_DET ((uint32_t)0x0200) 1627 #define I2C_IC_RAW_INTR_STAT_START_DET ((uint32_t)0x0400) 1628 #define I2C_IC_RAW_INTR_STAT_GEN_CALL ((uint32_t)0x0800) 1629 1630 /******************* Bit definition for IC_RX_TL register *******************/ 1631 #define I2C_IC_RX_TL_TL ((uint32_t)0x00FF) 1632 1633 /******************* Bit definition for IC_TX_TL register *******************/ 1634 #define I2C_IC_TX_TL_TL ((uint32_t)0x00FF) 1635 1636 /******************* Bit definition for IC_CLR_INTR register ****************/ 1637 #define I2C_IC_CLR_INTR ((uint32_t)0x0001) 1638 1639 /******************* Bit definition for IC_CLR_RX_UNDER register ************/ 1640 #define I2C_IC_CLR_RX_UNDER ((uint32_t)0x0001) 1641 1642 /******************* Bit definition for IC_CLR_RX_OVER register *************/ 1643 #define I2C_IC_CLR_RX_OVER ((uint32_t)0x0001) 1644 1645 /******************* Bit definition for IC_CLR_TX_OVER register *************/ 1646 #define I2C_IC_CLR_TX_OVER ((uint32_t)0x0001) 1647 1648 /******************* Bit definition for IC_CLR_RD_REQ register **************/ 1649 #define I2C_IC_CLR_RD_REQ ((uint32_t)0x0001) 1650 1651 /******************* Bit definition for IC_CLR_TX_ABRT register *************/ 1652 #define I2C_IC_CLR_TX_ABRT ((uint32_t)0x0001) 1653 1654 /******************* Bit definition for IC_CLR_RX_DONE register *************/ 1655 #define I2C_IC_CLR_RX_DONE ((uint32_t)0x0001) 1656 1657 /******************* Bit definition for IC_CLR_ACTIVITY register ************/ 1658 #define I2C_IC_CLR_ACTIVITY ((uint32_t)0x0001) 1659 1660 /******************* Bit definition for IC_CLR_STOP_DET register ************/ 1661 #define I2C_IC_CLR_STOP_DET ((uint32_t)0x0001) 1662 1663 /******************* Bit definition for IC_CLR_START_DET register ***********/ 1664 #define I2C_IC_CLR_START_DET ((uint32_t)0x0001) 1665 1666 /******************* Bit definition for IC_CLR_GEN_CALL register ************/ 1667 #define I2C_IC_CLR_GEN_CALL ((uint32_t)0x0001) 1668 1669 /******************* Bit definition for IC_ENABLE register *****************/ 1670 #define I2C_IC_ENABLE_ENABLE ((uint32_t)0x0001) 1671 #define I2C_IC_ENABLE_ABORT ((uint32_t)0x0002) 1672 1673 /******************* Bit definition for IC_STATUS register *****************/ 1674 #define I2C_IC_STATUS_ACTIVITY ((uint32_t)0x0001) 1675 #define I2C_IC_STATUS_TFNF ((uint32_t)0x0002) 1676 #define I2C_IC_STATUS_TFE ((uint32_t)0x0004) 1677 #define I2C_IC_STATUS_RFNE ((uint32_t)0x0008) 1678 #define I2C_IC_STATUS_RFF ((uint32_t)0x0010) 1679 #define I2C_IC_STATUS_MST_ACTIVITY ((uint32_t)0x0020) 1680 #define I2C_IC_STATUS_SLV_ACTIVITY ((uint32_t)0x0040) 1681 /******************* Bit definition for IC_TXFLR register ******************/ 1682 #define I2C_IC_TXFLR_TXFLR (8) 1683 1684 /******************* Bit definition for IC_RXFLR register ******************/ 1685 #define I2C_IC_RXFLR_RXFLR (8) 1686 1687 /******************* Bit definition for IC_SDA_HOLD register ***************/ 1688 #define I2C_IC_SDA_HOLD ((uint32_t)0xFFFF) 1689 1690 /******************* Bit definition for IC_TX_ABRT_SOURCE register *********/ 1691 #define I2C_IC_TX_ABRT_SOURCE_7B_ADDR_NOACK ((uint32_t)0x00000001) 1692 #define I2C_IC_TX_ABRT_SOURCE_10ADDR1_NOACK ((uint32_t)0x00000002) 1693 #define I2C_IC_TX_ABRT_SOURCE_10ADDR2_NOACK ((uint32_t)0x00000004) 1694 #define I2C_IC_TX_ABRT_SOURCE_TXDATA_NOACK ((uint32_t)0x00000008) 1695 #define I2C_IC_TX_ABRT_SOURCE_GCALL_NOACK ((uint32_t)0x00000010) 1696 #define I2C_IC_TX_ABRT_SOURCE_GCALL_READ ((uint32_t)0x00000020) 1697 #define I2C_IC_TX_ABRT_SOURCE_HS_ACKDET ((uint32_t)0x00000040) 1698 #define I2C_IC_TX_ABRT_SOURCE_SBYTE_ACKDET ((uint32_t)0x00000080) 1699 #define I2C_IC_TX_ABRT_SOURCE_HS_NORSTRT ((uint32_t)0x00000100) 1700 #define I2C_IC_TX_ABRT_SOURCE_SBYTE_NORSTRT ((uint32_t)0x00000200) 1701 #define I2C_IC_TX_ABRT_SOURCE_10B_RD_NORSTRT ((uint32_t)0x00000400) 1702 #define I2C_IC_TX_ABRT_SOURCE_MASTER_DIS ((uint32_t)0x00000800) 1703 #define I2C_IC_TX_ABRT_SOURCE_LOST ((uint32_t)0x00001000) 1704 #define I2C_IC_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO ((uint32_t)0x00002000) 1705 #define I2C_IC_TX_ABRT_SOURCE_SLV_ARBLOST ((uint32_t)0x00004000) 1706 #define I2C_IC_TX_ABRT_SOURCE_SLVRD_INTX ((uint32_t)0x00008000) 1707 #define I2C_IC_TX_ABRT_SOURCE_USER_ABRT ((uint32_t)0x00010000) 1708 #define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT ((uint32_t)0xFF000000) 1709 1710 /******************* Bit definition for IC_SLV_DATA_NACK_ONLY register *****/ 1711 #define I2C_IC_SLV_DATA_NACK_ONLY ((uint32_t)0x0001) 1712 1713 /******************* Bit definition for IC_DMA_TDLR register ***************/ 1714 #define I2C_IC_DMA_TDLR_TDLR ((uint32_t)0x000F) 1715 1716 /******************* Bit definition for IC_DMA_RDLR register ***************/ 1717 #define I2C_IC_DMA_TDLR_TDLR ((uint32_t)0x000F) 1718 1719 /******************* Bit definition for IC_SDA_SETUP register **************/ 1720 #define I2C_IC_SDA_SETUP ((uint32_t)0x00FF) 1721 1722 /******************* Bit definition for IC_ACK_GENERAL_CALL register *******/ 1723 #define I2C_IC_ACK_GENERAL_CALL ((uint32_t)0x0001) 1724 1725 /******************* Bit definition for IC_ENABLE_STATUS register **********/ 1726 #define I2C_IC_ENABLE_STATUS_IC_EN ((uint32_t)0x0001) 1727 #define I2C_IC_ENABLE_STATUS_SLV_RX_ABORTED ((uint32_t)0x0001) 1728 #define I2C_IC_ENABLE_STATUS_SLV_FIFO_FILLED_AND_FLUSHED ((uint32_t)0x0001) 1729 1730 /******************* Bit definition for IC_FS_SPKLEN register **************/ 1731 #define I2C_IC_FS_SPKLEN_SPKLEN ((uint32_t)0x00FF) 1732 1733 /******************* Bit definition for IC_HS_SPKLEN register **************/ 1734 #define I2C_IC_HS_SPKLEN_SPKLEN ((uint32_t)0x00FF) 1735 1736 /******************* Bit definition for IC_COMP_PARAM_1 register ***********/ 1737 #define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH ((uint32_t)0x0003) 1738 #define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_0 ((uint32_t)0x0001) 1739 #define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_1 ((uint32_t)0x0002) 1740 #define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE ((uint32_t)0x000C) 1741 #define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_0 ((uint32_t)0x0004) 1742 #define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_1 ((uint32_t)0x0008) 1743 #define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES ((uint32_t)0x0010) 1744 #define I2C_IC_COMP_PARAM_1_INTR_IO ((uint32_t)0x0020) 1745 #define I2C_IC_COMP_PARAM_1_HAS_DMA ((uint32_t)0x0040) 1746 #define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS ((uint32_t)0x0080) 1747 #define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH ((uint32_t)0x0000FF00) 1748 #define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH ((uint32_t)0x00FF0000) 1749 1750 /******************* Bit definition for IC_COMP_VERSION register ***********/ 1751 #define I2C_IC_COMP_VERSION ((uint32_t)0xFFFFFFFF) 1752 1753 /******************* Bit definition for IC_COMP_TYPE register **************/ 1754 #define I2C_IC_COMP_TYPE ((uint32_t)0xFFFFFFFF) 1755 1756 1757 /******************************************************************************/ 1758 /* */ 1759 /* Backup Register Unit Block */ 1760 /* */ 1761 /******************************************************************************/ 1762 /******************* Bit definition for BPK_RDY register ********************/ 1763 #define BPK_RDY_POR ((uint32_t)0x0002) 1764 #define BPK_RDY_READY ((uint32_t)0x0001) 1765 1766 /******************* Bit definition for BPK_RR register *********************/ 1767 #define BPK_RR_RESET ((uint32_t)0x0001) 1768 1769 /******************* Bit definition for BPK_LR register *********************/ 1770 #define BPK_LR_LOCK_SELF ((uint32_t)0x0001) 1771 #define BPK_LR_LOCK_RESET ((uint32_t)0x0002) 1772 #define BPK_LR_LOCK_KEYWRITE ((uint32_t)0x0004) 1773 #define BPK_LR_LOCK_KEYREAD ((uint32_t)0x0008) 1774 #define BPK_LR_LOCK_KEYCLEAR ((uint32_t)0x0010) 1775 #define BPK_LR_LOCK_SCRAMBER ((uint32_t)0x0020) 1776 #define BPK_LR_LOCK_ALL ((uint32_t)0x003F) 1777 1778 /******************************************************************************/ 1779 /* */ 1780 /* RTC Unit Block */ 1781 /* */ 1782 /******************************************************************************/ 1783 /******************* Bit definition for RTC_CS register *********************/ 1784 #define RTC_CS_ALARM_IT ((uint32_t)0x01) 1785 #define RTC_CS_LOCK_TIM ((uint32_t)0x02) 1786 #define RTC_CS_ALARM_EN ((uint32_t)0x04) 1787 #define RTC_CS_READY ((uint32_t)0x08) 1788 #define RTC_CS_CLR ((uint32_t)0x10) 1789 1790 /******************************************************************************/ 1791 /* */ 1792 /* Keyboard Control Unit Block */ 1793 /* */ 1794 /******************************************************************************/ 1795 /***************** Bit definition for KCU_CTRL0 register ********************/ 1796 #define KCU_PORT_0 ((uint32_t)0x0001) 1797 #define KCU_PORT_1 ((uint32_t)0x0002) 1798 #define KCU_PORT_2 ((uint32_t)0x0004) 1799 #define KCU_PORT_3 ((uint32_t)0x0008) 1800 #define KCU_PORT_4 ((uint32_t)0x0010) 1801 #define KCU_PORT_5 ((uint32_t)0x0020) 1802 #define KCU_PORT_6 ((uint32_t)0x0040) 1803 #define KCU_PORT_7 ((uint32_t)0x0080) 1804 #define KCU_PORT_8 ((uint32_t)0x0100) 1805 #define KCU_PORT_ALL_Mask ((uint32_t)0x001F) 1806 1807 #define KCU_DEBOUNCETIMELEVEL_0 ((uint32_t)0x0000) 1808 #define KCU_DEBOUNCETIMELEVEL_1 ((uint32_t)0x0001) 1809 #define KCU_DEBOUNCETIMELEVEL_2 ((uint32_t)0x0002) 1810 #define KCU_DEBOUNCETIMELEVEL_3 ((uint32_t)0x0003) 1811 #define KCU_DEBOUNCETIMELEVEL_4 ((uint32_t)0x0004) 1812 #define KCU_DEBOUNCETIMELEVEL_5 ((uint32_t)0x0005) 1813 #define KCU_DEBOUNCETIMELEVEL_6 ((uint32_t)0x0006) 1814 #define KCU_DEBOUNCETIMELEVEL_7 ((uint32_t)0x0007) 1815 #define KCU_DEBOUNCETIMELEVEL_POS (9) 1816 1817 /***************** Bit definition for KCU_CTRL1 register ********************/ 1818 #define KCU_CTRL1_KBD_EN ((uint32_t)0x0001) 1819 #define KCU_CTRL1_PUSH_IT ((uint32_t)0x0002) 1820 #define KCU_CTRL1_RELEASE_IT ((uint32_t)0x0004) 1821 #define KCU_CTRL1_OVERRUN_IT ((uint32_t)0x0008) 1822 #define KCU_CTRL1_KCU_RUNING ((uint32_t)0x80000000) 1823 1824 /***************** Bit definition for KCU_STATUS register *******************/ 1825 #define KCU_STATUS_IT ((uint32_t)0x0001) 1826 #define KCU_STATUS_OVERRUN_IT ((uint32_t)0x0002) 1827 #define KCU_STATUS_PUSH_IT ((uint32_t)0x0004) 1828 #define KCU_STATUS_RELEASE_IT ((uint32_t)0x0008) 1829 #define KCU_STATUS_EVENT_0_PUSH ((uint32_t)0x0010) 1830 #define KCU_STATUS_EVENT_0_NEW ((uint32_t)0x0020) 1831 #define KCU_STATUS_EVENT_1_PUSH ((uint32_t)0x0040) 1832 #define KCU_STATUS_EVENT_1_NEW ((uint32_t)0x0080) 1833 #define KCU_STATUS_EVENT_2_PUSH ((uint32_t)0x0100) 1834 #define KCU_STATUS_EVENT_2_NEW ((uint32_t)0x0200) 1835 #define KCU_STATUS_EVENT_3_PUSH ((uint32_t)0x0400) 1836 #define KCU_STATUS_EVENT_3_NEW ((uint32_t)0x0800) 1837 1838 /***************** Bit definition for KCU_EVENT register ********************/ 1839 #define KCU_EVENT_EVENT_0_INPUT_NUM ((uint32_t)0x0000000F) 1840 #define KCU_EVENT_EVENT_0_OUTPUT_NUM ((uint32_t)0x000000F0) 1841 #define KCU_EVENT_EVENT_1_INPUT_NUM ((uint32_t)0x00000F00) 1842 #define KCU_EVENT_EVENT_1_OUTPUT_NUM ((uint32_t)0x0000F000) 1843 #define KCU_EVENT_EVENT_2_INPUT_NUM ((uint32_t)0x000F0000) 1844 #define KCU_EVENT_EVENT_2_OUTPUT_NUM ((uint32_t)0x00F00000) 1845 #define KCU_EVENT_EVENT_3_INPUT_NUM ((uint32_t)0x0F000000) 1846 #define KCU_EVENT_EVENT_3_OUTPUT_NUM ((uint32_t)0xF0000000) 1847 1848 1849 /******************************************************************************/ 1850 /* */ 1851 /* Timer Control Unit Block */ 1852 /* */ 1853 /******************************************************************************/ 1854 /********** Bit definition for TIMER_CONTROL_REG register *******************/ 1855 #define TIMER_CONTROL_REG_TIMER_ENABLE (0x0001U) 1856 #define TIMER_CONTROL_REG_TIMER_MODE (0x0002U) 1857 #define TIMER_CONTROL_REG_TIMER_INTERRUPT (0x0004U) 1858 #define TIMER_CONTROL_REG_TIMER_PWM (0x0008U) 1859 #define TIMER_CONTROL_REG_PWM_SINGLE_PULSE (0x0010U) 1860 #define TIMER_CONTROL_REG_PWM_RELOAD_SINGLE_PULSE (0x0020U) 1861 1862 /***************** Bit definition for IntStatus register ********************/ 1863 #define TIMER_INT_STATUS_INTERRUPT (0x0001U) 1864 1865 1866 /******************************************************************************/ 1867 /* */ 1868 /* WDT Control Unit Block */ 1869 /* */ 1870 /******************************************************************************/ 1871 /***************** Bit definition for WDT_CR register ***********************/ 1872 #define WDT_CR_WDT_EN ((uint32_t)0x0001) 1873 #define WDT_CR_RMOD ((uint32_t)0x0002) 1874 /***************** Bit definition for WDT_CCVR register *********************/ 1875 #define WDT_CCVR_CCVR ((uint32_t)0xFFFFFFFF) 1876 /***************** Bit definition for WDT_CRR register **********************/ 1877 #define WDT_CRR_CRR ((uint32_t)0x00FF) 1878 /***************** Bit definition for WDT_STAT register *********************/ 1879 #define WDT_STAT_INT ((uint32_t)0x0001) 1880 /***************** Bit definition for WDT_EOI register **********************/ 1881 #define WDT_EOI_EOI ((uint32_t)0x0001) 1882 /***************** Bit definition for WDT_RLD register **********************/ 1883 #define WDT_RLD_RLD ((uint32_t)0xFFFFFFFF) 1884 1885 1886 /******************************************************************************/ 1887 /* */ 1888 /* RNG Control Unit Block */ 1889 /* */ 1890 /******************************************************************************/ 1891 /************ bit definition for TRNG RNG_INDEX REGISTER ************/ 1892 1893 #define RNG_FIFO_INDEX_Mask BIT(31) 1894 /************ bit definition for TRNG RNG_CSR REGISTER ************/ 1895 #define TRNG_RNG_CSR_INTP_EN_Mask ((uint32_t)0x0010) 1896 #define TRNG_RNG_CSR_ATTACK_TRNG0_Mask ((uint32_t)0x0004) 1897 #define TRNG_RNG_CSR_S128_TRNG0_Mask ((uint32_t)0x0001) 1898 1899 /************ bit definition for TRNG RNG_AMA REGISTER ************/ 1900 #define TRNG_RNG_AMA_ANA_OUT_TRNG0_Mask ((uint32_t)0x10000000) 1901 #define TRNG_RNG_AMA_PD_TRNG0_Mask ((uint32_t)0x00001000) 1902 #define TRNG_RNG_AMA_PD_TRNG1_Mask ((uint32_t)0x00002000) 1903 #define TRNG_RNG_AMA_PD_TRNG2_Mask ((uint32_t)0x00004000) 1904 #define TRNG_RNG_AMA_PD_TRNG3_Mask ((uint32_t)0x00008000) 1905 #define TRNG_RNG_AMA_PD_ALL_Mask ((uint32_t)0x0000F000) 1906 1907 1908 /******************************************************************************/ 1909 /* */ 1910 /* DCMI */ 1911 /* */ 1912 /******************************************************************************/ 1913 /************** Bit definition for DCMI SYSCTRL DBG_CR register *************/ 1914 #define DCMI_DBG_CR_INPUTSEL ((uint32_t)0x00002000) 1915 1916 /******************** Bits definition for DCMI_CR register ******************/ 1917 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001) 1918 #define DCMI_CR_CM ((uint32_t)0x00000002) 1919 #define DCMI_CR_CROP ((uint32_t)0x00000004) 1920 #define DCMI_CR_JPEG ((uint32_t)0x00000008) 1921 #define DCMI_CR_ESS ((uint32_t)0x00000010) 1922 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020) 1923 #define DCMI_CR_HSPOL ((uint32_t)0x00000040) 1924 #define DCMI_CR_VSPOL ((uint32_t)0x00000080) 1925 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100) 1926 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200) 1927 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400) 1928 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800) 1929 #define DCMI_CR_CRE ((uint32_t)0x00001000) 1930 #define DCMI_CR_ENABLE ((uint32_t)0x00004000) 1931 #define DCMI_CR_BSM_0 ((uint32_t)0x00010000) 1932 #define DCMI_CR_BSM_1 ((uint32_t)0x00020000) 1933 #define DCMI_CR_OEBS ((uint32_t)0x00040000) 1934 #define DCMI_CR_LSM ((uint32_t)0x00080000) 1935 #define DCMI_CR_OELS ((uint32_t)0x00100000) 1936 #define DCMI_CR_DMAS ((uint32_t)0xE0000000) 1937 1938 /******************** Bits definition for DCMI_SR register ******************/ 1939 #define DCMI_SR_HSYNC ((uint32_t)0x00000001) 1940 #define DCMI_SR_VSYNC ((uint32_t)0x00000002) 1941 #define DCMI_SR_FNE ((uint32_t)0x00000004) 1942 1943 /******************** Bits definition for DCMI_RISR register ****************/ 1944 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001) 1945 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002) 1946 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004) 1947 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008) 1948 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010) 1949 1950 /******************** Bits definition for DCMI_IER register *****************/ 1951 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001) 1952 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002) 1953 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004) 1954 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) 1955 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010) 1956 1957 /******************** Bits definition for DCMI_MISR register ****************/ 1958 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001) 1959 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002) 1960 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004) 1961 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008) 1962 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010) 1963 1964 /******************** Bits definition for DCMI_ICR register *****************/ 1965 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) 1966 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002) 1967 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) 1968 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) 1969 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) 1970 1971 1972 /****************** Bit definition for QUADSPI_FCU_CMD register ******************/ 1973 #define QUADSPI_FCU_CMD_CODE ((uint32_t)0xFF000000U) 1974 #define QUADSPI_FCU_CMD_BUS_MODE ((uint32_t)0x00000300U) 1975 #define QUADSPI_FCU_CMD_CMD_FORMAT ((uint32_t)0x000000F0U) 1976 #define QUADSPI_FCU_CMD_DONE ((uint32_t)0x00000008U) 1977 #define QUADSPI_FCU_CMD_BUSY ((uint32_t)0x00000004U) 1978 #define QUADSPI_FCU_CMD_ACCESS_ACK ((uint32_t)0x00000002U) 1979 #define QUADSPI_FCU_CMD_ACCESS_REQ ((uint32_t)0x00000001U) 1980 1981 #define QUADSPI_ADDRESS_ADR ((uint32_t)0xFFFFFF00U) 1982 #define QUADSPI_ADDRESS_M8 ((uint32_t)0x000000FFU) 1983 1984 #define QUADSPI_BYTE_NUM_WR_BYTE ((uint32_t)0x00001FFFU) 1985 #define QUADSPI_BYTE_NUM_RD_BYTE ((uint32_t)0x1FFF0000U) 1986 1987 #define QUADSPI_WR_FIFO_WR_DATA ((uint32_t)0xFFFFFFFFU) 1988 #define QUADSPI_RD_FIFO_RD_DATA ((uint32_t)0xFFFFFFFFU) 1989 1990 #define QUADSPI_DEVICE_PARA_SAMPLE_DLY ((uint32_t)0x00008000U) 1991 #define QUADSPI_DEVICE_PARA_SAMPLE_PHA ((uint32_t)0x00004000U) 1992 #define QUADSPI_DEVICE_PARA_PROTOCOL ((uint32_t)0x00000300U) 1993 #define QUADSPI_DEVICE_PARA_DUMMY_CYCLE ((uint32_t)0x000000F0U) 1994 #define QUADSPI_DEVICE_PARA_FLASH_READY ((uint32_t)0x00000008U) 1995 #define QUADSPI_DEVICE_PARA_FREQ_SEL ((uint32_t)0x00000003U) 1996 1997 #define QUADSPI_REG_WDATA ((uint32_t)0xFFFFFFFFU) 1998 #define QUADSPI_REG_RDATA ((uint32_t)0xFFFFFFFFU) 1999 2000 #define QUADSPI_INT_MASK_TFDM ((uint32_t)0x00000040U) 2001 #define QUADSPI_INT_MASK_RFDM ((uint32_t)0x00000020U) 2002 #define QUADSPI_INT_MASK_TFOM ((uint32_t)0x00000010U) 2003 #define QUADSPI_INT_MASK_TFUM ((uint32_t)0x00000008U) 2004 #define QUADSPI_INT_MASK_RFOM ((uint32_t)0x00000004U) 2005 #define QUADSPI_INT_MASK_RFUM ((uint32_t)0x00000002U) 2006 #define QUADSPI_INT_MASK_DONE_IM ((uint32_t)0x00000001U) 2007 2008 #define QUADSPI_INT_UMSAK_TFDU ((uint32_t)0x00000040U) 2009 #define QUADSPI_INT_UMSAK_RFDU ((uint32_t)0x00000020U) 2010 #define QUADSPI_INT_UMSAK_TFOU ((uint32_t)0x00000010U) 2011 #define QUADSPI_INT_UMSAK_TFUU ((uint32_t)0x00000008U) 2012 #define QUADSPI_INT_UMSAK_RFOU ((uint32_t)0x00000004U) 2013 #define QUADSPI_INT_UMSAK_RFUU ((uint32_t)0x00000002U) 2014 #define QUADSPI_INT_UMSAK_DONE_IU ((uint32_t)0x00000001U) 2015 2016 #define QUADSPI_INT_MASK_STATUS_TFDM ((uint32_t)0x00000040U) 2017 #define QUADSPI_INT_MASK_STATUS_RFDM ((uint32_t)0x00000020U) 2018 #define QUADSPI_INT_MASK_STATUS_TFOM ((uint32_t)0x00000010U) 2019 #define QUADSPI_INT_MASK_STATUS_TFUM ((uint32_t)0x00000008U) 2020 #define QUADSPI_INT_MASK_STATUS_RFOM ((uint32_t)0x00000004U) 2021 #define QUADSPI_INT_MASK_STATUS_RFUM ((uint32_t)0x00000002U) 2022 #define QUADSPI_INT_MASK_STATUS_DONE_IM ((uint32_t)0x00000001U) 2023 2024 #define QUADSPI_INT_STATUS_TFDS ((uint32_t)0x00000040U) 2025 #define QUADSPI_INT_STATUS_RFDS ((uint32_t)0x00000020U) 2026 #define QUADSPI_INT_STATUS_TFOS ((uint32_t)0x00000010U) 2027 #define QUADSPI_INT_STATUS_TFUS ((uint32_t)0x00000008U) 2028 #define QUADSPI_INT_STATUS_RFOS ((uint32_t)0x00000004U) 2029 #define QUADSPI_INT_STATUS_RFUS ((uint32_t)0x00000002U) 2030 #define QUADSPI_INT_STATUS_DONE_IS ((uint32_t)0x00000001U) 2031 2032 #define QUADSPI_INT_RAWSTATUS_TFDR ((uint32_t)0x00000040U) 2033 #define QUADSPI_INT_RAWSTATUS_RFDR ((uint32_t)0x00000020U) 2034 #define QUADSPI_INT_RAWSTATUS_TFOR ((uint32_t)0x00000010U) 2035 #define QUADSPI_INT_RAWSTATUS_TFUR ((uint32_t)0x00000008U) 2036 #define QUADSPI_INT_RAWSTATUS_RFOR ((uint32_t)0x00000004U) 2037 #define QUADSPI_INT_RAWSTATUS_RFUR ((uint32_t)0x00000002U) 2038 #define QUADSPI_INT_RAWSTATUS_DONE_IR ((uint32_t)0x00000001U) 2039 2040 #define QUADSPI_INT_CLEAR_CTFD ((uint32_t)0x00000040U) 2041 #define QUADSPI_INT_CLEAR_CRFD ((uint32_t)0x00000020U) 2042 #define QUADSPI_INT_CLEAR_CTFO ((uint32_t)0x00000010U) 2043 #define QUADSPI_INT_CLEAR_CTFU ((uint32_t)0x00000008U) 2044 #define QUADSPI_INT_CLEAR_CRFO ((uint32_t)0x00000004U) 2045 #define QUADSPI_INT_CLEAR_CRFU ((uint32_t)0x00000002U) 2046 #define QUADSPI_INT_CLEAR_DONE ((uint32_t)0x00000001U) 2047 2048 #define QUADSPI_CACHE_INTF_CMD_RELDS ((uint32_t)0xFF000000U) 2049 #define QUADSPI_CACHE_INTF_CMD_DS ((uint32_t)0x00FF0000U) 2050 #define QUADSPI_CACHE_INTF_CMD_RD_BUS_MODE ((uint32_t)0x00003000U) 2051 #define QUADSPI_CACHE_INTF_CMD_RD_FORMAT ((uint32_t)0x00000F00U) 2052 #define QUADSPI_CACHE_INTF_CMD_RDCMD ((uint32_t)0x000000FFU) 2053 2054 #define QUADSPI_DMA_CNTL_TX_EN ((uint32_t)0x00000001U) 2055 2056 #define QUADSPI_FIFO_CNTL_TFFH ((uint32_t)0x80000000U) 2057 #define QUADSPI_FIFO_CNTL_TFE ((uint32_t)0x00200000U) 2058 #define QUADSPI_FIFO_CNTL_TFFL ((uint32_t)0x00100000U) 2059 #define QUADSPI_FIFO_CNTL_TFL ((uint32_t)0x000F0000U) 2060 #define QUADSPI_FIFO_CNTL_RFFH ((uint32_t)0x00008000U) 2061 #define QUADSPI_FIFO_CNTL_RFE ((uint32_t)0x00000020U) 2062 #define QUADSPI_FIFO_CNTL_RFFL ((uint32_t)0x00000010U) 2063 #define QUADSPI_FIFO_CNTL_RFL ((uint32_t)0x0000000FU) 2064 2065 2066 #define AIR105_READ_REG8(reg) (*(__IO uint8_t *) reg) 2067 #define AIR105_READ_REG16(reg) (*(__IO uint16_t *) reg) 2068 #define AIR105_READ_REG32(reg) (*(__IO uint32_t *) reg) 2069 #define AIR105_WRITE_REG8(reg, value) (*(__IO uint8_t *) reg = value) 2070 #define AIR105_WRITE_REG16(reg, value) (*(__IO uint16_t *) reg = value) 2071 #define AIR105_WRITE_REG32(reg, value) (*(__IO uint32_t *) reg = value) 2072 #define AIR105_MODIFY_REG8(reg, clear_mask, set_mask) \ 2073 AIR105_WRITE_REG8(reg, (((AIR105_READ_REG8(reg)) & ~clear_mask) | set_mask)) 2074 #define AIR105_MODIFY_REG16(reg, clear_mask, set_mask) \ 2075 AIR105_WRITE_REG16(reg, (((AIR105_READ_REG16(reg)) & ~clear_mask) | set_mask)) 2076 #define AIR105_MODIFY_REG32(reg, clear_mask, set_mask) \ 2077 AIR105_WRITE_REG32(reg, (((AIR105_READ_REG32(reg)) & ~clear_mask) | set_mask)) 2078 2079 2080 #include "air105_conf.h" 2081 2082 2083 #ifdef __cplusplus 2084 } 2085 #endif 2086 2087 #endif /* AIR105_H */ 2088