1 /*
2 * Copyright (c) 2025, sakumisu
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #ifndef __USB_DWC2_PARAM_H__
7 #define __USB_DWC2_PARAM_H__
8
9 /* Maximum number of Endpoints/HostChannels */
10 #define MAX_EPS_CHANNELS 16
11
12 #define HSOTG_REG(x) (x)
13
14 #define dwc2_readl(addr) \
15 (*(volatile uint32_t *)(addr))
16
17 #define GUID_OFFSET HSOTG_REG(0x003C)
18
19 #define GSNPSID_OFFSET HSOTG_REG(0x0040)
20 #define GSNPSID_ID_MASK (0xFFFF0000UL)
21
22 #define GHWCFG1_OFFSET HSOTG_REG(0x0044)
23
24 #define GHWCFG2_OFFSET HSOTG_REG(0x0048)
25 #define GHWCFG2_OTG_ENABLE_IC_USB (0x01UL << 31U)
26 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1FUL << 26U)
27 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT (26U)
28 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x03UL << 24U)
29 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT (24U)
30 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x03UL << 22U)
31 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT (22U)
32 #define GHWCFG2_MULTI_PROC_INT (0x01UL << 20U)
33 #define GHWCFG2_DYNAMIC_FIFO (0x01UL << 19U)
34 #define GHWCFG2_PERIO_EP_SUPPORTED (0x01UL << 18U)
35 #define GHWCFG2_NUM_HOST_CHAN_MASK (0x0FUL << 14U)
36 #define GHWCFG2_NUM_HOST_CHAN_SHIFT (14U)
37 #define GHWCFG2_NUM_DEV_EP_MASK (0x0FUL << 10U)
38 #define GHWCFG2_NUM_DEV_EP_SHIFT (10U)
39 #define GHWCFG2_FS_PHY_TYPE_MASK (0x03UL << 8U)
40 #define GHWCFG2_FS_PHY_TYPE_SHIFT (8U)
41 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED (0x00UL)
42 #define GHWCFG2_FS_PHY_TYPE_DEDICATED (0x01UL)
43 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI (0x02UL)
44 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI (0x03UL)
45 #define GHWCFG2_HS_PHY_TYPE_MASK (0x03UL << 6U)
46 #define GHWCFG2_HS_PHY_TYPE_SHIFT (6U)
47 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED (0x00UL)
48 #define GHWCFG2_HS_PHY_TYPE_UTMI (0x01UL)
49 #define GHWCFG2_HS_PHY_TYPE_ULPI (0x02UL)
50 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI (0x03UL)
51 #define GHWCFG2_POINT2POINT (0x01UL << 5U)
52 #define GHWCFG2_ARCHITECTURE_MASK (0x03UL << 3U)
53 #define GHWCFG2_ARCHITECTURE_SHIFT (3U)
54 #define GHWCFG2_SLAVE_ONLY_ARCH (0x00UL)
55 #define GHWCFG2_EXT_DMA_ARCH (0x01UL)
56 #define GHWCFG2_INT_DMA_ARCH (0x02UL)
57 #define GHWCFG2_OP_MODE_MASK (0x07UL << 0U)
58 #define GHWCFG2_OP_MODE_SHIFT (0U)
59 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE (0x00UL)
60 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE (0x01UL)
61 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE (0x02UL)
62 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE (0x03UL)
63 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE (0x04UL)
64 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST (0x05UL)
65 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST (0x06UL)
66 #define GHWCFG2_OP_MODE_UNDEFINED (0x07UL)
67
68 #define GHWCFG3_OFFSET HSOTG_REG(0x004C)
69 #define GHWCFG3_DFIFO_DEPTH_MASK (0xFFFFUL << 16U)
70 #define GHWCFG3_DFIFO_DEPTH_SHIFT (16U)
71 #define GHWCFG3_OTG_LPM_EN (0x0001UL << 15U)
72 #define GHWCFG3_BC_SUPPORT (0x0001UL << 14U)
73 #define GHWCFG3_OTG_ENABLE_HSIC (0x0001UL << 13U)
74 #define GHWCFG3_ADP_SUPP (0x0001UL << 12U)
75 #define GHWCFG3_SYNCH_RESET_TYPE (0x0001UL << 11U)
76 #define GHWCFG3_OPTIONAL_FEATURES (0x0001UL << 10U)
77 #define GHWCFG3_VENDOR_CTRL_IF (0x0001UL << 9U)
78 #define GHWCFG3_I2C (0x0001UL << 8U)
79 #define GHWCFG3_OTG_FUNC (0x0001UL << 7U)
80 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x0007UL << 4U)
81 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT (4U)
82 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0x000FUL << 0U)
83 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT (0U)
84
85 #define GHWCFG4_OFFSET HSOTG_REG(0x0050)
86 #define GHWCFG4_DESC_DMA_DYN (0x1UL << 31U)
87 #define GHWCFG4_DESC_DMA (0x1UL << 30U)
88 #define GHWCFG4_NUM_IN_EPS_MASK (0xFUL << 26U)
89 #define GHWCFG4_NUM_IN_EPS_SHIFT (26U)
90 #define GHWCFG4_DED_FIFO_EN (0x1UL << 25U)
91 #define GHWCFG4_DED_FIFO_SHIFT (25U)
92 #define GHWCFG4_SESSION_END_FILT_EN (0x1UL << 24U)
93 #define GHWCFG4_B_VALID_FILT_EN (0x1UL << 23U)
94 #define GHWCFG4_A_VALID_FILT_EN (0x1UL << 22U)
95 #define GHWCFG4_VBUS_VALID_FILT_EN (0x1UL << 21U)
96 #define GHWCFG4_IDDIG_FILT_EN (0x1UL << 20U)
97 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xFUL << 16U)
98 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT (16U)
99 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3UL << 14U)
100 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT (14U)
101 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 (0x0UL)
102 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 (0x1UL)
103 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 (0x2UL)
104 #define GHWCFG4_ACG_SUPPORTED (0x1UL << 12U)
105 #define GHWCFG4_IPG_ISOC_SUPPORTED (0x1UL << 11U)
106 #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED (0x1UL << 10U)
107 #define GHWCFG4_XHIBER (0x1UL << 7U)
108 #define GHWCFG4_HIBER (0x1UL << 6U)
109 #define GHWCFG4_MIN_AHB_FREQ (0x1UL << 5U)
110 #define GHWCFG4_POWER_OPTIMIZ (0x1UL << 4U)
111 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xFUL << 0U)
112 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT (0U)
113
114 /**
115 * struct dwc2_hw_params - Autodetected parameters.
116 *
117 * These parameters are the various parameters read from hardware
118 * registers during initialization. They typically contain the best
119 * supported or maximum value that can be configured in the
120 * corresponding dwc2_core_params value.
121 *
122 * The values that are not in dwc2_core_params are documented below.
123 *
124 * @snpsid: Value from SNPSID register
125 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
126 *
127 * @op_mode: Mode of Operation
128 * 0 - HNP- and SRP-Capable OTG (Host & Device)
129 * 1 - SRP-Capable OTG (Host & Device)
130 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
131 * 3 - SRP-Capable Device
132 * 4 - Non-OTG Device
133 * 5 - SRP-Capable Host
134 * 6 - Non-OTG Host
135 * @arch: Architecture
136 * 0 - Slave only
137 * 1 - External DMA
138 * 2 - Internal DMA
139 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
140 * 1 - Allow dynamic FIFO sizing (default, if available)
141 * @host_channels: The number of host channel registers to use
142 * 1 to 16
143 * @hs_phy_type: High-speed PHY interface type
144 * 0 - High-speed interface not supported
145 * 1 - UTMI+
146 * 2 - ULPI
147 * 3 - UTMI+ and ULPI
148 * @fs_phy_type: Full-speed PHY interface type
149 * 0 - Full speed interface not supported
150 * 1 - Dedicated full speed interface
151 * 2 - FS pins shared with UTMI+ pins
152 * 3 - FS pins shared with ULPI pins
153 * @num_dev_ep: Number of device endpoints available
154 * @nperio_tx_q_depth:
155 * Non-Periodic Request Queue Depth
156 * 2, 4 or 8
157 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
158 * Depth
159 * 0 to 30
160 * @host_perio_tx_q_depth:
161 * Host Mode Periodic Request Queue Depth
162 * 2, 4 or 8
163 *
164 * @max_transfer_size: The maximum transfer size supported, in bytes
165 * 2047 to 65,535
166 * Actual maximum value is autodetected and also
167 * the default.
168 * @max_packet_count: The maximum number of packets in a transfer
169 * 15 to 511
170 * Actual maximum value is autodetected and also
171 * the default.
172 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
173 * speed PHY. This parameter is only applicable if phy_type
174 * is FS.
175 * 0 - No (default)
176 * 1 - Yes
177 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
178 * @lpm_mode: For enabling Link Power Management in the controller
179 * 0 - Disable
180 * 1 - Enable
181 *
182 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
183 * are enabled for non-periodic IN endpoints in device
184 * mode.
185 * @num_dev_in_eps: Number of device IN endpoints available
186 * @num_dev_perio_in_ep: Number of device periodic IN endpoints
187 * available
188 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
189 * address DMA mode or descriptor DMA mode for accessing
190 * the data FIFOs. The driver will automatically detect the
191 * value for this if none is specified.
192 * 0 - Address DMA
193 * 1 - Descriptor DMA (default, if available)
194
195 * @power_optimized: Are power optimizations enabled?
196 * @hibernation: Is hibernation enabled?
197 * @utmi_phy_data_width: UTMI+ PHY data width
198 * 0 - 8 bits
199 * 1 - 16 bits
200 * 2 - 8 or 16 bits
201
202 * @acg_enable: For enabling Active Clock Gating in the controller
203 * 0 - Disable
204 * 1 - Enable
205 * @ipg_isoc_en: This feature indicates that the controller supports
206 * the worst-case scenario of Rx followed by Rx
207 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi
208 * specification for any token following ISOC OUT token.
209 * 0 - Don't support
210 * 1 - Support
211 * @service_interval_mode: For enabling service interval based scheduling in the
212 * controller.
213 * 0 - Disable
214 * 1 - Enable
215 */
216 struct dwc2_hw_params {
217 uint32_t snpsid;
218 uint32_t dev_ep_dirs;
219
220 unsigned op_mode : 3;
221 unsigned arch : 2;
222 unsigned enable_dynamic_fifo : 1;
223 unsigned host_channels : 5;
224 unsigned hs_phy_type : 2;
225 unsigned fs_phy_type : 2;
226 unsigned num_dev_ep : 4;
227 unsigned nperio_tx_q_depth : 3;
228 unsigned host_perio_tx_q_depth : 3;
229 unsigned dev_token_q_depth : 5;
230
231 unsigned max_transfer_size : 26;
232 unsigned max_packet_count : 11;
233 unsigned i2c_enable : 1;
234 unsigned total_fifo_size : 16;
235 unsigned lpm_mode : 1;
236
237 unsigned en_multiple_tx_fifo : 1;
238 unsigned num_dev_in_eps : 4;
239 unsigned num_dev_perio_in_ep : 4;
240 unsigned dma_desc_enable : 1;
241 unsigned power_optimized : 1;
242 unsigned hibernation : 1;
243 unsigned utmi_phy_data_width : 2;
244 unsigned acg_enable : 1;
245 unsigned ipg_isoc_en : 1;
246 unsigned service_interval_mode : 1;
247 };
248
249 #define DWC2_PHY_TYPE_PARAM_FS 0
250 #define DWC2_PHY_TYPE_PARAM_UTMI 1
251 #define DWC2_PHY_TYPE_PARAM_ULPI 2
252
253 struct dwc2_user_params {
254 uint8_t phy_type;
255 uint8_t phy_utmi_width;
256
257 bool device_dma_enable;
258 bool device_dma_desc_enable;
259 /* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for
260 * status information) + (2 * number of OUT endpoints) + 1 for Global NAK
261 */
262 uint16_t device_rx_fifo_size;
263 /* IN Endpoints Max packet Size / 4 */
264 uint16_t device_tx_fifo_size[MAX_EPS_CHANNELS];
265
266 bool host_dma_desc_enable;
267 /*
268 * (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
269 * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
270 */
271 uint16_t host_rx_fifo_size;
272 /* largest non-periodic USB packet used / 4 */
273 uint16_t host_nperio_tx_fifo_size;
274 /* largest periodic USB packet used / 4 */
275 uint16_t host_perio_tx_fifo_size;
276
277 uint32_t device_gccfg;
278 uint32_t host_gccfg;
279
280 bool b_session_valid_override;
281 uint32_t total_fifo_size;
282 };
283
284 struct usb_dwc2_user_fifo_config {
285 /* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for
286 * status information) + (2 * number of OUT endpoints) + 1 for Global NAK
287 */
288 uint16_t device_rx_fifo_size;
289 /* IN Endpoints Max packet Size / 4 */
290 uint16_t device_tx_fifo_size[MAX_EPS_CHANNELS];
291 };
292
dwc2_get_hwparams(uint32_t reg_base,struct dwc2_hw_params * hw)293 static inline void dwc2_get_hwparams(uint32_t reg_base, struct dwc2_hw_params *hw)
294 {
295 unsigned int width;
296 uint32_t snpsid, hwcfg1, hwcfg2, hwcfg3, hwcfg4;
297
298 snpsid = dwc2_readl(reg_base + GSNPSID_OFFSET);
299
300 hwcfg1 = dwc2_readl(reg_base + GHWCFG1_OFFSET);
301 hwcfg2 = dwc2_readl(reg_base + GHWCFG2_OFFSET);
302 hwcfg3 = dwc2_readl(reg_base + GHWCFG3_OFFSET);
303 hwcfg4 = dwc2_readl(reg_base + GHWCFG4_OFFSET);
304
305 /* snpsid */
306 hw->snpsid = snpsid;
307
308 /* hwcfg1 */
309 hw->dev_ep_dirs = hwcfg1;
310
311 /* hwcfg2 */
312 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
313 GHWCFG2_OP_MODE_SHIFT;
314 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
315 GHWCFG2_ARCHITECTURE_SHIFT;
316 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
317 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
318 GHWCFG2_NUM_HOST_CHAN_SHIFT);
319 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
320 GHWCFG2_HS_PHY_TYPE_SHIFT;
321 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
322 GHWCFG2_FS_PHY_TYPE_SHIFT;
323 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
324 GHWCFG2_NUM_DEV_EP_SHIFT;
325 hw->nperio_tx_q_depth =
326 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
327 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
328 hw->host_perio_tx_q_depth =
329 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
330 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
331 hw->dev_token_q_depth =
332 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
333 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
334
335 /* hwcfg3 */
336 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
337 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
338 hw->max_transfer_size = (1 << (width + 11)) - 1;
339 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
340 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
341 hw->max_packet_count = (1 << (width + 4)) - 1;
342 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
343 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
344 GHWCFG3_DFIFO_DEPTH_SHIFT;
345 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
346
347 /* hwcfg4 */
348 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
349 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
350 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
351 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
352 GHWCFG4_NUM_IN_EPS_SHIFT;
353 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
354 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
355 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
356 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
357 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
358 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
359 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
360 hw->service_interval_mode = !!(hwcfg4 &
361 GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
362 }
363
364 void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params);
365 void dwc2_get_user_fifo_config(uint32_t reg_base, struct usb_dwc2_user_fifo_config *config);
366
367 #endif