1 /*********************************************************************************************************//**
2 * @file ht32f5xxxx_mctm.c
3 * @version $Rev:: 6421 $
4 * @date $Date:: 2022-11-03 #$
5 * @brief This file provides all the MCTM firmware functions.
6 *************************************************************************************************************
7 * @attention
8 *
9 * Firmware Disclaimer Information
10 *
11 * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the
12 * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the
13 * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and
14 * other intellectual property laws.
15 *
16 * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the
17 * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties
18 * other than HOLTEK and the customer.
19 *
20 * 3. The program technical documentation, including the code, is provided "as is" and for customer reference
21 * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including
22 * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including
23 * the warranties of merchantability, satisfactory quality and fitness for a particular purpose.
24 *
25 * <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2>
26 ************************************************************************************************************/
27
28 /* Includes ------------------------------------------------------------------------------------------------*/
29 #include "ht32f5xxxx_mctm.h"
30
31 /** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver
32 * @{
33 */
34
35 /** @defgroup MCTM MCTM
36 * @brief MCTM driver modules
37 * @{
38 */
39
40
41 /* Private constants ---------------------------------------------------------------------------------------*/
42 /** @defgroup MCTM_Private_Define MCTM private definitions
43 * @{
44 */
45 #define CTR_COMPRE 0x00000100ul
46 #define CTR_COMUS 0x00000200ul
47
48 #define CHBRKCTR_CHMOE 0x00000010ul
49 /**
50 * @}
51 */
52
53
54 /* Global functions ----------------------------------------------------------------------------------------*/
55 /** @defgroup MCTM_Exported_Functions MCTM exported functions
56 * @{
57 */
58
59 /*********************************************************************************************************//**
60 * @brief Configure polarity of the MCTMx channel N.
61 * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral.
62 * @param Channel: Specify the MCTM channel.
63 * This parameter can be one of the following values:
64 * @arg MCTM_CH_0 : MCTM channel 0
65 * @arg MCTM_CH_1 : MCTM channel 1
66 * @arg MCTM_CH_2 : MCTM channel 2
67 * @arg MCTM_CH_3 : MCTM channel 3
68 * @param Pol: Specify the polarity of channel N.
69 * This parameter can be one of the following values:
70 * @arg MCTM_CHP_NONINVERTED : active high
71 * @arg MCTM_CHP_INVERTED : active low
72 * @retval None
73 ************************************************************************************************************/
MCTM_ChNPolarityConfig(HT_TM_TypeDef * MCTMx,TM_CH_Enum Channel,TM_CHP_Enum Pol)74 void MCTM_ChNPolarityConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHP_Enum Pol)
75 {
76 u32 wChpolr;
77
78 /* Check the parameters */
79 Assert_Param(IS_MCTM(MCTMx));
80 Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel));
81 Assert_Param(IS_TM_CHP(Pol));
82
83 /* Set or reset the CHxN polarity */
84 wChpolr = MCTMx->CHPOLR & (~(u32)(0x2 << (Channel << 1)));
85 MCTMx->CHPOLR = wChpolr | ((Pol << 1) << (Channel << 1));
86 }
87
88 /*********************************************************************************************************//**
89 * @brief Enable or Disable the MCTMx channel N.
90 * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripheral.
91 * @param Channel: Specify the MCTM channel.
92 * This parameter can be one of the following values:
93 * @arg MCTM_CH_0 : MCTM channel 0
94 * @arg MCTM_CH_1 : MCTM channel 1
95 * @arg MCTM_CH_2 : MCTM channel 2
96 * @arg MCTM_CH_3 : MCTM channel 3
97 * @param Control: This parameter can be TM_CHCTL_ENABLE or TM_CHCTL_DISABLE.
98 * @retval None
99 ************************************************************************************************************/
MCTM_ChannelNConfig(HT_TM_TypeDef * MCTMx,TM_CH_Enum Channel,TM_CHCTL_Enum Control)100 void MCTM_ChannelNConfig(HT_TM_TypeDef* MCTMx, TM_CH_Enum Channel, TM_CHCTL_Enum Control)
101 {
102 /* Check the parameters */
103 Assert_Param(IS_MCTM(MCTMx));
104 Assert_Param(IS_MCTM_COMPLEMENTARY_CH(Channel));
105 Assert_Param(IS_TM_CHCTL(Control));
106
107 /* Reset the CHxNE Bit */
108 MCTMx->CHCTR &= ~(u32)(0x2 << (Channel << 1));
109
110 /* Set or reset the CHxNE Bit */
111 MCTMx->CHCTR |= (u32)(Control << 1) << (Channel << 1);
112 }
113
114 /*********************************************************************************************************//**
115 * @brief Enable or Disable the channels main output of the MCTMx.
116 * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals.
117 * @param NewState: This parameter can be ENABLE or DISABLE.
118 * @retval None
119 ************************************************************************************************************/
MCTM_CHMOECmd(HT_TM_TypeDef * MCTMx,ControlStatus NewState)120 void MCTM_CHMOECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState)
121 {
122 /* Check the parameters */
123 Assert_Param(IS_MCTM(MCTMx));
124 Assert_Param(IS_CONTROL_STATUS(NewState));
125
126 if (NewState != DISABLE)
127 {
128 /* Enable the MCTM Main Output */
129 MCTMx->CHBRKCTR |= CHBRKCTR_CHMOE;
130 }
131 else
132 {
133 /* Disable the MCTM Main Output */
134 MCTMx->CHBRKCTR &= ~CHBRKCTR_CHMOE;
135 }
136 }
137
138 /*********************************************************************************************************//**
139 * @brief Configure the break feature, dead time, Lock level, the OSSI, the OSSR State
140 * and the CHAOE(automatic output enable).
141 * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals.
142 * @param CHBRKCTRInit: Point to a MCTM_CHBRKCTRInitTypeDef structure.
143 * @retval None
144 ************************************************************************************************************/
MCTM_CHBRKCTRConfig(HT_TM_TypeDef * MCTMx,MCTM_CHBRKCTRInitTypeDef * CHBRKCTRInit)145 void MCTM_CHBRKCTRConfig(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRInitTypeDef *CHBRKCTRInit)
146 {
147 u32 wTmpReg;
148
149 /* Check the parameters */
150 Assert_Param(IS_MCTM(MCTMx));
151 Assert_Param(IS_MCTM_OSSR_STATE(CHBRKCTRInit->OSSRState));
152 Assert_Param(IS_MCTM_OSSI_STATE(CHBRKCTRInit->OSSIState));
153 Assert_Param(IS_MCTM_LOCK_LEVEL(CHBRKCTRInit->LockLevel));
154 Assert_Param(IS_MCTM_BREAK_STATE(CHBRKCTRInit->Break0));
155 Assert_Param(IS_MCTM_BREAK_POLARITY(CHBRKCTRInit->Break0Polarity));
156 Assert_Param(IS_MCTM_CHAOE_STATE(CHBRKCTRInit->AutomaticOutput));
157 Assert_Param(IS_TM_FILTER(CHBRKCTRInit->BreakFilter));
158
159 wTmpReg = MCTMx->CHBRKCTR & 0x00000010; // Keep CHMOE
160 wTmpReg |= (u32)CHBRKCTRInit->BreakFilter << 8;
161 wTmpReg |= (u32)CHBRKCTRInit->DeadTime << 24;
162 wTmpReg |= CHBRKCTRInit->LockLevel | CHBRKCTRInit->OSSRState | CHBRKCTRInit->OSSIState;
163 wTmpReg |= CHBRKCTRInit->Break0 | CHBRKCTRInit->Break0Polarity | CHBRKCTRInit->AutomaticOutput;
164
165 MCTMx->CHBRKCTR = wTmpReg;
166 }
167
168 /*********************************************************************************************************//**
169 * @brief Configure the break feature, dead time, Lock level, the OSSI, the OSSR State
170 * and the CHAOE(automatic output enable).
171 * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals.
172 * @param CHBRKCTRInit: Point to a MCTM_CHBRKCTRTypeDef structure.
173 * @retval None
174 ************************************************************************************************************/
MCTM_CHBRKCTRConfig2(HT_TM_TypeDef * MCTMx,MCTM_CHBRKCTRTypeDef * CHBRKCTRInit)175 void MCTM_CHBRKCTRConfig2(HT_TM_TypeDef* MCTMx, MCTM_CHBRKCTRTypeDef *CHBRKCTRInit)
176 {
177 u32 wTmpReg;
178
179 wTmpReg = MCTMx->CHBRKCTR & 0x00000010; // Keep CHMOE
180
181 wTmpReg |= CHBRKCTRInit->Reg;
182
183 MCTMx->CHBRKCTR = wTmpReg;
184 }
185
186 /*********************************************************************************************************//**
187 * @brief Fill each CHBRKCTRInitStruct member with its default value.
188 * @param CHBRKCTRInitStruct: Point to a MCTM_CHBRKCTRInitTypeDef structure.
189 * @retval None
190 ************************************************************************************************************/
MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef * CHBRKCTRInitStruct)191 void MCTM_CHBRKCTRStructInit(MCTM_CHBRKCTRInitTypeDef* CHBRKCTRInitStruct)
192 {
193 /* Set the default configuration */
194 CHBRKCTRInitStruct->OSSRState = MCTM_OSSR_STATE_DISABLE;
195 CHBRKCTRInitStruct->OSSIState = MCTM_OSSI_STATE_DISABLE;
196 CHBRKCTRInitStruct->LockLevel = MCTM_LOCK_LEVEL_OFF;
197 CHBRKCTRInitStruct->DeadTime = 0x00;
198 CHBRKCTRInitStruct->Break0 = MCTM_BREAK_DISABLE;
199 CHBRKCTRInitStruct->Break0Polarity = MCTM_BREAK_POLARITY_LOW;
200 CHBRKCTRInitStruct->BreakFilter = 0;
201 CHBRKCTRInitStruct->AutomaticOutput = MCTM_CHAOE_DISABLE;
202 }
203
204 /*********************************************************************************************************//**
205 * @brief Enable or Disable MCTMx COMPRE function.
206 * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals.
207 * @param NewState: This parameter can be ENABLE or DISABLE.
208 * @retval None
209 ************************************************************************************************************/
MCTM_COMPRECmd(HT_TM_TypeDef * MCTMx,ControlStatus NewState)210 void MCTM_COMPRECmd(HT_TM_TypeDef* MCTMx, ControlStatus NewState)
211 {
212 /* Check the parameters */
213 Assert_Param(IS_MCTM(MCTMx));
214 Assert_Param(IS_CONTROL_STATUS(NewState));
215
216 if (NewState != DISABLE)
217 {
218 /* Enable the MCTM COMPRE */
219 MCTMx->CTR |= CTR_COMPRE;
220 }
221 else
222 {
223 /* Disable the MCTM COMPRE */
224 MCTMx->CTR &= ~CTR_COMPRE;
225 }
226 }
227
228 /*********************************************************************************************************//**
229 * @brief Configure the MCTMx COMUS function.
230 * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals.
231 * @param Sel: Specify the COMUS value.
232 * This parameter can be one of the following values:
233 * @arg MCTM_COMUS_STIOFF : MCTM capture/compare control bits are updated by setting the UEV2G bit only
234 * @arg MCTM_COMUS_STION : MCTM capture/compare control bits are updated by both setting the UEV2G bit
235 * or when a rising edge occurs on STI
236 * @retval None
237 ************************************************************************************************************/
MCTM_COMUSConfig(HT_TM_TypeDef * MCTMx,MCTM_COMUS_Enum Sel)238 void MCTM_COMUSConfig(HT_TM_TypeDef* MCTMx, MCTM_COMUS_Enum Sel)
239 {
240 /* Check the parameters */
241 Assert_Param(IS_MCTM(MCTMx));
242 Assert_Param(IS_MCTM_COMUS(Sel));
243
244 if (Sel != MCTM_COMUS_STIOFF)
245 {
246 /* Set the MCTM COMUS bit */
247 MCTMx->CTR |= CTR_COMUS;
248 }
249 else
250 {
251 /* Clear the MCTM COMUS bit */
252 MCTMx->CTR &= ~CTR_COMUS;
253 }
254 }
255
256 #if (LIBCFG_MCTM_UEV1DIS)
257 /*********************************************************************************************************//**
258 * @brief Enable or Disable Overflow/Underflow update event(does not contain interrupt) of the MCTMx.
259 * @param MCTMx: where MCTMx is the selected MCTM from the MCTM peripherals.
260 * @param MCTM_UEV1x: MCTM_UEV1UD or MCTM_UEV1OD. Overflow/underflow request disable control.
261 * @param NewState: This parameter can be SET or RESET.
262 * @retval None
263 ************************************************************************************************************/
MCTM_UpdateEventDisable(HT_TM_TypeDef * MCTMx,MCTM_UEV1DIS_Enum MCTM_UEV1x,FlagStatus NewState)264 void MCTM_UpdateEventDisable(HT_TM_TypeDef* MCTMx, MCTM_UEV1DIS_Enum MCTM_UEV1x, FlagStatus NewState)
265 {
266 /* Check the parameters */
267 Assert_Param(IS_MCTM(MCTMx));
268 Assert_Param(IS_CONTROL_STATUS(NewState));
269
270 if (NewState != RESET)
271 {
272 /* Set the update disable bit */
273 MCTMx->CNTCFR |= MCTM_UEV1x;
274 }
275 else
276 {
277 /* Reset the update disable bit */
278 MCTMx->CNTCFR &= ~MCTM_UEV1x;
279 }
280 }
281 #endif
282 /**
283 * @}
284 */
285
286
287 /**
288 * @}
289 */
290
291 /**
292 * @}
293 */
294