1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_MIPI_CSI_PHY_H 10 #define HPM_MIPI_CSI_PHY_H 11 12 typedef struct { 13 __RW uint32_t SOFT_RST; /* 0x0: soft reset control */ 14 __RW uint32_t PHY_RCAL; /* 0x4: dphy resistor calibration */ 15 __RW uint32_t ULP_RX_EN; /* 0x8: enable lprx and ulprx */ 16 __R uint32_t VOFFCAL_OUT; /* 0xC: hs-rx dc-offset auto-calibration results */ 17 __RW uint32_t CSI_CTL01; /* 0x10: dphy hardcore control */ 18 __RW uint32_t CSI_CTL23; /* 0x14: dphy hardcore control */ 19 __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ 20 __RW uint32_t CSI_VINIT; /* 0x1C: ulp lp-rx input threshold voltage trimming for data lane */ 21 __RW uint32_t CLANE_PARA; /* 0x20: clock lane parameter */ 22 __RW uint32_t T_HS_TERMEN; /* 0x24: t-termen of all datalane */ 23 __RW uint32_t T_HS_SETTLE; /* 0x28: t-settle of all data lanes */ 24 __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ 25 __RW uint32_t T_CLANE_INIT; /* 0x30: t-init of clock lane */ 26 __RW uint32_t T_LANE_INIT0; /* 0x34: t-init of data lane0 */ 27 __RW uint32_t T_LANE_INIT1; /* 0x38: t-init of data lane1 */ 28 __R uint8_t RESERVED2[8]; /* 0x3C - 0x43: Reserved */ 29 __RW uint32_t TLPX_CTRL; /* 0x44: the time of tlpx_ctrl of all lane */ 30 __RW uint32_t NE_SWAP; /* 0x48: lane swap and dp/dn swap select */ 31 __RW uint32_t MISC_INFO; /* 0x4C: misc info of dphyrx_pcs control */ 32 __R uint8_t RESERVED3[32]; /* 0x50 - 0x6F: Reserved */ 33 __RW uint32_t BIST_TEST0; /* 0x70: bist test control */ 34 __RW uint32_t BIST_TEST1; /* 0x74: bist test control */ 35 __RW uint32_t BIST_TEST2; /* 0x78: bist test control */ 36 __R uint32_t BIST_TEST3; /* 0x7C: bist test control */ 37 __R uint8_t RESERVED4[32]; /* 0x80 - 0x9F: Reserved */ 38 __RW uint32_t BURN_IN_TEST0; /* 0xA0: burn-in test control */ 39 __RW uint32_t BURN_IN_TEST1; /* 0xA4: burn-in test control */ 40 __R uint32_t BURN_IN_TEST2; /* 0xA8: bist test control */ 41 __R uint8_t RESERVED5[4]; /* 0xAC - 0xAF: Reserved */ 42 __R uint32_t BURN_IN_TEST4; /* 0xB0: bist test control */ 43 __R uint32_t BURN_IN_TEST5; /* 0xB4: burn-in test control */ 44 __R uint32_t BURN_IN_TEST6; /* 0xB8: burn-in test control */ 45 __R uint8_t RESERVED6[8]; /* 0xBC - 0xC3: Reserved */ 46 __R uint32_t BURN_IN_TEST9; /* 0xC4: burn-in test control */ 47 __R uint8_t RESERVED7[8]; /* 0xC8 - 0xCF: Reserved */ 48 __RW uint32_t DEBUG_INFO; /* 0xD0: debug data control */ 49 __RW uint32_t DEBUG_CFG_REG0; /* 0xD4: the hardcore interface control in debug mode */ 50 __RW uint32_t DEBUG_CFG_REG1; /* 0xD8: the hardcore interface control in debug mode */ 51 __R uint8_t RESERVED8[3126]; /* 0xDC - 0xD11: Reserved */ 52 __RW uint32_t DEBUG_CFG_REG2; /* 0xD12: the hardcore interface control in debug mode */ 53 __RW uint32_t DEBUG_CFG_REG3; /* 0xD16: the hardcore interface control in debug mode */ 54 __R uint8_t RESERVED9[6]; /* 0xD1A - 0xD1F: Reserved */ 55 __RW uint32_t DEBUG_CFG_REG4; /* 0xD20: the hardcore interface control in debug mode */ 56 __RW uint32_t DEBUG_CFG_REG5; /* 0xD24: the hardcore interface control in debug mode */ 57 } MIPI_CSI_PHY_Type; 58 59 60 /* Bitfield definition for register: SOFT_RST */ 61 /* 62 * HS_CLK_SOFT_RST (RW) 63 * 64 * the soft reset of clk_hs domain 65 */ 66 #define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK (0x2U) 67 #define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT (1U) 68 #define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT) & MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK) 69 #define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK) >> MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT) 70 71 /* 72 * CFG_CLK_SOFT_RST (RW) 73 * 74 * the soft reset of clk_cfg domain 75 */ 76 #define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK (0x1U) 77 #define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT (0U) 78 #define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT) & MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK) 79 #define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK) >> MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT) 80 81 /* Bitfield definition for register: PHY_RCAL */ 82 /* 83 * RCAL_DONE (RO) 84 * 85 * hs-rx terminal trimming done indicator signal 86 */ 87 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_MASK (0x20000UL) 88 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_SHIFT (17U) 89 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_SHIFT) 90 91 /* 92 * RCAL_OUT (RO) 93 * 94 * hs-rx terminal trimming results 95 */ 96 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_MASK (0x1E000UL) 97 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_SHIFT (13U) 98 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_SHIFT) 99 100 /* 101 * RCAL_CTL (RW) 102 * 103 * rcal function control 104 */ 105 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK (0x1FE0U) 106 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT (5U) 107 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK) 108 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT) 109 110 /* 111 * RCAL_TRIM (RW) 112 * 113 * default value of HS-RX terminal configure 114 */ 115 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK (0x1EU) 116 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT (1U) 117 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK) 118 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT) 119 120 /* 121 * RCAL_EN (RW) 122 * 123 * enable hs-rx terminal trimming 124 */ 125 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK (0x1U) 126 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT (0U) 127 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK) 128 #define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT) 129 130 /* Bitfield definition for register: ULP_RX_EN */ 131 /* 132 * CSI_1_ULPRX_EN (RW) 133 * 134 * data lane1 ulp-rx receiver enable control 135 */ 136 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK (0x80U) 137 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT (7U) 138 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK) 139 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT) 140 141 /* 142 * CSI_0_ULPRX_EN (RW) 143 * 144 * data lane0 ulp-rx receiver enable control 145 */ 146 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK (0x40U) 147 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT (6U) 148 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK) 149 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT) 150 151 /* 152 * CSI_CLK_ULPRX_EN (RW) 153 * 154 * clock lane ulp-rx receiver enable control 155 */ 156 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK (0x20U) 157 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT (5U) 158 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK) 159 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT) 160 161 /* 162 * CSI_1_LPRX_EN (RW) 163 * 164 * data lane1 lp-rx receiver enable control 165 */ 166 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK (0x2U) 167 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT (1U) 168 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK) 169 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT) 170 171 /* 172 * CSI_CLK_LPRX_EN (RW) 173 * 174 * clock lane lp=rx receiver enable control 175 */ 176 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK (0x1U) 177 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT (0U) 178 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK) 179 #define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT) 180 181 /* Bitfield definition for register: VOFFCAL_OUT */ 182 /* 183 * CSI_CLK_VOFFCAL_DONE (RO) 184 * 185 * clock lane hs-rx dc-offset auto-calibration done 186 */ 187 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_MASK (0x20000000UL) 188 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_SHIFT (29U) 189 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_SHIFT) 190 191 /* 192 * CSI_CLK_VOFFCAL_OUT (RO) 193 * 194 * clock lane hs-rx dc-offset auto-calibration results 195 */ 196 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_MASK (0x1F000000UL) 197 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_SHIFT (24U) 198 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_SHIFT) 199 200 /* 201 * CSI_0_VOFFCAL_DONE (RO) 202 * 203 * data lane0 hs-rx dc-offset auto-calibration done 204 */ 205 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_MASK (0x800000UL) 206 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_SHIFT (23U) 207 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_SHIFT) 208 209 /* 210 * CSI_O_VOFFCAL_OUT (RO) 211 * 212 * data lane0 hs-rx dc-offset auto-calibration result 213 */ 214 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_MASK (0x7C0000UL) 215 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_SHIFT (18U) 216 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_SHIFT) 217 218 /* 219 * CSI_1_VOFFCAL_DONE (RO) 220 * 221 * data lane1 hs-rx dc-offset auto-calibration done 222 */ 223 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_MASK (0x20000UL) 224 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_SHIFT (17U) 225 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_SHIFT) 226 227 /* 228 * CSI_1_VOFFCAL_OUT (RO) 229 * 230 * data lane1 hs-rx dc-offset auto-calibration result 231 */ 232 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_MASK (0x1F000UL) 233 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_SHIFT (12U) 234 #define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_SHIFT) 235 236 /* Bitfield definition for register: CSI_CTL01 */ 237 /* 238 * CSI_CTL1_7 (RW) 239 * 240 * clock lane hs-rx dc-offset auto-calibration enable 241 */ 242 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK (0x20000000UL) 243 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT (29U) 244 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK) 245 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT) 246 247 /* 248 * CSI_CTL1_6 (RW) 249 * 250 * clock lane hs-rx dc-offset trimming control 251 */ 252 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK (0x1F000000UL) 253 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT (24U) 254 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK) 255 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT) 256 257 /* 258 * CSI_CTL1_5 (RW) 259 * 260 * ulprx_vref_trim 261 */ 262 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK (0x600000UL) 263 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT (21U) 264 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK) 265 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT) 266 267 /* 268 * CSI_CTL1_4 (RW) 269 * 270 * bypass hs_rx_voffcal_en 271 */ 272 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK (0x100000UL) 273 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT (20U) 274 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK) 275 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT) 276 277 /* 278 * CSI_CTL1_3 (RW) 279 * 280 * hs_rx_voffcal_trim_polar 281 */ 282 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK (0x80000UL) 283 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT (19U) 284 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK) 285 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT) 286 287 /* 288 * CSI_CTL1_2 (RW) 289 * 290 * ulprx_lpen 291 */ 292 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK (0x40000UL) 293 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT (18U) 294 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK) 295 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT) 296 297 /* 298 * CSI_CTL1_1 (RW) 299 * 300 * force data lane-n and clock lane lp/ulprx to be normal operation 301 */ 302 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK (0x20000UL) 303 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT (17U) 304 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK) 305 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT) 306 307 /* 308 * CSI_CTL1_0 (RW) 309 * 310 * force data lane-n and clock lane hs-rx to be normal operation 311 */ 312 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK (0x10000UL) 313 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT (16U) 314 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK) 315 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT) 316 317 /* 318 * CSI_CTL0_7 (RW) 319 * 320 * clock lane hs-rx dc-offset auto-calibration enable 321 */ 322 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK (0x2000U) 323 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT (13U) 324 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK) 325 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT) 326 327 /* 328 * CSI_CTL0_6 (RW) 329 * 330 * clock lane hs-rx dc-offset trimming control 331 */ 332 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK (0x1F00U) 333 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT (8U) 334 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK) 335 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT) 336 337 /* 338 * CSI_CTL0_5 (RW) 339 * 340 * ulprx_vref_trim 341 */ 342 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK (0x60U) 343 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT (5U) 344 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK) 345 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT) 346 347 /* 348 * CSI_CTL0_4 (RW) 349 * 350 * bypass hs_rx_voffcal_en 351 */ 352 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK (0x10U) 353 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT (4U) 354 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK) 355 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT) 356 357 /* 358 * CSI_CTL0_3 (RW) 359 * 360 * hs_rx_voffcal_trim_polar 361 */ 362 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK (0x8U) 363 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT (3U) 364 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK) 365 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT) 366 367 /* 368 * CSI_CTL0_2 (RW) 369 * 370 * ulprx_lpen 371 */ 372 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK (0x4U) 373 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT (2U) 374 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK) 375 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT) 376 377 /* 378 * CSI_CTL0_1 (RW) 379 * 380 * force data lane-n and clock lane lp/ulprx to be normal operation 381 */ 382 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK (0x2U) 383 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT (1U) 384 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK) 385 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT) 386 387 /* 388 * CSI_CTL0_0 (RW) 389 * 390 * force data lane-n and clock lane hs-rx to be normal operation 391 */ 392 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK (0x1U) 393 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT (0U) 394 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK) 395 #define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT) 396 397 /* Bitfield definition for register: CSI_CTL23 */ 398 /* 399 * CSI_CTL3_3 (RW) 400 * 401 * data lane-1 skew trimming enable 402 */ 403 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK (0x10000000UL) 404 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT (28U) 405 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK) 406 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT) 407 408 /* 409 * CSI_CTL3_2 (RW) 410 * 411 * data lane-1 hs-rx skew adjust with binary code 412 */ 413 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK (0xF000000UL) 414 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT (24U) 415 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK) 416 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT) 417 418 /* 419 * CSI_CTL3_1 (RW) 420 * 421 * data lane-0 skew trimming enable 422 */ 423 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK (0x100000UL) 424 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT (20U) 425 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK) 426 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT) 427 428 /* 429 * CSI_CTL3_0 (RW) 430 * 431 * data lane-0 hs-rx skew adjust with binary code 432 */ 433 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK (0xF0000UL) 434 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT (16U) 435 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK) 436 #define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT) 437 438 /* Bitfield definition for register: CSI_VINIT */ 439 /* 440 * CSI_LPRX_VREF_TRIM (RW) 441 * 442 * pt ft indicator in csi clk data lane 443 */ 444 #define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK (0xF00000UL) 445 #define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT (20U) 446 #define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT) & MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK) 447 #define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT) 448 449 /* 450 * CSI_CLK_LPRX_VINT (RO) 451 * 452 * pt ft indicator in csi clk lane 453 */ 454 #define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_MASK (0xF0000UL) 455 #define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_SHIFT (16U) 456 #define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_SHIFT) 457 458 /* 459 * CSI_1_LPRX_VINIT (RO) 460 * 461 * pt ft indicator in csi lane-1 462 */ 463 #define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_MASK (0xF0U) 464 #define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_SHIFT (4U) 465 #define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_SHIFT) 466 467 /* 468 * CSI_0_LPRX_VINIT (RO) 469 * 470 * pt ft indicator in csi lane-0 471 */ 472 #define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_MASK (0xFU) 473 #define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_SHIFT (0U) 474 #define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_SHIFT) 475 476 /* Bitfield definition for register: CLANE_PARA */ 477 /* 478 * T_CLK_TERMEN (RW) 479 * 480 * time for the clock lane receiver to enable the HS line termination 481 */ 482 #define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK (0xFF00U) 483 #define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT (8U) 484 #define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK) 485 #define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK) >> MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT) 486 487 /* 488 * T_CLK_SETTLE (RW) 489 * 490 * the value of tclk-settle of clklane 491 */ 492 #define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK (0xFFU) 493 #define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT (0U) 494 #define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK) 495 #define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK) >> MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT) 496 497 /* Bitfield definition for register: T_HS_TERMEN */ 498 /* 499 * T_D1_TERMEN (RW) 500 * 501 * the value of ths-termen of datalane1 502 */ 503 #define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK (0xFF00U) 504 #define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT (8U) 505 #define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT) & MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK) 506 #define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK) >> MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT) 507 508 /* 509 * T_D0_TERMEN (RW) 510 * 511 * the value of ths-termen of datalane0 512 */ 513 #define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK (0xFFU) 514 #define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT (0U) 515 #define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT) & MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK) 516 #define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK) >> MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT) 517 518 /* Bitfield definition for register: T_HS_SETTLE */ 519 /* 520 * T_D1_SETTLE (RW) 521 * 522 * the value of ths-settle of data lane1 523 */ 524 #define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK (0xFF00U) 525 #define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT (8U) 526 #define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT) & MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK) 527 #define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK) >> MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT) 528 529 /* 530 * T_D0_SETTLE (RW) 531 * 532 * the value of ths-settle of data lane0 533 */ 534 #define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK (0xFFU) 535 #define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT (0U) 536 #define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT) & MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK) 537 #define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK) >> MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT) 538 539 /* Bitfield definition for register: T_CLANE_INIT */ 540 /* 541 * T_CLK_INIT (RW) 542 * 543 * initialization time of lock lane 544 */ 545 #define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK (0xFFFFFFUL) 546 #define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT (0U) 547 #define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT) & MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK) 548 #define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK) >> MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT) 549 550 /* Bitfield definition for register: T_LANE_INIT0 */ 551 /* 552 * T_D0_INIT (RW) 553 * 554 * initialization time of data lane 555 */ 556 #define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK (0xFFFFFFUL) 557 #define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT (0U) 558 #define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT) & MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK) 559 #define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK) >> MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT) 560 561 /* Bitfield definition for register: T_LANE_INIT1 */ 562 /* 563 * T_D1_INIT (RW) 564 * 565 * initialization time of data lane 566 */ 567 #define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK (0xFFFFFFUL) 568 #define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT (0U) 569 #define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT) & MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK) 570 #define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK) >> MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT) 571 572 /* Bitfield definition for register: TLPX_CTRL */ 573 /* 574 * EN_TLPX_CHECK (RW) 575 * 576 * enable the tlpx width check 577 */ 578 #define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK (0x100U) 579 #define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT (8U) 580 #define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT) & MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK) 581 #define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK) >> MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT) 582 583 /* 584 * TLPX (RW) 585 * 586 * the width of tlpx 587 */ 588 #define MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK (0xFFU) 589 #define MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT (0U) 590 #define MIPI_CSI_PHY_TLPX_CTRL_TLPX_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT) & MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK) 591 #define MIPI_CSI_PHY_TLPX_CTRL_TLPX_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK) >> MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT) 592 593 /* Bitfield definition for register: NE_SWAP */ 594 /* 595 * DPDN_SWAP_LANE1 (RW) 596 * 597 * datalane1 dpdn swap 598 */ 599 #define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK (0x200U) 600 #define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT (9U) 601 #define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK) 602 #define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK) >> MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT) 603 604 /* 605 * DPDN_SWAP_LAN0 (RW) 606 * 607 * datalane0 dpdn swap 608 */ 609 #define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK (0x100U) 610 #define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT (8U) 611 #define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK) 612 #define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK) >> MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT) 613 614 /* 615 * LANE_SWAP_LAN1 (RW) 616 * 617 * data lane1 swap 618 */ 619 #define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK (0xCU) 620 #define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT (2U) 621 #define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK) 622 #define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK) >> MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT) 623 624 /* 625 * LANE_SWAP_LANE0 (RW) 626 * 627 * data lane0 swap 628 */ 629 #define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK (0x3U) 630 #define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT (0U) 631 #define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK) 632 #define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK) >> MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT) 633 634 /* Bitfield definition for register: MISC_INFO */ 635 /* 636 * ULPS_LP10_SEL (RW) 637 * 638 * the lp10 select signal in ulps_exit state 639 */ 640 #define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK (0x2U) 641 #define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT (1U) 642 #define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT) & MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK) 643 #define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK) >> MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT) 644 645 /* 646 * LONG_SOTSYNC_EN (RW) 647 * 648 * at least six zero is checked before sot swquence "00011101" 649 */ 650 #define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK (0x1U) 651 #define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT (0U) 652 #define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT) & MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK) 653 #define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK) >> MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT) 654 655 /* Bitfield definition for register: BIST_TEST0 */ 656 /* 657 * BIST_DONE_LAN1 (RO) 658 * 659 * bist_done of lane1 660 */ 661 #define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_MASK (0x80U) 662 #define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_SHIFT (7U) 663 #define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_SHIFT) 664 665 /* 666 * BIST_DONE_LAN0 (RO) 667 * 668 * bist_done of lane0 669 */ 670 #define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_MASK (0x40U) 671 #define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_SHIFT (6U) 672 #define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_SHIFT) 673 674 /* 675 * BIST_OK_LANE1 (RO) 676 * 677 * bist_ok of lane1 678 */ 679 #define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_MASK (0x8U) 680 #define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_SHIFT (3U) 681 #define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_SHIFT) 682 683 /* 684 * BIST_OK_LANE0 (RO) 685 * 686 * bist_ok of lane0 687 */ 688 #define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_MASK (0x4U) 689 #define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_SHIFT (2U) 690 #define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_SHIFT) 691 692 /* 693 * BIST_EN_SEL (RW) 694 * 695 * the source of bist_en sel 696 */ 697 #define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK (0x2U) 698 #define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT (1U) 699 #define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK) 700 #define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT) 701 702 /* 703 * BIST_EN_SOFT (RW) 704 * 705 * enable prbs bist test 706 */ 707 #define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK (0x1U) 708 #define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT (0U) 709 #define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK) 710 #define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT) 711 712 /* Bitfield definition for register: BIST_TEST1 */ 713 /* 714 * PRBS_CHECK_NUM (RW) 715 * 716 * the byte num of prbs bist check num 717 */ 718 #define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK (0xFFFFFFFFUL) 719 #define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT (0U) 720 #define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT) & MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK) 721 #define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK) >> MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT) 722 723 /* Bitfield definition for register: BIST_TEST2 */ 724 /* 725 * PRBS_SEED (RW) 726 * 727 * the seed of prbs7 728 */ 729 #define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK (0xFF0000UL) 730 #define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT (16U) 731 #define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT) & MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK) 732 #define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK) >> MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT) 733 734 /* 735 * PRBS_ERR_THRESHOLD (RW) 736 * 737 * the threshold of prbs bist error 738 */ 739 #define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK (0xFFFFU) 740 #define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT (0U) 741 #define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT) & MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK) 742 #define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK) >> MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT) 743 744 /* Bitfield definition for register: BIST_TEST3 */ 745 /* 746 * PRBS_ERR_NUM_LAN1 (RO) 747 * 748 * the byte num of mismatch data of data lane1 in bist mode 749 */ 750 #define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_MASK (0xFFFF0000UL) 751 #define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_SHIFT (16U) 752 #define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_SHIFT) 753 754 /* 755 * PRBS_ERR_NUM_LAN0 (RO) 756 * 757 * the byte num of mismatch data of data lane0 in bist mode 758 */ 759 #define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_MASK (0xFFFFU) 760 #define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_SHIFT (0U) 761 #define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_SHIFT) 762 763 /* Bitfield definition for register: BURN_IN_TEST0 */ 764 /* 765 * BURN_IN_OK_CLAN (RO) 766 * 767 * burn_in_ok of clock lane 768 */ 769 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_MASK (0x40U) 770 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_SHIFT (6U) 771 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_SHIFT) 772 773 /* 774 * BURN_IN_OK_LAN1 (RO) 775 * 776 * burn_in_ok of lane1 777 */ 778 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_MASK (0x8U) 779 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_SHIFT (3U) 780 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_SHIFT) 781 782 /* 783 * BURN_IN_OK_LAN0 (RO) 784 * 785 * burn_in_ok of lane0 786 */ 787 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_MASK (0x4U) 788 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_SHIFT (2U) 789 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_SHIFT) 790 791 /* 792 * BURN_IN_EN_SEL (RW) 793 * 794 * the source of prbs burn_in_en sel 795 */ 796 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK (0x2U) 797 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT (1U) 798 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK) 799 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT) 800 801 /* 802 * BURN_IN_EN_SOFT (RW) 803 * 804 * enable prbs burn_in test 805 */ 806 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK (0x1U) 807 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT (0U) 808 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK) 809 #define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT) 810 811 /* Bitfield definition for register: BURN_IN_TEST1 */ 812 /* 813 * BURN_IN_SEED (RW) 814 * 815 * the seed of prbs7 for brun-in test 816 */ 817 #define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK (0xFFU) 818 #define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT (0U) 819 #define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK) 820 #define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT) 821 822 /* Bitfield definition for register: BURN_IN_TEST2 */ 823 /* 824 * BURN_IN_ERR_NUM_LAN1 (RO) 825 * 826 * the bit num of mismatch data on data lan1 in burn-in mode 827 */ 828 #define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_MASK (0xFFFF0000UL) 829 #define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_SHIFT (16U) 830 #define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_SHIFT) 831 832 /* 833 * BURN_IN_ERR_NUM_LAN0 (RO) 834 * 835 * the bit num of mismatch data on data lan0 in burn-in mode 836 */ 837 #define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_MASK (0xFFFFU) 838 #define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_SHIFT (0U) 839 #define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_SHIFT) 840 841 /* Bitfield definition for register: BURN_IN_TEST4 */ 842 /* 843 * BURN_IN_ERR_NUM_CLAN (RO) 844 * 845 * the bit num of mismatch data on clock lane in burn-in mode 846 */ 847 #define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_MASK (0xFFFFU) 848 #define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_SHIFT (0U) 849 #define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_SHIFT) 850 851 /* Bitfield definition for register: BURN_IN_TEST5 */ 852 /* 853 * BURN_IN_CHECK_NUM_LAN0 (RO) 854 * 855 * the checked bit num of lane0 856 */ 857 #define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_MASK (0xFFFFFFFFUL) 858 #define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_SHIFT (0U) 859 #define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_SHIFT) 860 861 /* Bitfield definition for register: BURN_IN_TEST6 */ 862 /* 863 * BURN_IN_CHECKED_NUM_LAN1 (RO) 864 * 865 * the checked bit num of lane1 866 */ 867 #define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_MASK (0xFFFFFFFFUL) 868 #define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_SHIFT (0U) 869 #define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_SHIFT) 870 871 /* Bitfield definition for register: BURN_IN_TEST9 */ 872 /* 873 * BURN_IN_CHECK_NUM_CLAN (RO) 874 * 875 * the checked bit num of clock lane 876 */ 877 #define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_MASK (0xFFFFFFFFUL) 878 #define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_SHIFT (0U) 879 #define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_SHIFT) 880 881 /* Bitfield definition for register: DEBUG_INFO */ 882 /* 883 * DEBUG_MODE_SEL (RW) 884 * 885 * the debug bus sel 886 */ 887 #define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK (0x3F0000UL) 888 #define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT (16U) 889 #define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT) & MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK) 890 #define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK) >> MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT) 891 892 /* Bitfield definition for register: DEBUG_CFG_REG0 */ 893 /* 894 * DEBUG_CFG_REG0 (RW) 895 * 896 * debug config register0 897 */ 898 #define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK (0xFFFFFFFFUL) 899 #define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT (0U) 900 #define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK) 901 #define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT) 902 903 /* Bitfield definition for register: DEBUG_CFG_REG1 */ 904 /* 905 * DEBUG_CFG_REG1 (RW) 906 * 907 * debug config register1 908 */ 909 #define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK (0xFFFFFFFFUL) 910 #define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT (0U) 911 #define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK) 912 #define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT) 913 914 /* Bitfield definition for register: DEBUG_CFG_REG2 */ 915 /* 916 * DEBUG_CFG_REG2 (RW) 917 * 918 * debug config register2 919 */ 920 #define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK (0xFFFFFFFFUL) 921 #define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT (0U) 922 #define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK) 923 #define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT) 924 925 /* Bitfield definition for register: DEBUG_CFG_REG3 */ 926 /* 927 * DEBUG_CFG_REG3 (RW) 928 * 929 * debug config register3 930 */ 931 #define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK (0xFFFFFFFFUL) 932 #define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT (0U) 933 #define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK) 934 #define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT) 935 936 /* Bitfield definition for register: DEBUG_CFG_REG4 */ 937 /* 938 * DEBUG_CFG_REG4 (RW) 939 * 940 * debug config register4 941 */ 942 #define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK (0xFFFFFFFFUL) 943 #define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT (0U) 944 #define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK) 945 #define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT) 946 947 /* Bitfield definition for register: DEBUG_CFG_REG5 */ 948 /* 949 * DEBUG_CFG_REG5 (RW) 950 * 951 * debug config register5 952 */ 953 #define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK (0xFFFFFFFFUL) 954 #define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT (0U) 955 #define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK) 956 #define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT) 957 958 959 960 961 #endif /* HPM_MIPI_CSI_PHY_H */ 962