1 #ifndef __SWM320_H__ 2 #define __SWM320_H__ 3 4 /* 5 * ========================================================================== 6 * ---------- Interrupt Number Definition ----------------------------------- 7 * ========================================================================== 8 */ 9 typedef enum IRQn 10 { 11 /****** Cortex-M0 Processor Exceptions Numbers **********************************************/ 12 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 13 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 14 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 15 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 16 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 17 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 18 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 19 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 20 21 /****** Cortex-M4 specific Interrupt Numbers ************************************************/ 22 GPIOA0_IRQn = 0, 23 GPIOA1_IRQn = 1, 24 GPIOA2_IRQn = 2, 25 GPIOA3_IRQn = 3, 26 GPIOA4_IRQn = 4, 27 GPIOA5_IRQn = 5, 28 GPIOA6_IRQn = 6, 29 GPIOA7_IRQn = 7, 30 GPIOB0_IRQn = 8, 31 GPIOB1_IRQn = 9, 32 GPIOB2_IRQn = 10, 33 GPIOB3_IRQn = 11, 34 GPIOB4_IRQn = 12, 35 GPIOB5_IRQn = 13, 36 GPIOB6_IRQn = 14, 37 GPIOB7_IRQn = 15, 38 GPIOC0_IRQn = 16, 39 GPIOC1_IRQn = 17, 40 GPIOC2_IRQn = 18, 41 GPIOC3_IRQn = 19, 42 GPIOC4_IRQn = 20, 43 GPIOC5_IRQn = 21, 44 GPIOC6_IRQn = 22, 45 GPIOC7_IRQn = 23, 46 GPIOM0_IRQn = 24, 47 GPIOM1_IRQn = 25, 48 GPIOM2_IRQn = 26, 49 GPIOM3_IRQn = 27, 50 GPIOM4_IRQn = 28, 51 GPIOM5_IRQn = 29, 52 GPIOM6_IRQn = 30, 53 GPIOM7_IRQn = 31, 54 DMA_IRQn = 32, 55 LCD_IRQn = 33, 56 NORFLC_IRQn = 34, 57 CAN_IRQn = 35, 58 PULSE_IRQn = 36, 59 WDT_IRQn = 37, 60 PWM_IRQn = 38, 61 UART0_IRQn = 39, 62 UART1_IRQn = 40, 63 UART2_IRQn = 41, 64 UART3_IRQn = 42, 65 UART4_IRQn = 43, 66 I2C0_IRQn = 44, 67 I2C1_IRQn = 45, 68 SPI0_IRQn = 46, 69 ADC0_IRQn = 47, 70 RTC_IRQn = 48, 71 BOD_IRQn = 49, 72 SDIO_IRQn = 50, 73 GPIOA_IRQn = 51, 74 GPIOB_IRQn = 52, 75 GPIOC_IRQn = 53, 76 GPIOM_IRQn = 54, 77 GPION_IRQn = 55, 78 GPIOP_IRQn = 56, 79 ADC1_IRQn = 57, 80 FPU_IRQn = 58, 81 SPI1_IRQn = 59, 82 TIMR0_IRQn = 60, 83 TIMR1_IRQn = 61, 84 TIMR2_IRQn = 62, 85 TIMR3_IRQn = 63, 86 TIMR4_IRQn = 64, 87 TIMR5_IRQn = 65, 88 } IRQn_Type; 89 90 /* 91 * ========================================================================== 92 * ----------- Processor and Core Peripheral Section ------------------------ 93 * ========================================================================== 94 */ 95 96 /* Configuration of the Cortex-M0 Processor and Core Peripherals */ 97 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ 98 #define __MPU_PRESENT 0 /*!< SWM320 not provides an MPU */ 99 #define __NVIC_PRIO_BITS 3 /*!< SWM320 uses 3 Bits for the Priority Levels */ 100 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 101 #define __FPU_PRESENT 0 /*!< FPU present */ 102 103 #if defined ( __CC_ARM ) 104 #pragma anon_unions 105 #endif 106 107 #include <stdio.h> 108 #include <stdbool.h> 109 #include "core_cm4.h" /* Cortex-M0 processor and core peripherals */ 110 #include "system_SWM320.h" 111 112 113 /******************************************************************************/ 114 /* Device Specific Peripheral registers structures */ 115 /******************************************************************************/ 116 typedef struct { 117 __IO uint32_t CLKSEL; //Clock Select 118 119 __IO uint32_t CLKDIV; 120 121 __IO uint32_t CLKEN; //Clock Enable 122 123 __IO uint32_t SLEEP; 124 125 uint32_t RESERVED0[6]; 126 127 __IO uint32_t RTCBKP_ISO; //[0] 1 RTC备份电源域处于隔离状态 0 RTC备份电源域可访问 128 129 __IO uint32_t RTCWKEN; //[0] 1 使能RTC唤醒功能 130 131 uint32_t RESERVED[52+64]; 132 133 __IO uint32_t PAWKEN; //Port A Wakeup Enable 134 __IO uint32_t PBWKEN; 135 __IO uint32_t PCWKEN; 136 137 uint32_t RESERVED2[1+4]; 138 139 __IO uint32_t PAWKSR; //Port A Wakeup Status Register，写1清零 140 __IO uint32_t PBWKSR; 141 __IO uint32_t PCWKSR; 142 143 uint32_t RESERVED3[64-10]; 144 145 __IO uint32_t RSTCR; //Reset Control Register 146 __IO uint32_t RSTSR; //Reset Status Register 147 148 uint32_t RESERVED4[61+64]; 149 150 __IO uint32_t BKP[3]; //数据备份寄存器 151 152 //RTC Power Domain: 0x4001E000 153 uint32_t RESERVED5[(0x4001E000-0x40000508)/4-1]; 154 155 __IO uint32_t RTCBKP[8]; //RTC电源域数据备份寄存器 156 157 __IO uint32_t LRCCR; //Low speed RC Control Register 158 __IO uint32_t LRCTRIM0; //Low speed RC Trim 159 __IO uint32_t LRCTRIM1; 160 161 uint32_t RESERVED6; 162 163 __IO uint32_t RTCLDOTRIM; //RTC Power Domain LDO Trim 164 165 //Analog Control: 0x40031000 166 uint32_t RESERVED7[(0x40031000-0x4001E030)/4-1]; 167 168 __IO uint32_t HRCCR; //High speed RC Control Register 169 170 uint32_t RESERVED8[7]; 171 172 __IO uint32_t XTALCR; 173 174 __IO uint32_t PLLCR; 175 __IO uint32_t PLLDIV; 176 __IO uint32_t PLLSET; 177 __IO uint32_t PLLLOCK; //[0] 1 PLL已锁定 178 179 __IO uint32_t BODIE; 180 __IO uint32_t BODIF; 181 } SYS_TypeDef; 182 183 184 #define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source 0 LRC 1 PLL 185 #define SYS_CLKSEL_LFCK_Msk (0x01 << SYS_CLKSEL_LFCK_Pos) 186 #define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC 1 XTAL 187 #define SYS_CLKSEL_HFCK_Msk (0x01 << SYS_CLKSEL_HFCK_Pos) 188 #define SYS_CLKSEL_SYS_Pos 2 //系统时钟选择 0 LFCK 1 HFCK 189 #define SYS_CLKSEL_SYS_Msk (0x01 << SYS_CLKSEL_SYS_Pos) 190 191 #define SYS_CLKDIV_SYS_Pos 0 //系统时钟分频 0 1分频 1 2分频 192 #define SYS_CLKDIV_SYS_Msk (0x01 << SYS_CLKDIV_SYS_Pos) 193 #define SYS_CLKDIV_PWM_Pos 1 //PWM 时钟分频 0 1分频 1 8分频 194 #define SYS_CLKDIV_PWM_Msk (0x01 << SYS_CLKDIV_PWM_Pos) 195 #define SYS_CLKDIV_SDRAM_Pos 2 //SDRAM时钟分频 0 1分频 1 2分频 2 4分频 196 #define SYS_CLKDIV_SDRAM_Msk (0x03 << SYS_CLKDIV_SDRAM_Pos) 197 #define SYS_CLKDIV_SDIO_Pos 4 //SDIO时钟分频 0 1分频 1 2分频 2 4分频 3 8分频 198 #define SYS_CLKDIV_SDIO_Msk (0x03 << SYS_CLKDIV_SDIO_Pos) 199 200 #define SYS_CLKEN_GPIOA_Pos 0 201 #define SYS_CLKEN_GPIOA_Msk (0x01 << SYS_CLKEN_GPIOA_Pos) 202 #define SYS_CLKEN_GPIOB_Pos 1 203 #define SYS_CLKEN_GPIOB_Msk (0x01 << SYS_CLKEN_GPIOB_Pos) 204 #define SYS_CLKEN_GPIOC_Pos 2 205 #define SYS_CLKEN_GPIOC_Msk (0x01 << SYS_CLKEN_GPIOC_Pos) 206 #define SYS_CLKEN_GPIOM_Pos 4 207 #define SYS_CLKEN_GPIOM_Msk (0x01 << SYS_CLKEN_GPIOM_Pos) 208 #define SYS_CLKEN_GPION_Pos 5 209 #define SYS_CLKEN_GPION_Msk (0x01 << SYS_CLKEN_GPION_Pos) 210 #define SYS_CLKEN_TIMR_Pos 6 211 #define SYS_CLKEN_TIMR_Msk (0x01 << SYS_CLKEN_TIMR_Pos) 212 #define SYS_CLKEN_WDT_Pos 7 213 #define SYS_CLKEN_WDT_Msk (0x01 << SYS_CLKEN_WDT_Pos) 214 #define SYS_CLKEN_ADC0_Pos 8 215 #define SYS_CLKEN_ADC0_Msk (0x01 << SYS_CLKEN_ADC0_Pos) 216 #define SYS_CLKEN_PWM_Pos 9 217 #define SYS_CLKEN_PWM_Msk (0x01 << SYS_CLKEN_PWM_Pos) 218 #define SYS_CLKEN_RTC_Pos 10 219 #define SYS_CLKEN_RTC_Msk (0x01 << SYS_CLKEN_RTC_Pos) 220 #define SYS_CLKEN_UART0_Pos 11 221 #define SYS_CLKEN_UART0_Msk (0x01 << SYS_CLKEN_UART0_Pos) 222 #define SYS_CLKEN_UART1_Pos 12 223 #define SYS_CLKEN_UART1_Msk (0x01 << SYS_CLKEN_UART1_Pos) 224 #define SYS_CLKEN_UART2_Pos 13 225 #define SYS_CLKEN_UART2_Msk (0x01 << SYS_CLKEN_UART2_Pos) 226 #define SYS_CLKEN_UART3_Pos 14 227 #define SYS_CLKEN_UART3_Msk (0x01 << SYS_CLKEN_UART3_Pos) 228 #define SYS_CLKEN_UART4_Pos 15 229 #define SYS_CLKEN_UART4_Msk (0x01 << SYS_CLKEN_UART4_Pos) 230 #define SYS_CLKEN_SPI0_Pos 16 231 #define SYS_CLKEN_SPI0_Msk (0x01 << SYS_CLKEN_SPI0_Pos) 232 #define SYS_CLKEN_I2C0_Pos 17 233 #define SYS_CLKEN_I2C0_Msk (0x01 << SYS_CLKEN_I2C0_Pos) 234 #define SYS_CLKEN_I2C1_Pos 18 235 #define SYS_CLKEN_I2C1_Msk (0x01 << SYS_CLKEN_I2C1_Pos) 236 #define SYS_CLKEN_I2C2_Pos 19 237 #define SYS_CLKEN_I2C2_Msk (0x01 << SYS_CLKEN_I2C2_Pos) 238 #define SYS_CLKEN_LCD_Pos 20 239 #define SYS_CLKEN_LCD_Msk (0x01 << SYS_CLKEN_LCD_Pos) 240 #define SYS_CLKEN_GPIOP_Pos 21 241 #define SYS_CLKEN_GPIOP_Msk (0x01 << SYS_CLKEN_GPIOP_Pos) 242 #define SYS_CLKEN_ANAC_Pos 22 //模拟控制单元时钟使能 243 #define SYS_CLKEN_ANAC_Msk (0x01 << SYS_CLKEN_ANAC_Pos) 244 #define SYS_CLKEN_CRC_Pos 23 245 #define SYS_CLKEN_CRC_Msk (0x01 << SYS_CLKEN_CRC_Pos) 246 #define SYS_CLKEN_RTCBKP_Pos 24 247 #define SYS_CLKEN_RTCBKP_Msk (0x01 << SYS_CLKEN_RTCBKP_Pos) 248 #define SYS_CLKEN_CAN_Pos 25 249 #define SYS_CLKEN_CAN_Msk (0x01 << SYS_CLKEN_CAN_Pos) 250 #define SYS_CLKEN_SDRAM_Pos 26 251 #define SYS_CLKEN_SDRAM_Msk (0x01 << SYS_CLKEN_SDRAM_Pos) 252 #define SYS_CLKEN_NORFL_Pos 27 //NOR Flash 253 #define SYS_CLKEN_NORFL_Msk (0x01 << SYS_CLKEN_NORFL_Pos) 254 #define SYS_CLKEN_RAMC_Pos 28 255 #define SYS_CLKEN_RAMC_Msk (0x01 << SYS_CLKEN_RAMC_Pos) 256 #define SYS_CLKEN_SDIO_Pos 29 257 #define SYS_CLKEN_SDIO_Msk (0x01 << SYS_CLKEN_SDIO_Pos) 258 #define SYS_CLKEN_ADC1_Pos 30 259 #define SYS_CLKEN_ADC1_Msk (0x01 << SYS_CLKEN_ADC1_Pos) 260 #define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVE电源域系统时钟使能 261 #define SYS_CLKEN_ALIVE_Msk (0x01 << SYS_CLKEN_ALIVE_Pos) 262 263 #define SYS_SLEEP_SLEEP_Pos 0 //将该位置1后，系统将进入SLEEP模式 264 #define SYS_SLEEP_SLEEP_Msk (0x01 << SYS_SLEEP_SLEEP_Pos) 265 #define SYS_SLEEP_DEEP_Pos 1 //将该位置1后，系统将进入STOP SLEEP模式 266 #define SYS_SLEEP_DEEP_Msk (0x01 << SYS_SLEEP_DEEP_Pos) 267 268 #define SYS_RSTCR_SYS_Pos 0 //写1进行系统复位，硬件自动清零 269 #define SYS_RSTCR_SYS_Msk (0x01 << SYS_RSTCR_SYS_Pos) 270 #define SYS_RSTCR_FLASH_Pos 1 //写1对FLASH控制器进行一次复位，硬件自动清零 271 #define SYS_RSTCR_FLASH_Msk (0x01 << SYS_RSTCR_FLASH_Pos) 272 #define SYS_RSTCR_PWM_Pos 2 //写1对PWM进行一次复位，硬件自动清零 273 #define SYS_RSTCR_PWM_Msk (0x01 << SYS_RSTCR_PWM_Pos) 274 #define SYS_RSTCR_CPU_Pos 3 //写1对CPU进行一次复位，硬件自动清零 275 #define SYS_RSTCR_CPU_Msk (0x01 << SYS_RSTCR_CPU_Pos) 276 #define SYS_RSTCR_DMA_Pos 4 //写1对DMA进行一次复位，硬件自动清零 277 #define SYS_RSTCR_DMA_Msk (0x01 << SYS_RSTCR_DMA_Pos) 278 #define SYS_RSTCR_NORFLASH_Pos 5 //写1对NOR Flash控制器进行一次复位，硬件自动清零 279 #define SYS_RSTCR_NORFLASH_Msk (0x01 << SYS_RSTCR_NORFLASH_Pos) 280 #define SYS_RSTCR_SRAM_Pos 6 //写1对SRAM控制器进行一次复位，硬件自动清零 281 #define SYS_RSTCR_SRAM_Msk (0x01 << SYS_RSTCR_SRAM_Pos) 282 #define SYS_RSTCR_SDRAM_Pos 7 //写1对SDRAM控制器进行一次复位，硬件自动清零 283 #define SYS_RSTCR_SDRAM_Msk (0x01 << SYS_RSTCR_SDRAM_Pos) 284 #define SYS_RSTCR_SDIO_Pos 8 //写1对SDIO进行一次复位，硬件自动清零 285 #define SYS_RSTCR_SDIO_Msk (0x01 << SYS_RSTCR_SDIO_Pos) 286 #define SYS_RSTCR_LCD_Pos 9 //写1对LCD进行一次复位，硬件自动清零 287 #define SYS_RSTCR_LCD_Msk (0x01 << SYS_RSTCR_LCD_Pos) 288 #define SYS_RSTCR_CAN_Pos 10 //写1对CAN进行一次复位，硬件自动清零 289 #define SYS_RSTCR_CAN_Msk (0x01 << SYS_RSTCR_CAN_Pos) 290 291 #define SYS_RSTSR_POR_Pos 0 //1 出现过POR复位，写1清零 292 #define SYS_RSTSR_POR_Msk (0x01 << SYS_RSTSR_POR_Pos) 293 #define SYS_RSTSR_BOD_Pos 1 //1 出现过BOD复位，写1清零 294 #define SYS_RSTSR_BOD_Msk (0x01 << SYS_RSTSR_BOD_Pos) 295 #define SYS_RSTSR_PIN_Pos 2 //1 出现过外部引脚复位，写1清零 296 #define SYS_RSTSR_PIN_Msk (0x01 << SYS_RSTSR_PIN_Pos) 297 #define SYS_RSTSR_WDT_Pos 3 //1 出现过WDT复位，写1清零 298 #define SYS_RSTSR_WDT_Msk (0x01 << SYS_RSTSR_WDT_Pos) 299 #define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 出现过软件复位，写1清零 300 #define SYS_RSTSR_SWRST_Msk (0x01 << SYS_RSTSR_SWRST_Pos) 301 302 #define SYS_LRCCR_OFF_Pos 0 //Low Speed RC Off 303 #define SYS_LRCCR_OFF_Msk (0x01 << SYS_LRCCR_OFF_Pos) 304 305 #define SYS_LRCTRIM0_R_Pos 0 //LRC粗调控制位 306 #define SYS_LRCTRIM0_R_Msk (0x7FFF << SYS_LRCTRIM0_R_Pos) 307 #define SYS_LRCTRIM0_M_Pos 15 //LRC中调控制位 308 #define SYS_LRCTRIM0_M_Msk (0x3F << SYS_LRCTRIM2_M_Pos) 309 #define SYS_LRCTRIM0_F_Pos 21 //LRC细调控制位 310 #define SYS_LRCTRIM0_F_Msk (0x7FF << SYS_LRCTRIM0_F_Pos) 311 312 #define SYS_LRCTRIM1_U_Pos 0 //LRC U调控制位 313 #define SYS_LRCTRIM1_U_Msk (0x7FFF << SYS_LRCTRIM1_U_Pos) 314 315 316 #define SYS_HRCCR_DBL_Pos 0 //Double Frequency 0 20MHz 1 40MHz 317 #define SYS_HRCCR_DBL_Msk (0x01 << SYS_HRCCR_DBL_Pos) 318 #define SYS_HRCCR_OFF_Pos 1 //High speed RC Off 319 #define SYS_HRCCR_OFF_Msk (0x01 << SYS_HRCCR_OFF_Pos) 320 321 #define SYS_XTALCR_EN_Pos 0 322 #define SYS_XTALCR_EN_Msk (0x01 << SYS_XTALCR_EN_Pos) 323 324 #define SYS_PLLCR_OUTEN_Pos 0 //只能LOCK后设置 325 #define SYS_PLLCR_OUTEN_Msk (0x01 << SYS_PLLCR_OUTEN_Pos) 326 #define SYS_PLLCR_INSEL_Pos 1 //0 XTAL 1 HRC 327 #define SYS_PLLCR_INSEL_Msk (0x01 << SYS_PLLCR_INSEL_Pos) 328 #define SYS_PLLCR_OFF_Pos 2 329 #define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos) 330 331 #define SYS_PLLDIV_FBDIV_Pos 0 //PLL FeedBack分频寄存器 332 //VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV 333 //PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV 334 #define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos) 335 #define SYS_PLLDIV_ADDIV_Pos 9 //ADC时钟基（即VCO输出分频后的时钟）经ADDIV分频后作为ADC的转换时钟 336 #define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos) 337 #define SYS_PLLDIV_ADVCO_Pos 14 //0 VCO输出16分频作为ADC时钟基 1 VCO输出经过32分频作为ADC时钟基 2 VCO输出经过64分频作为ADC时钟基 338 #define SYS_PLLDIV_ADVCO_Msk (0x03 << SYS_PLLDIV_ADVCO_Pos) 339 #define SYS_PLLDIV_INDIV_Pos 16 //PLL 输入源时钟分频 340 #define SYS_PLLDIV_INDIV_Msk (0x1F << SYS_PLLDIV_INDIV_Pos) 341 #define SYS_PLLDIV_OUTDIV_Pos 24 //PLL 输出分频，0 8分频 1 4分频 0 2分频 342 #define SYS_PLLDIV_OUTDIV_Msk (0x03 << SYS_PLLDIV_OUTDIV_Pos) 343 344 #define SYS_PLLSET_LPFBW_Pos 0 //PLL Low Pass Filter Bandwidth 345 #define SYS_PLLSET_LPFBW_Msk (0x0F << SYS_PLLSET_LPFBW_Pos) 346 #define SYS_PLLSET_BIASADJ_Pos 4 //PLL Current Bias Adjustment 347 #define SYS_PLLSET_BIASADJ_Msk (0x03 << SYS_PLLSET_BIASADJ_Pos) 348 #define SYS_PLLSET_REFVSEL_Pos 6 //PLL Reference Voltage Select 349 #define SYS_PLLSET_REFVSEL_Msk (0x03 << SYS_PLLSET_REFVSEL_Pos) 350 #define SYS_PLLSET_CHPADJL_Pos 8 //PLL charge pump LSB current Adjustment 351 #define SYS_PLLSET_CHPADJL_Msk (0x07 << SYS_PLLSET_CHPADJL_Pos) 352 #define SYS_PLLSET_CHPADJM_Pos 11 //PLL charge pump MSB current Adjustment 353 #define SYS_PLLSET_CHPADJM_Msk (0x03 << SYS_PLLSET_CHPADJM_Pos) 354 355 #define SYS_BODIE_2V2_Pos 1 //BOD 2.2V等级触发中断使能 356 #define SYS_BODIE_2V2_Msk (0x01 << SYS_BODIE_2V2_Pos) 357 358 #define SYS_BODIF_2V2_Pos 1 //BOD 2.2V等级触发中断状态，写1清零 359 #define SYS_BODIF_2V2_Msk (0x01 << SYS_BODIF_2V2_Pos) 360 361 362 363 364 typedef struct { 365 __IO uint32_t PORTA_SEL; //给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能 366 //当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设 367 __IO uint32_t PORTB_SEL; 368 369 __IO uint32_t PORTC_SEL; 370 371 uint32_t RESERVED[5]; 372 373 __IO uint32_t PORTM_SEL0; 374 375 __IO uint32_t PORTM_SEL1; 376 377 uint32_t RESERVED2[2]; 378 379 __IO uint32_t PORTN_SEL0; 380 381 __IO uint32_t PORTN_SEL1; 382 383 uint32_t RESERVED3[2]; 384 385 __IO uint32_t PORTP_SEL0; 386 387 __IO uint32_t PORTP_SEL1; 388 389 uint32_t RESERVED4[46]; 390 391 __IO uint32_t PORTA_MUX0; 392 393 __IO uint32_t PORTA_MUX1; 394 395 uint32_t RESERVED5[2]; 396 397 __IO uint32_t PORTB_MUX0; 398 399 __IO uint32_t PORTB_MUX1; 400 401 uint32_t RESERVED6[2]; 402 403 __IO uint32_t PORTC_MUX0; 404 405 __IO uint32_t PORTC_MUX1; 406 407 uint32_t RESERVED7[14]; 408 409 __IO uint32_t PORTM_MUX0; 410 411 __IO uint32_t PORTM_MUX1; 412 413 __IO uint32_t PORTM_MUX2; 414 415 __IO uint32_t PORTM_MUX3; 416 417 __IO uint32_t PORTN_MUX0; 418 419 __IO uint32_t PORTN_MUX1; 420 421 __IO uint32_t PORTN_MUX2; 422 423 uint32_t RESERVED8; 424 425 __IO uint32_t PORTP_MUX0; 426 427 __IO uint32_t PORTP_MUX1; 428 429 __IO uint32_t PORTP_MUX2; 430 431 __IO uint32_t PORTP_MUX3; 432 433 uint32_t RESERVED9[28]; 434 435 __IO uint32_t PORTA_PULLU; //上拉使能 436 437 uint32_t RESERVED10[3]; 438 439 __IO uint32_t PORTC_PULLU; 440 441 uint32_t RESERVED11[3]; 442 443 __IO uint32_t PORTM_PULLU; 444 445 uint32_t RESERVED12[3]; 446 447 __IO uint32_t PORTP_PULLU; 448 449 uint32_t RESERVED13[51]; 450 451 __IO uint32_t PORTB_PULLD; //下拉使能 452 453 uint32_t RESERVED14[3]; 454 455 __IO uint32_t PORTD_PULLD; 456 457 uint32_t RESERVED15[3]; 458 459 __IO uint32_t PORTN_PULLD; 460 461 uint32_t RESERVED16[135]; 462 463 __IO uint32_t PORTM_DRIVS; //驱动强度 464 465 uint32_t RESERVED17[3]; 466 467 __IO uint32_t PORTN_DRIVS; 468 469 uint32_t RESERVED18[3]; 470 471 __IO uint32_t PORTP_DRIVS; 472 473 uint32_t RESERVED19[39]; 474 475 __IO uint32_t PORTA_INEN; //输入使能 476 477 uint32_t RESERVED20[3]; 478 479 __IO uint32_t PORTB_INEN; 480 481 uint32_t RESERVED21[3]; 482 483 __IO uint32_t PORTC_INEN; 484 485 uint32_t RESERVED22[7]; 486 487 __IO uint32_t PORTM_INEN; 488 489 uint32_t RESERVED23[3]; 490 491 __IO uint32_t PORTN_INEN; 492 493 uint32_t RESERVED24[3]; 494 495 __IO uint32_t PORTP_INEN; 496 } PORT_TypeDef; 497 498 499 #define PORT_PORTA_PULLU_PIN0_Pos 0 500 #define PORT_PORTA_PULLU_PIN0_Msk (0x01 << PORT_PORTA_PULLU_PIN0_Pos) 501 #define PORT_PORTA_PULLU_PIN1_Pos 1 502 #define PORT_PORTA_PULLU_PIN1_Msk (0x01 << PORT_PORTA_PULLU_PIN1_Pos) 503 #define PORT_PORTA_PULLU_PIN2_Pos 2 504 #define PORT_PORTA_PULLU_PIN2_Msk (0x01 << PORT_PORTA_PULLU_PIN2_Pos) 505 #define PORT_PORTA_PULLU_PIN3_Pos 3 506 #define PORT_PORTA_PULLU_PIN3_Msk (0x01 << PORT_PORTA_PULLU_PIN3_Pos) 507 #define PORT_PORTA_PULLU_PIN4_Pos 4 508 #define PORT_PORTA_PULLU_PIN4_Msk (0x01 << PORT_PORTA_PULLU_PIN4_Pos) 509 #define PORT_PORTA_PULLU_PIN5_Pos 5 510 #define PORT_PORTA_PULLU_PIN5_Msk (0x01 << PORT_PORTA_PULLU_PIN5_Pos) 511 #define PORT_PORTA_PULLU_PIN6_Pos 6 512 #define PORT_PORTA_PULLU_PIN6_Msk (0x01 << PORT_PORTA_PULLU_PIN6_Pos) 513 #define PORT_PORTA_PULLU_PIN7_Pos 7 514 #define PORT_PORTA_PULLU_PIN7_Msk (0x01 << PORT_PORTA_PULLU_PIN7_Pos) 515 #define PORT_PORTA_PULLU_PIN8_Pos 8 516 #define PORT_PORTA_PULLU_PIN8_Msk (0x01 << PORT_PORTA_PULLU_PIN8_Pos) 517 #define PORT_PORTA_PULLU_PIN9_Pos 9 518 #define PORT_PORTA_PULLU_PIN9_Msk (0x01 << PORT_PORTA_PULLU_PIN9_Pos) 519 #define PORT_PORTA_PULLU_PIN10_Pos 10 520 #define PORT_PORTA_PULLU_PIN10_Msk (0x01 << PORT_PORTA_PULLU_PIN10_Pos) 521 #define PORT_PORTA_PULLU_PIN11_Pos 11 522 #define PORT_PORTA_PULLU_PIN11_Msk (0x01 << PORT_PORTA_PULLU_PIN11_Pos) 523 #define PORT_PORTA_PULLU_PIN12_Pos 12 524 #define PORT_PORTA_PULLU_PIN12_Msk (0x01 << PORT_PORTA_PULLU_PIN12_Pos) 525 #define PORT_PORTA_PULLU_PIN13_Pos 13 526 #define PORT_PORTA_PULLU_PIN13_Msk (0x01 << PORT_PORTA_PULLU_PIN13_Pos) 527 #define PORT_PORTA_PULLU_PIN14_Pos 14 528 #define PORT_PORTA_PULLU_PIN14_Msk (0x01 << PORT_PORTA_PULLU_PIN14_Pos) 529 #define PORT_PORTA_PULLU_PIN15_Pos 15 530 #define PORT_PORTA_PULLU_PIN15_Msk (0x01 << PORT_PORTA_PULLU_PIN15_Pos) 531 532 #define PORT_PORTC_PULLU_PIN0_Pos 0 533 #define PORT_PORTC_PULLU_PIN0_Msk (0x01 << PORT_PORTC_PULLU_PIN0_Pos) 534 #define PORT_PORTC_PULLU_PIN1_Pos 1 535 #define PORT_PORTC_PULLU_PIN1_Msk (0x01 << PORT_PORTC_PULLU_PIN1_Pos) 536 #define PORT_PORTC_PULLU_PIN2_Pos 2 537 #define PORT_PORTC_PULLU_PIN2_Msk (0x01 << PORT_PORTC_PULLU_PIN2_Pos) 538 #define PORT_PORTC_PULLU_PIN3_Pos 3 539 #define PORT_PORTC_PULLU_PIN3_Msk (0x01 << PORT_PORTC_PULLU_PIN3_Pos) 540 #define PORT_PORTC_PULLU_PIN4_Pos 4 541 #define PORT_PORTC_PULLU_PIN4_Msk (0x01 << PORT_PORTC_PULLU_PIN4_Pos) 542 #define PORT_PORTC_PULLU_PIN5_Pos 5 543 #define PORT_PORTC_PULLU_PIN5_Msk (0x01 << PORT_PORTC_PULLU_PIN5_Pos) 544 #define PORT_PORTC_PULLU_PIN6_Pos 6 545 #define PORT_PORTC_PULLU_PIN6_Msk (0x01 << PORT_PORTC_PULLU_PIN6_Pos) 546 #define PORT_PORTC_PULLU_PIN7_Pos 7 547 #define PORT_PORTC_PULLU_PIN7_Msk (0x01 << PORT_PORTC_PULLU_PIN7_Pos) 548 #define PORT_PORTC_PULLU_PIN8_Pos 8 549 #define PORT_PORTC_PULLU_PIN8_Msk (0x01 << PORT_PORTC_PULLU_PIN8_Pos) 550 #define PORT_PORTC_PULLU_PIN9_Pos 9 551 #define PORT_PORTC_PULLU_PIN9_Msk (0x01 << PORT_PORTC_PULLU_PIN9_Pos) 552 #define PORT_PORTC_PULLU_PIN10_Pos 10 553 #define PORT_PORTC_PULLU_PIN10_Msk (0x01 << PORT_PORTC_PULLU_PIN10_Pos) 554 #define PORT_PORTC_PULLU_PIN11_Pos 11 555 #define PORT_PORTC_PULLU_PIN11_Msk (0x01 << PORT_PORTC_PULLU_PIN11_Pos) 556 #define PORT_PORTC_PULLU_PIN12_Pos 12 557 #define PORT_PORTC_PULLU_PIN12_Msk (0x01 << PORT_PORTC_PULLU_PIN12_Pos) 558 #define PORT_PORTC_PULLU_PIN13_Pos 13 559 #define PORT_PORTC_PULLU_PIN13_Msk (0x01 << PORT_PORTC_PULLU_PIN13_Pos) 560 #define PORT_PORTC_PULLU_PIN14_Pos 14 561 #define PORT_PORTC_PULLU_PIN14_Msk (0x01 << PORT_PORTC_PULLU_PIN14_Pos) 562 #define PORT_PORTC_PULLU_PIN15_Pos 15 563 #define PORT_PORTC_PULLU_PIN15_Msk (0x01 << PORT_PORTC_PULLU_PIN15_Pos) 564 565 #define PORT_PORTM_PULLU_PIN0_Pos 0 566 #define PORT_PORTM_PULLU_PIN0_Msk (0x01 << PORT_PORTM_PULLU_PIN0_Pos) 567 #define PORT_PORTM_PULLU_PIN1_Pos 1 568 #define PORT_PORTM_PULLU_PIN1_Msk (0x01 << PORT_PORTM_PULLU_PIN1_Pos) 569 #define PORT_PORTM_PULLU_PIN2_Pos 2 570 #define PORT_PORTM_PULLU_PIN2_Msk (0x01 << PORT_PORTM_PULLU_PIN2_Pos) 571 #define PORT_PORTM_PULLU_PIN3_Pos 3 572 #define PORT_PORTM_PULLU_PIN3_Msk (0x01 << PORT_PORTM_PULLU_PIN3_Pos) 573 #define PORT_PORTM_PULLU_PIN4_Pos 4 574 #define PORT_PORTM_PULLU_PIN4_Msk (0x01 << PORT_PORTM_PULLU_PIN4_Pos) 575 #define PORT_PORTM_PULLU_PIN5_Pos 5 576 #define PORT_PORTM_PULLU_PIN5_Msk (0x01 << PORT_PORTM_PULLU_PIN5_Pos) 577 #define PORT_PORTM_PULLU_PIN6_Pos 6 578 #define PORT_PORTM_PULLU_PIN6_Msk (0x01 << PORT_PORTM_PULLU_PIN6_Pos) 579 #define PORT_PORTM_PULLU_PIN7_Pos 7 580 #define PORT_PORTM_PULLU_PIN7_Msk (0x01 << PORT_PORTM_PULLU_PIN7_Pos) 581 #define PORT_PORTM_PULLU_PIN8_Pos 8 582 #define PORT_PORTM_PULLU_PIN8_Msk (0x01 << PORT_PORTM_PULLU_PIN8_Pos) 583 #define PORT_PORTM_PULLU_PIN9_Pos 9 584 #define PORT_PORTM_PULLU_PIN9_Msk (0x01 << PORT_PORTM_PULLU_PIN9_Pos) 585 #define PORT_PORTM_PULLU_PIN10_Pos 10 586 #define PORT_PORTM_PULLU_PIN10_Msk (0x01 << PORT_PORTM_PULLU_PIN10_Pos) 587 #define PORT_PORTM_PULLU_PIN11_Pos 11 588 #define PORT_PORTM_PULLU_PIN11_Msk (0x01 << PORT_PORTM_PULLU_PIN11_Pos) 589 #define PORT_PORTM_PULLU_PIN12_Pos 12 590 #define PORT_PORTM_PULLU_PIN12_Msk (0x01 << PORT_PORTM_PULLU_PIN12_Pos) 591 #define PORT_PORTM_PULLU_PIN13_Pos 13 592 #define PORT_PORTM_PULLU_PIN13_Msk (0x01 << PORT_PORTM_PULLU_PIN13_Pos) 593 #define PORT_PORTM_PULLU_PIN14_Pos 14 594 #define PORT_PORTM_PULLU_PIN14_Msk (0x01 << PORT_PORTM_PULLU_PIN14_Pos) 595 #define PORT_PORTM_PULLU_PIN15_Pos 15 596 #define PORT_PORTM_PULLU_PIN15_Msk (0x01 << PORT_PORTM_PULLU_PIN15_Pos) 597 #define PORT_PORTM_PULLU_PIN16_Pos 16 598 #define PORT_PORTM_PULLU_PIN16_Msk (0x01 << PORT_PORTM_PULLU_PIN16_Pos) 599 #define PORT_PORTM_PULLU_PIN17_Pos 17 600 #define PORT_PORTM_PULLU_PIN17_Msk (0x01 << PORT_PORTM_PULLU_PIN17_Pos) 601 #define PORT_PORTM_PULLU_PIN18_Pos 18 602 #define PORT_PORTM_PULLU_PIN18_Msk (0x01 << PORT_PORTM_PULLU_PIN18_Pos) 603 #define PORT_PORTM_PULLU_PIN19_Pos 19 604 #define PORT_PORTM_PULLU_PIN19_Msk (0x01 << PORT_PORTM_PULLU_PIN19_Pos) 605 #define PORT_PORTM_PULLU_PIN20_Pos 20 606 #define PORT_PORTM_PULLU_PIN20_Msk (0x01 << PORT_PORTM_PULLU_PIN20_Pos) 607 #define PORT_PORTM_PULLU_PIN21_Pos 21 608 #define PORT_PORTM_PULLU_PIN21_Msk (0x01 << PORT_PORTM_PULLU_PIN21_Pos) 609 #define PORT_PORTM_PULLU_PIN22_Pos 22 610 #define PORT_PORTM_PULLU_PIN22_Msk (0x01 << PORT_PORTM_PULLU_PIN22_Pos) 611 #define PORT_PORTM_PULLU_PIN23_Pos 23 612 #define PORT_PORTM_PULLU_PIN23_Msk (0x01 << PORT_PORTM_PULLU_PIN23_Pos) 613 614 #define PORT_PORTP_PULLU_PIN0_Pos 0 615 #define PORT_PORTP_PULLU_PIN0_Msk (0x01 << PORT_PORTP_PULLU_PIN0_Pos) 616 #define PORT_PORTP_PULLU_PIN1_Pos 1 617 #define PORT_PORTP_PULLU_PIN1_Msk (0x01 << PORT_PORTP_PULLU_PIN1_Pos) 618 #define PORT_PORTP_PULLU_PIN2_Pos 2 619 #define PORT_PORTP_PULLU_PIN2_Msk (0x01 << PORT_PORTP_PULLU_PIN2_Pos) 620 #define PORT_PORTP_PULLU_PIN3_Pos 3 621 #define PORT_PORTP_PULLU_PIN3_Msk (0x01 << PORT_PORTP_PULLU_PIN3_Pos) 622 #define PORT_PORTP_PULLU_PIN4_Pos 4 623 #define PORT_PORTP_PULLU_PIN4_Msk (0x01 << PORT_PORTP_PULLU_PIN4_Pos) 624 #define PORT_PORTP_PULLU_PIN5_Pos 5 625 #define PORT_PORTP_PULLU_PIN5_Msk (0x01 << PORT_PORTP_PULLU_PIN5_Pos) 626 #define PORT_PORTP_PULLU_PIN6_Pos 6 627 #define PORT_PORTP_PULLU_PIN6_Msk (0x01 << PORT_PORTP_PULLU_PIN6_Pos) 628 #define PORT_PORTP_PULLU_PIN7_Pos 7 629 #define PORT_PORTP_PULLU_PIN7_Msk (0x01 << PORT_PORTP_PULLU_PIN7_Pos) 630 #define PORT_PORTP_PULLU_PIN8_Pos 8 631 #define PORT_PORTP_PULLU_PIN8_Msk (0x01 << PORT_PORTP_PULLU_PIN8_Pos) 632 #define PORT_PORTP_PULLU_PIN9_Pos 9 633 #define PORT_PORTP_PULLU_PIN9_Msk (0x01 << PORT_PORTP_PULLU_PIN9_Pos) 634 #define PORT_PORTP_PULLU_PIN10_Pos 10 635 #define PORT_PORTP_PULLU_PIN10_Msk (0x01 << PORT_PORTP_PULLU_PIN10_Pos) 636 #define PORT_PORTP_PULLU_PIN11_Pos 11 637 #define PORT_PORTP_PULLU_PIN11_Msk (0x01 << PORT_PORTP_PULLU_PIN11_Pos) 638 #define PORT_PORTP_PULLU_PIN12_Pos 12 639 #define PORT_PORTP_PULLU_PIN12_Msk (0x01 << PORT_PORTP_PULLU_PIN12_Pos) 640 #define PORT_PORTP_PULLU_PIN13_Pos 13 641 #define PORT_PORTP_PULLU_PIN13_Msk (0x01 << PORT_PORTP_PULLU_PIN13_Pos) 642 #define PORT_PORTP_PULLU_PIN14_Pos 14 643 #define PORT_PORTP_PULLU_PIN14_Msk (0x01 << PORT_PORTP_PULLU_PIN14_Pos) 644 #define PORT_PORTP_PULLU_PIN15_Pos 15 645 #define PORT_PORTP_PULLU_PIN15_Msk (0x01 << PORT_PORTP_PULLU_PIN15_Pos) 646 #define PORT_PORTP_PULLU_PIN16_Pos 16 647 #define PORT_PORTP_PULLU_PIN16_Msk (0x01 << PORT_PORTP_PULLU_PIN16_Pos) 648 #define PORT_PORTP_PULLU_PIN17_Pos 17 649 #define PORT_PORTP_PULLU_PIN17_Msk (0x01 << PORT_PORTP_PULLU_PIN17_Pos) 650 #define PORT_PORTP_PULLU_PIN18_Pos 18 651 #define PORT_PORTP_PULLU_PIN18_Msk (0x01 << PORT_PORTP_PULLU_PIN18_Pos) 652 #define PORT_PORTP_PULLU_PIN19_Pos 19 653 #define PORT_PORTP_PULLU_PIN19_Msk (0x01 << PORT_PORTP_PULLU_PIN19_Pos) 654 #define PORT_PORTP_PULLU_PIN20_Pos 20 655 #define PORT_PORTP_PULLU_PIN20_Msk (0x01 << PORT_PORTP_PULLU_PIN20_Pos) 656 #define PORT_PORTP_PULLU_PIN21_Pos 21 657 #define PORT_PORTP_PULLU_PIN21_Msk (0x01 << PORT_PORTP_PULLU_PIN21_Pos) 658 #define PORT_PORTP_PULLU_PIN22_Pos 22 659 #define PORT_PORTP_PULLU_PIN22_Msk (0x01 << PORT_PORTP_PULLU_PIN22_Pos) 660 #define PORT_PORTP_PULLU_PIN23_Pos 23 661 #define PORT_PORTP_PULLU_PIN23_Msk (0x01 << PORT_PORTP_PULLU_PIN23_Pos) 662 663 #define PORT_PORTB_PULLD_PIN0_Pos 0 664 #define PORT_PORTB_PULLD_PIN0_Msk (0x01 << PORT_PORTB_PULLD_PIN0_Pos) 665 #define PORT_PORTB_PULLD_PIN1_Pos 1 666 #define PORT_PORTB_PULLD_PIN1_Msk (0x01 << PORT_PORTB_PULLD_PIN1_Pos) 667 #define PORT_PORTB_PULLD_PIN2_Pos 2 668 #define PORT_PORTB_PULLD_PIN2_Msk (0x01 << PORT_PORTB_PULLD_PIN2_Pos) 669 #define PORT_PORTB_PULLD_PIN3_Pos 3 670 #define PORT_PORTB_PULLD_PIN3_Msk (0x01 << PORT_PORTB_PULLD_PIN3_Pos) 671 #define PORT_PORTB_PULLD_PIN4_Pos 4 672 #define PORT_PORTB_PULLD_PIN4_Msk (0x01 << PORT_PORTB_PULLD_PIN4_Pos) 673 #define PORT_PORTB_PULLD_PIN5_Pos 5 674 #define PORT_PORTB_PULLD_PIN5_Msk (0x01 << PORT_PORTB_PULLD_PIN5_Pos) 675 #define PORT_PORTB_PULLD_PIN6_Pos 6 676 #define PORT_PORTB_PULLD_PIN6_Msk (0x01 << PORT_PORTB_PULLD_PIN6_Pos) 677 #define PORT_PORTB_PULLD_PIN7_Pos 7 678 #define PORT_PORTB_PULLD_PIN7_Msk (0x01 << PORT_PORTB_PULLD_PIN7_Pos) 679 #define PORT_PORTB_PULLD_PIN8_Pos 8 680 #define PORT_PORTB_PULLD_PIN8_Msk (0x01 << PORT_PORTB_PULLD_PIN8_Pos) 681 #define PORT_PORTB_PULLD_PIN9_Pos 9 682 #define PORT_PORTB_PULLD_PIN9_Msk (0x01 << PORT_PORTB_PULLD_PIN9_Pos) 683 #define PORT_PORTB_PULLD_PIN10_Pos 10 684 #define PORT_PORTB_PULLD_PIN10_Msk (0x01 << PORT_PORTB_PULLD_PIN10_Pos) 685 #define PORT_PORTB_PULLD_PIN11_Pos 11 686 #define PORT_PORTB_PULLD_PIN11_Msk (0x01 << PORT_PORTB_PULLD_PIN11_Pos) 687 #define PORT_PORTB_PULLD_PIN12_Pos 12 688 #define PORT_PORTB_PULLD_PIN12_Msk (0x01 << PORT_PORTB_PULLD_PIN12_Pos) 689 #define PORT_PORTB_PULLD_PIN13_Pos 13 690 #define PORT_PORTB_PULLD_PIN13_Msk (0x01 << PORT_PORTB_PULLD_PIN13_Pos) 691 #define PORT_PORTB_PULLD_PIN14_Pos 14 692 #define PORT_PORTB_PULLD_PIN14_Msk (0x01 << PORT_PORTB_PULLD_PIN14_Pos) 693 #define PORT_PORTB_PULLD_PIN15_Pos 15 694 #define PORT_PORTB_PULLD_PIN15_Msk (0x01 << PORT_PORTB_PULLD_PIN15_Pos) 695 696 #define PORT_PORTN_PULLD_PIN0_Pos 0 697 #define PORT_PORTN_PULLD_PIN0_Msk (0x01 << PORT_PORTN_PULLD_PIN0_Pos) 698 #define PORT_PORTN_PULLD_PIN1_Pos 1 699 #define PORT_PORTN_PULLD_PIN1_Msk (0x01 << PORT_PORTN_PULLD_PIN1_Pos) 700 #define PORT_PORTN_PULLD_PIN2_Pos 2 701 #define PORT_PORTN_PULLD_PIN2_Msk (0x01 << PORT_PORTN_PULLD_PIN2_Pos) 702 #define PORT_PORTN_PULLD_PIN3_Pos 3 703 #define PORT_PORTN_PULLD_PIN3_Msk (0x01 << PORT_PORTN_PULLD_PIN3_Pos) 704 #define PORT_PORTN_PULLD_PIN4_Pos 4 705 #define PORT_PORTN_PULLD_PIN4_Msk (0x01 << PORT_PORTN_PULLD_PIN4_Pos) 706 #define PORT_PORTN_PULLD_PIN5_Pos 5 707 #define PORT_PORTN_PULLD_PIN5_Msk (0x01 << PORT_PORTN_PULLD_PIN5_Pos) 708 #define PORT_PORTN_PULLD_PIN6_Pos 6 709 #define PORT_PORTN_PULLD_PIN6_Msk (0x01 << PORT_PORTN_PULLD_PIN6_Pos) 710 #define PORT_PORTN_PULLD_PIN7_Pos 7 711 #define PORT_PORTN_PULLD_PIN7_Msk (0x01 << PORT_PORTN_PULLD_PIN7_Pos) 712 #define PORT_PORTN_PULLD_PIN8_Pos 8 713 #define PORT_PORTN_PULLD_PIN8_Msk (0x01 << PORT_PORTN_PULLD_PIN8_Pos) 714 #define PORT_PORTN_PULLD_PIN9_Pos 9 715 #define PORT_PORTN_PULLD_PIN9_Msk (0x01 << PORT_PORTN_PULLD_PIN9_Pos) 716 #define PORT_PORTN_PULLD_PIN10_Pos 10 717 #define PORT_PORTN_PULLD_PIN10_Msk (0x01 << PORT_PORTN_PULLD_PIN10_Pos) 718 #define PORT_PORTN_PULLD_PIN11_Pos 11 719 #define PORT_PORTN_PULLD_PIN11_Msk (0x01 << PORT_PORTN_PULLD_PIN11_Pos) 720 #define PORT_PORTN_PULLD_PIN12_Pos 12 721 #define PORT_PORTN_PULLD_PIN12_Msk (0x01 << PORT_PORTN_PULLD_PIN12_Pos) 722 #define PORT_PORTN_PULLD_PIN13_Pos 13 723 #define PORT_PORTN_PULLD_PIN13_Msk (0x01 << PORT_PORTN_PULLD_PIN13_Pos) 724 #define PORT_PORTN_PULLD_PIN14_Pos 14 725 #define PORT_PORTN_PULLD_PIN14_Msk (0x01 << PORT_PORTN_PULLD_PIN14_Pos) 726 #define PORT_PORTN_PULLD_PIN15_Pos 15 727 #define PORT_PORTN_PULLD_PIN15_Msk (0x01 << PORT_PORTN_PULLD_PIN15_Pos) 728 #define PORT_PORTN_PULLD_PIN16_Pos 16 729 #define PORT_PORTN_PULLD_PIN16_Msk (0x01 << PORT_PORTN_PULLD_PIN16_Pos) 730 #define PORT_PORTN_PULLD_PIN17_Pos 17 731 #define PORT_PORTN_PULLD_PIN17_Msk (0x01 << PORT_PORTN_PULLD_PIN17_Pos) 732 #define PORT_PORTN_PULLD_PIN18_Pos 18 733 #define PORT_PORTN_PULLD_PIN18_Msk (0x01 << PORT_PORTN_PULLD_PIN18_Pos) 734 #define PORT_PORTN_PULLD_PIN19_Pos 19 735 #define PORT_PORTN_PULLD_PIN19_Msk (0x01 << PORT_PORTN_PULLD_PIN19_Pos) 736 #define PORT_PORTN_PULLD_PIN20_Pos 20 737 #define PORT_PORTN_PULLD_PIN20_Msk (0x01 << PORT_PORTN_PULLD_PIN20_Pos) 738 #define PORT_PORTN_PULLD_PIN21_Pos 21 739 #define PORT_PORTN_PULLD_PIN21_Msk (0x01 << PORT_PORTN_PULLD_PIN21_Pos) 740 #define PORT_PORTN_PULLD_PIN22_Pos 22 741 #define PORT_PORTN_PULLD_PIN22_Msk (0x01 << PORT_PORTN_PULLD_PIN22_Pos) 742 #define PORT_PORTN_PULLD_PIN23_Pos 23 743 #define PORT_PORTN_PULLD_PIN23_Msk (0x01 << PORT_PORTN_PULLD_PIN23_Pos) 744 745 #define PORT_PORTM_DRIVS_PIN0_Pos 0 746 #define PORT_PORTM_DRIVS_PIN0_Msk (0x01 << PORT_PORTM_DRIVS_PIN0_Pos) 747 #define PORT_PORTM_DRIVS_PIN1_Pos 1 748 #define PORT_PORTM_DRIVS_PIN1_Msk (0x01 << PORT_PORTM_DRIVS_PIN1_Pos) 749 #define PORT_PORTM_DRIVS_PIN2_Pos 2 750 #define PORT_PORTM_DRIVS_PIN2_Msk (0x01 << PORT_PORTM_DRIVS_PIN2_Pos) 751 #define PORT_PORTM_DRIVS_PIN3_Pos 3 752 #define PORT_PORTM_DRIVS_PIN3_Msk (0x01 << PORT_PORTM_DRIVS_PIN3_Pos) 753 #define PORT_PORTM_DRIVS_PIN4_Pos 4 754 #define PORT_PORTM_DRIVS_PIN4_Msk (0x01 << PORT_PORTM_DRIVS_PIN4_Pos) 755 #define PORT_PORTM_DRIVS_PIN5_Pos 5 756 #define PORT_PORTM_DRIVS_PIN5_Msk (0x01 << PORT_PORTM_DRIVS_PIN5_Pos) 757 #define PORT_PORTM_DRIVS_PIN6_Pos 6 758 #define PORT_PORTM_DRIVS_PIN6_Msk (0x01 << PORT_PORTM_DRIVS_PIN6_Pos) 759 #define PORT_PORTM_DRIVS_PIN7_Pos 7 760 #define PORT_PORTM_DRIVS_PIN7_Msk (0x01 << PORT_PORTM_DRIVS_PIN7_Pos) 761 #define PORT_PORTM_DRIVS_PIN8_Pos 8 762 #define PORT_PORTM_DRIVS_PIN8_Msk (0x01 << PORT_PORTM_DRIVS_PIN8_Pos) 763 #define PORT_PORTM_DRIVS_PIN9_Pos 9 764 #define PORT_PORTM_DRIVS_PIN9_Msk (0x01 << PORT_PORTM_DRIVS_PIN9_Pos) 765 #define PORT_PORTM_DRIVS_PIN10_Pos 10 766 #define PORT_PORTM_DRIVS_PIN10_Msk (0x01 << PORT_PORTM_DRIVS_PIN10_Pos) 767 #define PORT_PORTM_DRIVS_PIN11_Pos 11 768 #define PORT_PORTM_DRIVS_PIN11_Msk (0x01 << PORT_PORTM_DRIVS_PIN11_Pos) 769 #define PORT_PORTM_DRIVS_PIN12_Pos 12 770 #define PORT_PORTM_DRIVS_PIN12_Msk (0x01 << PORT_PORTM_DRIVS_PIN12_Pos) 771 #define PORT_PORTM_DRIVS_PIN13_Pos 13 772 #define PORT_PORTM_DRIVS_PIN13_Msk (0x01 << PORT_PORTM_DRIVS_PIN13_Pos) 773 #define PORT_PORTM_DRIVS_PIN14_Pos 14 774 #define PORT_PORTM_DRIVS_PIN14_Msk (0x01 << PORT_PORTM_DRIVS_PIN14_Pos) 775 #define PORT_PORTM_DRIVS_PIN15_Pos 15 776 #define PORT_PORTM_DRIVS_PIN15_Msk (0x01 << PORT_PORTM_DRIVS_PIN15_Pos) 777 #define PORT_PORTM_DRIVS_PIN16_Pos 16 778 #define PORT_PORTM_DRIVS_PIN16_Msk (0x01 << PORT_PORTM_DRIVS_PIN16_Pos) 779 #define PORT_PORTM_DRIVS_PIN17_Pos 17 780 #define PORT_PORTM_DRIVS_PIN17_Msk (0x01 << PORT_PORTM_DRIVS_PIN17_Pos) 781 #define PORT_PORTM_DRIVS_PIN18_Pos 18 782 #define PORT_PORTM_DRIVS_PIN18_Msk (0x01 << PORT_PORTM_DRIVS_PIN18_Pos) 783 #define PORT_PORTM_DRIVS_PIN19_Pos 19 784 #define PORT_PORTM_DRIVS_PIN19_Msk (0x01 << PORT_PORTM_DRIVS_PIN19_Pos) 785 #define PORT_PORTM_DRIVS_PIN20_Pos 20 786 #define PORT_PORTM_DRIVS_PIN20_Msk (0x01 << PORT_PORTM_DRIVS_PIN20_Pos) 787 #define PORT_PORTM_DRIVS_PIN21_Pos 21 788 #define PORT_PORTM_DRIVS_PIN21_Msk (0x01 << PORT_PORTM_DRIVS_PIN21_Pos) 789 #define PORT_PORTM_DRIVS_PIN22_Pos 22 790 #define PORT_PORTM_DRIVS_PIN22_Msk (0x01 << PORT_PORTM_DRIVS_PIN22_Pos) 791 #define PORT_PORTM_DRIVS_PIN23_Pos 23 792 #define PORT_PORTM_DRIVS_PIN23_Msk (0x01 << PORT_PORTM_DRIVS_PIN23_Pos) 793 794 #define PORT_PORTN_DRIVS_PIN0_Pos 0 795 #define PORT_PORTN_DRIVS_PIN0_Msk (0x01 << PORT_PORTN_DRIVS_PIN0_Pos) 796 #define PORT_PORTN_DRIVS_PIN1_Pos 1 797 #define PORT_PORTN_DRIVS_PIN1_Msk (0x01 << PORT_PORTN_DRIVS_PIN1_Pos) 798 #define PORT_PORTN_DRIVS_PIN2_Pos 2 799 #define PORT_PORTN_DRIVS_PIN2_Msk (0x01 << PORT_PORTN_DRIVS_PIN2_Pos) 800 #define PORT_PORTN_DRIVS_PIN3_Pos 3 801 #define PORT_PORTN_DRIVS_PIN3_Msk (0x01 << PORT_PORTN_DRIVS_PIN3_Pos) 802 #define PORT_PORTN_DRIVS_PIN4_Pos 4 803 #define PORT_PORTN_DRIVS_PIN4_Msk (0x01 << PORT_PORTN_DRIVS_PIN4_Pos) 804 #define PORT_PORTN_DRIVS_PIN5_Pos 5 805 #define PORT_PORTN_DRIVS_PIN5_Msk (0x01 << PORT_PORTN_DRIVS_PIN5_Pos) 806 #define PORT_PORTN_DRIVS_PIN6_Pos 6 807 #define PORT_PORTN_DRIVS_PIN6_Msk (0x01 << PORT_PORTN_DRIVS_PIN6_Pos) 808 #define PORT_PORTN_DRIVS_PIN7_Pos 7 809 #define PORT_PORTN_DRIVS_PIN7_Msk (0x01 << PORT_PORTN_DRIVS_PIN7_Pos) 810 #define PORT_PORTN_DRIVS_PIN8_Pos 8 811 #define PORT_PORTN_DRIVS_PIN8_Msk (0x01 << PORT_PORTN_DRIVS_PIN8_Pos) 812 #define PORT_PORTN_DRIVS_PIN9_Pos 9 813 #define PORT_PORTN_DRIVS_PIN9_Msk (0x01 << PORT_PORTN_DRIVS_PIN9_Pos) 814 #define PORT_PORTN_DRIVS_PIN10_Pos 10 815 #define PORT_PORTN_DRIVS_PIN10_Msk (0x01 << PORT_PORTN_DRIVS_PIN10_Pos) 816 #define PORT_PORTN_DRIVS_PIN11_Pos 11 817 #define PORT_PORTN_DRIVS_PIN11_Msk (0x01 << PORT_PORTN_DRIVS_PIN11_Pos) 818 #define PORT_PORTN_DRIVS_PIN12_Pos 12 819 #define PORT_PORTN_DRIVS_PIN12_Msk (0x01 << PORT_PORTN_DRIVS_PIN12_Pos) 820 #define PORT_PORTN_DRIVS_PIN13_Pos 13 821 #define PORT_PORTN_DRIVS_PIN13_Msk (0x01 << PORT_PORTN_DRIVS_PIN13_Pos) 822 #define PORT_PORTN_DRIVS_PIN14_Pos 14 823 #define PORT_PORTN_DRIVS_PIN14_Msk (0x01 << PORT_PORTN_DRIVS_PIN14_Pos) 824 #define PORT_PORTN_DRIVS_PIN15_Pos 15 825 #define PORT_PORTN_DRIVS_PIN15_Msk (0x01 << PORT_PORTN_DRIVS_PIN15_Pos) 826 #define PORT_PORTN_DRIVS_PIN16_Pos 16 827 #define PORT_PORTN_DRIVS_PIN16_Msk (0x01 << PORT_PORTN_DRIVS_PIN16_Pos) 828 #define PORT_PORTN_DRIVS_PIN17_Pos 17 829 #define PORT_PORTN_DRIVS_PIN17_Msk (0x01 << PORT_PORTN_DRIVS_PIN17_Pos) 830 #define PORT_PORTN_DRIVS_PIN18_Pos 18 831 #define PORT_PORTN_DRIVS_PIN18_Msk (0x01 << PORT_PORTN_DRIVS_PIN18_Pos) 832 #define PORT_PORTN_DRIVS_PIN19_Pos 19 833 #define PORT_PORTN_DRIVS_PIN19_Msk (0x01 << PORT_PORTN_DRIVS_PIN19_Pos) 834 #define PORT_PORTN_DRIVS_PIN20_Pos 20 835 #define PORT_PORTN_DRIVS_PIN20_Msk (0x01 << PORT_PORTN_DRIVS_PIN20_Pos) 836 #define PORT_PORTN_DRIVS_PIN21_Pos 21 837 #define PORT_PORTN_DRIVS_PIN21_Msk (0x01 << PORT_PORTN_DRIVS_PIN21_Pos) 838 #define PORT_PORTN_DRIVS_PIN22_Pos 22 839 #define PORT_PORTN_DRIVS_PIN22_Msk (0x01 << PORT_PORTN_DRIVS_PIN22_Pos) 840 #define PORT_PORTN_DRIVS_PIN23_Pos 23 841 #define PORT_PORTN_DRIVS_PIN23_Msk (0x01 << PORT_PORTN_DRIVS_PIN23_Pos) 842 843 #define PORT_PORTP_DRIVS_PIN0_Pos 0 844 #define PORT_PORTP_DRIVS_PIN0_Msk (0x01 << PORT_PORTP_DRIVS_PIN0_Pos) 845 #define PORT_PORTP_DRIVS_PIN1_Pos 1 846 #define PORT_PORTP_DRIVS_PIN1_Msk (0x01 << PORT_PORTP_DRIVS_PIN1_Pos) 847 #define PORT_PORTP_DRIVS_PIN2_Pos 2 848 #define PORT_PORTP_DRIVS_PIN2_Msk (0x01 << PORT_PORTP_DRIVS_PIN2_Pos) 849 #define PORT_PORTP_DRIVS_PIN3_Pos 3 850 #define PORT_PORTP_DRIVS_PIN3_Msk (0x01 << PORT_PORTP_DRIVS_PIN3_Pos) 851 #define PORT_PORTP_DRIVS_PIN4_Pos 4 852 #define PORT_PORTP_DRIVS_PIN4_Msk (0x01 << PORT_PORTP_DRIVS_PIN4_Pos) 853 #define PORT_PORTP_DRIVS_PIN5_Pos 5 854 #define PORT_PORTP_DRIVS_PIN5_Msk (0x01 << PORT_PORTP_DRIVS_PIN5_Pos) 855 #define PORT_PORTP_DRIVS_PIN6_Pos 6 856 #define PORT_PORTP_DRIVS_PIN6_Msk (0x01 << PORT_PORTP_DRIVS_PIN6_Pos) 857 #define PORT_PORTP_DRIVS_PIN7_Pos 7 858 #define PORT_PORTP_DRIVS_PIN7_Msk (0x01 << PORT_PORTP_DRIVS_PIN7_Pos) 859 #define PORT_PORTP_DRIVS_PIN8_Pos 8 860 #define PORT_PORTP_DRIVS_PIN8_Msk (0x01 << PORT_PORTP_DRIVS_PIN8_Pos) 861 #define PORT_PORTP_DRIVS_PIN9_Pos 9 862 #define PORT_PORTP_DRIVS_PIN9_Msk (0x01 << PORT_PORTP_DRIVS_PIN9_Pos) 863 #define PORT_PORTP_DRIVS_PIN10_Pos 10 864 #define PORT_PORTP_DRIVS_PIN10_Msk (0x01 << PORT_PORTP_DRIVS_PIN10_Pos) 865 #define PORT_PORTP_DRIVS_PIN11_Pos 11 866 #define PORT_PORTP_DRIVS_PIN11_Msk (0x01 << PORT_PORTP_DRIVS_PIN11_Pos) 867 #define PORT_PORTP_DRIVS_PIN12_Pos 12 868 #define PORT_PORTP_DRIVS_PIN12_Msk (0x01 << PORT_PORTP_DRIVS_PIN12_Pos) 869 #define PORT_PORTP_DRIVS_PIN13_Pos 13 870 #define PORT_PORTP_DRIVS_PIN13_Msk (0x01 << PORT_PORTP_DRIVS_PIN13_Pos) 871 #define PORT_PORTP_DRIVS_PIN14_Pos 14 872 #define PORT_PORTP_DRIVS_PIN14_Msk (0x01 << PORT_PORTP_DRIVS_PIN14_Pos) 873 #define PORT_PORTP_DRIVS_PIN15_Pos 15 874 #define PORT_PORTP_DRIVS_PIN15_Msk (0x01 << PORT_PORTP_DRIVS_PIN15_Pos) 875 #define PORT_PORTP_DRIVS_PIN16_Pos 16 876 #define PORT_PORTP_DRIVS_PIN16_Msk (0x01 << PORT_PORTP_DRIVS_PIN16_Pos) 877 #define PORT_PORTP_DRIVS_PIN17_Pos 17 878 #define PORT_PORTP_DRIVS_PIN17_Msk (0x01 << PORT_PORTP_DRIVS_PIN17_Pos) 879 #define PORT_PORTP_DRIVS_PIN18_Pos 18 880 #define PORT_PORTP_DRIVS_PIN18_Msk (0x01 << PORT_PORTP_DRIVS_PIN18_Pos) 881 #define PORT_PORTP_DRIVS_PIN19_Pos 19 882 #define PORT_PORTP_DRIVS_PIN19_Msk (0x01 << PORT_PORTP_DRIVS_PIN19_Pos) 883 #define PORT_PORTP_DRIVS_PIN20_Pos 20 884 #define PORT_PORTP_DRIVS_PIN20_Msk (0x01 << PORT_PORTP_DRIVS_PIN20_Pos) 885 #define PORT_PORTP_DRIVS_PIN21_Pos 21 886 #define PORT_PORTP_DRIVS_PIN21_Msk (0x01 << PORT_PORTP_DRIVS_PIN21_Pos) 887 #define PORT_PORTP_DRIVS_PIN22_Pos 22 888 #define PORT_PORTP_DRIVS_PIN22_Msk (0x01 << PORT_PORTP_DRIVS_PIN22_Pos) 889 #define PORT_PORTP_DRIVS_PIN23_Pos 23 890 #define PORT_PORTP_DRIVS_PIN23_Msk (0x01 << PORT_PORTP_DRIVS_PIN23_Pos) 891 892 #define PORT_PORTA_INEN_PIN0_Pos 0 893 #define PORT_PORTA_INEN_PIN0_Msk (0x01 << PORT_PORTA_INEN_PIN0_Pos) 894 #define PORT_PORTA_INEN_PIN1_Pos 1 895 #define PORT_PORTA_INEN_PIN1_Msk (0x01 << PORT_PORTA_INEN_PIN1_Pos) 896 #define PORT_PORTA_INEN_PIN2_Pos 2 897 #define PORT_PORTA_INEN_PIN2_Msk (0x01 << PORT_PORTA_INEN_PIN2_Pos) 898 #define PORT_PORTA_INEN_PIN3_Pos 3 899 #define PORT_PORTA_INEN_PIN3_Msk (0x01 << PORT_PORTA_INEN_PIN3_Pos) 900 #define PORT_PORTA_INEN_PIN4_Pos 4 901 #define PORT_PORTA_INEN_PIN4_Msk (0x01 << PORT_PORTA_INEN_PIN4_Pos) 902 #define PORT_PORTA_INEN_PIN5_Pos 5 903 #define PORT_PORTA_INEN_PIN5_Msk (0x01 << PORT_PORTA_INEN_PIN5_Pos) 904 #define PORT_PORTA_INEN_PIN6_Pos 6 905 #define PORT_PORTA_INEN_PIN6_Msk (0x01 << PORT_PORTA_INEN_PIN6_Pos) 906 #define PORT_PORTA_INEN_PIN7_Pos 7 907 #define PORT_PORTA_INEN_PIN7_Msk (0x01 << PORT_PORTA_INEN_PIN7_Pos) 908 #define PORT_PORTA_INEN_PIN8_Pos 8 909 #define PORT_PORTA_INEN_PIN8_Msk (0x01 << PORT_PORTA_INEN_PIN8_Pos) 910 #define PORT_PORTA_INEN_PIN9_Pos 9 911 #define PORT_PORTA_INEN_PIN9_Msk (0x01 << PORT_PORTA_INEN_PIN9_Pos) 912 #define PORT_PORTA_INEN_PIN10_Pos 10 913 #define PORT_PORTA_INEN_PIN10_Msk (0x01 << PORT_PORTA_INEN_PIN10_Pos) 914 #define PORT_PORTA_INEN_PIN11_Pos 11 915 #define PORT_PORTA_INEN_PIN11_Msk (0x01 << PORT_PORTA_INEN_PIN11_Pos) 916 #define PORT_PORTA_INEN_PIN12_Pos 12 917 #define PORT_PORTA_INEN_PIN12_Msk (0x01 << PORT_PORTA_INEN_PIN12_Pos) 918 #define PORT_PORTA_INEN_PIN13_Pos 13 919 #define PORT_PORTA_INEN_PIN13_Msk (0x01 << PORT_PORTA_INEN_PIN13_Pos) 920 #define PORT_PORTA_INEN_PIN14_Pos 14 921 #define PORT_PORTA_INEN_PIN14_Msk (0x01 << PORT_PORTA_INEN_PIN14_Pos) 922 #define PORT_PORTA_INEN_PIN15_Pos 15 923 #define PORT_PORTA_INEN_PIN15_Msk (0x01 << PORT_PORTA_INEN_PIN15_Pos) 924 925 #define PORT_PORTB_INEN_PIN0_Pos 0 926 #define PORT_PORTB_INEN_PIN0_Msk (0x01 << PORT_PORTB_INEN_PIN0_Pos) 927 #define PORT_PORTB_INEN_PIN1_Pos 1 928 #define PORT_PORTB_INEN_PIN1_Msk (0x01 << PORT_PORTB_INEN_PIN1_Pos) 929 #define PORT_PORTB_INEN_PIN2_Pos 2 930 #define PORT_PORTB_INEN_PIN2_Msk (0x01 << PORT_PORTB_INEN_PIN2_Pos) 931 #define PORT_PORTB_INEN_PIN3_Pos 3 932 #define PORT_PORTB_INEN_PIN3_Msk (0x01 << PORT_PORTB_INEN_PIN3_Pos) 933 #define PORT_PORTB_INEN_PIN4_Pos 4 934 #define PORT_PORTB_INEN_PIN4_Msk (0x01 << PORT_PORTB_INEN_PIN4_Pos) 935 #define PORT_PORTB_INEN_PIN5_Pos 5 936 #define PORT_PORTB_INEN_PIN5_Msk (0x01 << PORT_PORTB_INEN_PIN5_Pos) 937 #define PORT_PORTB_INEN_PIN6_Pos 6 938 #define PORT_PORTB_INEN_PIN6_Msk (0x01 << PORT_PORTB_INEN_PIN6_Pos) 939 #define PORT_PORTB_INEN_PIN7_Pos 7 940 #define PORT_PORTB_INEN_PIN7_Msk (0x01 << PORT_PORTB_INEN_PIN7_Pos) 941 #define PORT_PORTB_INEN_PIN8_Pos 8 942 #define PORT_PORTB_INEN_PIN8_Msk (0x01 << PORT_PORTB_INEN_PIN8_Pos) 943 #define PORT_PORTB_INEN_PIN9_Pos 9 944 #define PORT_PORTB_INEN_PIN9_Msk (0x01 << PORT_PORTB_INEN_PIN9_Pos) 945 #define PORT_PORTB_INEN_PIN10_Pos 10 946 #define PORT_PORTB_INEN_PIN10_Msk (0x01 << PORT_PORTB_INEN_PIN10_Pos) 947 #define PORT_PORTB_INEN_PIN11_Pos 11 948 #define PORT_PORTB_INEN_PIN11_Msk (0x01 << PORT_PORTB_INEN_PIN11_Pos) 949 #define PORT_PORTB_INEN_PIN12_Pos 12 950 #define PORT_PORTB_INEN_PIN12_Msk (0x01 << PORT_PORTB_INEN_PIN12_Pos) 951 #define PORT_PORTB_INEN_PIN13_Pos 13 952 #define PORT_PORTB_INEN_PIN13_Msk (0x01 << PORT_PORTB_INEN_PIN13_Pos) 953 #define PORT_PORTB_INEN_PIN14_Pos 14 954 #define PORT_PORTB_INEN_PIN14_Msk (0x01 << PORT_PORTB_INEN_PIN14_Pos) 955 #define PORT_PORTB_INEN_PIN15_Pos 15 956 #define PORT_PORTB_INEN_PIN15_Msk (0x01 << PORT_PORTB_INEN_PIN15_Pos) 957 958 #define PORT_PORTC_INEN_PIN0_Pos 0 959 #define PORT_PORTC_INEN_PIN0_Msk (0x01 << PORT_PORTC_INEN_PIN0_Pos) 960 #define PORT_PORTC_INEN_PIN1_Pos 1 961 #define PORT_PORTC_INEN_PIN1_Msk (0x01 << PORT_PORTC_INEN_PIN1_Pos) 962 #define PORT_PORTC_INEN_PIN2_Pos 2 963 #define PORT_PORTC_INEN_PIN2_Msk (0x01 << PORT_PORTC_INEN_PIN2_Pos) 964 #define PORT_PORTC_INEN_PIN3_Pos 3 965 #define PORT_PORTC_INEN_PIN3_Msk (0x01 << PORT_PORTC_INEN_PIN3_Pos) 966 #define PORT_PORTC_INEN_PIN4_Pos 4 967 #define PORT_PORTC_INEN_PIN4_Msk (0x01 << PORT_PORTC_INEN_PIN4_Pos) 968 #define PORT_PORTC_INEN_PIN5_Pos 5 969 #define PORT_PORTC_INEN_PIN5_Msk (0x01 << PORT_PORTC_INEN_PIN5_Pos) 970 #define PORT_PORTC_INEN_PIN6_Pos 6 971 #define PORT_PORTC_INEN_PIN6_Msk (0x01 << PORT_PORTC_INEN_PIN6_Pos) 972 #define PORT_PORTC_INEN_PIN7_Pos 7 973 #define PORT_PORTC_INEN_PIN7_Msk (0x01 << PORT_PORTC_INEN_PIN7_Pos) 974 #define PORT_PORTC_INEN_PIN8_Pos 8 975 #define PORT_PORTC_INEN_PIN8_Msk (0x01 << PORT_PORTC_INEN_PIN8_Pos) 976 #define PORT_PORTC_INEN_PIN9_Pos 9 977 #define PORT_PORTC_INEN_PIN9_Msk (0x01 << PORT_PORTC_INEN_PIN9_Pos) 978 #define PORT_PORTC_INEN_PIN10_Pos 10 979 #define PORT_PORTC_INEN_PIN10_Msk (0x01 << PORT_PORTC_INEN_PIN10_Pos) 980 #define PORT_PORTC_INEN_PIN11_Pos 11 981 #define PORT_PORTC_INEN_PIN11_Msk (0x01 << PORT_PORTC_INEN_PIN11_Pos) 982 #define PORT_PORTC_INEN_PIN12_Pos 12 983 #define PORT_PORTC_INEN_PIN12_Msk (0x01 << PORT_PORTC_INEN_PIN12_Pos) 984 #define PORT_PORTC_INEN_PIN13_Pos 13 985 #define PORT_PORTC_INEN_PIN13_Msk (0x01 << PORT_PORTC_INEN_PIN13_Pos) 986 #define PORT_PORTC_INEN_PIN14_Pos 14 987 #define PORT_PORTC_INEN_PIN14_Msk (0x01 << PORT_PORTC_INEN_PIN14_Pos) 988 #define PORT_PORTC_INEN_PIN15_Pos 15 989 #define PORT_PORTC_INEN_PIN15_Msk (0x01 << PORT_PORTC_INEN_PIN15_Pos) 990 991 #define PORT_PORTM_INEN_PIN0_Pos 0 992 #define PORT_PORTM_INEN_PIN0_Msk (0x01 << PORT_PORTM_INEN_PIN0_Pos) 993 #define PORT_PORTM_INEN_PIN1_Pos 1 994 #define PORT_PORTM_INEN_PIN1_Msk (0x01 << PORT_PORTM_INEN_PIN1_Pos) 995 #define PORT_PORTM_INEN_PIN2_Pos 2 996 #define PORT_PORTM_INEN_PIN2_Msk (0x01 << PORT_PORTM_INEN_PIN2_Pos) 997 #define PORT_PORTM_INEN_PIN3_Pos 3 998 #define PORT_PORTM_INEN_PIN3_Msk (0x01 << PORT_PORTM_INEN_PIN3_Pos) 999 #define PORT_PORTM_INEN_PIN4_Pos 4 1000 #define PORT_PORTM_INEN_PIN4_Msk (0x01 << PORT_PORTM_INEN_PIN4_Pos) 1001 #define PORT_PORTM_INEN_PIN5_Pos 5 1002 #define PORT_PORTM_INEN_PIN5_Msk (0x01 << PORT_PORTM_INEN_PIN5_Pos) 1003 #define PORT_PORTM_INEN_PIN6_Pos 6 1004 #define PORT_PORTM_INEN_PIN6_Msk (0x01 << PORT_PORTM_INEN_PIN6_Pos) 1005 #define PORT_PORTM_INEN_PIN7_Pos 7 1006 #define PORT_PORTM_INEN_PIN7_Msk (0x01 << PORT_PORTM_INEN_PIN7_Pos) 1007 #define PORT_PORTM_INEN_PIN8_Pos 8 1008 #define PORT_PORTM_INEN_PIN8_Msk (0x01 << PORT_PORTM_INEN_PIN8_Pos) 1009 #define PORT_PORTM_INEN_PIN9_Pos 9 1010 #define PORT_PORTM_INEN_PIN9_Msk (0x01 << PORT_PORTM_INEN_PIN9_Pos) 1011 #define PORT_PORTM_INEN_PIN10_Pos 10 1012 #define PORT_PORTM_INEN_PIN10_Msk (0x01 << PORT_PORTM_INEN_PIN10_Pos) 1013 #define PORT_PORTM_INEN_PIN11_Pos 11 1014 #define PORT_PORTM_INEN_PIN11_Msk (0x01 << PORT_PORTM_INEN_PIN11_Pos) 1015 #define PORT_PORTM_INEN_PIN12_Pos 12 1016 #define PORT_PORTM_INEN_PIN12_Msk (0x01 << PORT_PORTM_INEN_PIN12_Pos) 1017 #define PORT_PORTM_INEN_PIN13_Pos 13 1018 #define PORT_PORTM_INEN_PIN13_Msk (0x01 << PORT_PORTM_INEN_PIN13_Pos) 1019 #define PORT_PORTM_INEN_PIN14_Pos 14 1020 #define PORT_PORTM_INEN_PIN14_Msk (0x01 << PORT_PORTM_INEN_PIN14_Pos) 1021 #define PORT_PORTM_INEN_PIN15_Pos 15 1022 #define PORT_PORTM_INEN_PIN15_Msk (0x01 << PORT_PORTM_INEN_PIN15_Pos) 1023 #define PORT_PORTM_INEN_PIN16_Pos 16 1024 #define PORT_PORTM_INEN_PIN16_Msk (0x01 << PORT_PORTM_INEN_PIN16_Pos) 1025 #define PORT_PORTM_INEN_PIN17_Pos 17 1026 #define PORT_PORTM_INEN_PIN17_Msk (0x01 << PORT_PORTM_INEN_PIN17_Pos) 1027 #define PORT_PORTM_INEN_PIN18_Pos 18 1028 #define PORT_PORTM_INEN_PIN18_Msk (0x01 << PORT_PORTM_INEN_PIN18_Pos) 1029 #define PORT_PORTM_INEN_PIN19_Pos 19 1030 #define PORT_PORTM_INEN_PIN19_Msk (0x01 << PORT_PORTM_INEN_PIN19_Pos) 1031 #define PORT_PORTM_INEN_PIN20_Pos 20 1032 #define PORT_PORTM_INEN_PIN20_Msk (0x01 << PORT_PORTM_INEN_PIN20_Pos) 1033 #define PORT_PORTM_INEN_PIN21_Pos 21 1034 #define PORT_PORTM_INEN_PIN21_Msk (0x01 << PORT_PORTM_INEN_PIN21_Pos) 1035 #define PORT_PORTM_INEN_PIN22_Pos 22 1036 #define PORT_PORTM_INEN_PIN22_Msk (0x01 << PORT_PORTM_INEN_PIN22_Pos) 1037 #define PORT_PORTM_INEN_PIN23_Pos 23 1038 #define PORT_PORTM_INEN_PIN23_Msk (0x01 << PORT_PORTM_INEN_PIN23_Pos) 1039 1040 #define PORT_PORTN_INEN_PIN0_Pos 0 1041 #define PORT_PORTN_INEN_PIN0_Msk (0x01 << PORT_PORTN_INEN_PIN0_Pos) 1042 #define PORT_PORTN_INEN_PIN1_Pos 1 1043 #define PORT_PORTN_INEN_PIN1_Msk (0x01 << PORT_PORTN_INEN_PIN1_Pos) 1044 #define PORT_PORTN_INEN_PIN2_Pos 2 1045 #define PORT_PORTN_INEN_PIN2_Msk (0x01 << PORT_PORTN_INEN_PIN2_Pos) 1046 #define PORT_PORTN_INEN_PIN3_Pos 3 1047 #define PORT_PORTN_INEN_PIN3_Msk (0x01 << PORT_PORTN_INEN_PIN3_Pos) 1048 #define PORT_PORTN_INEN_PIN4_Pos 4 1049 #define PORT_PORTN_INEN_PIN4_Msk (0x01 << PORT_PORTN_INEN_PIN4_Pos) 1050 #define PORT_PORTN_INEN_PIN5_Pos 5 1051 #define PORT_PORTN_INEN_PIN5_Msk (0x01 << PORT_PORTN_INEN_PIN5_Pos) 1052 #define PORT_PORTN_INEN_PIN6_Pos 6 1053 #define PORT_PORTN_INEN_PIN6_Msk (0x01 << PORT_PORTN_INEN_PIN6_Pos) 1054 #define PORT_PORTN_INEN_PIN7_Pos 7 1055 #define PORT_PORTN_INEN_PIN7_Msk (0x01 << PORT_PORTN_INEN_PIN7_Pos) 1056 #define PORT_PORTN_INEN_PIN8_Pos 8 1057 #define PORT_PORTN_INEN_PIN8_Msk (0x01 << PORT_PORTN_INEN_PIN8_Pos) 1058 #define PORT_PORTN_INEN_PIN9_Pos 9 1059 #define PORT_PORTN_INEN_PIN9_Msk (0x01 << PORT_PORTN_INEN_PIN9_Pos) 1060 #define PORT_PORTN_INEN_PIN10_Pos 10 1061 #define PORT_PORTN_INEN_PIN10_Msk (0x01 << PORT_PORTN_INEN_PIN10_Pos) 1062 #define PORT_PORTN_INEN_PIN11_Pos 11 1063 #define PORT_PORTN_INEN_PIN11_Msk (0x01 << PORT_PORTN_INEN_PIN11_Pos) 1064 #define PORT_PORTN_INEN_PIN12_Pos 12 1065 #define PORT_PORTN_INEN_PIN12_Msk (0x01 << PORT_PORTN_INEN_PIN12_Pos) 1066 #define PORT_PORTN_INEN_PIN13_Pos 13 1067 #define PORT_PORTN_INEN_PIN13_Msk (0x01 << PORT_PORTN_INEN_PIN13_Pos) 1068 #define PORT_PORTN_INEN_PIN14_Pos 14 1069 #define PORT_PORTN_INEN_PIN14_Msk (0x01 << PORT_PORTN_INEN_PIN14_Pos) 1070 #define PORT_PORTN_INEN_PIN15_Pos 15 1071 #define PORT_PORTN_INEN_PIN15_Msk (0x01 << PORT_PORTN_INEN_PIN15_Pos) 1072 #define PORT_PORTN_INEN_PIN16_Pos 16 1073 #define PORT_PORTN_INEN_PIN16_Msk (0x01 << PORT_PORTN_INEN_PIN16_Pos) 1074 #define PORT_PORTN_INEN_PIN17_Pos 17 1075 #define PORT_PORTN_INEN_PIN17_Msk (0x01 << PORT_PORTN_INEN_PIN17_Pos) 1076 #define PORT_PORTN_INEN_PIN18_Pos 18 1077 #define PORT_PORTN_INEN_PIN18_Msk (0x01 << PORT_PORTN_INEN_PIN18_Pos) 1078 #define PORT_PORTN_INEN_PIN19_Pos 19 1079 #define PORT_PORTN_INEN_PIN19_Msk (0x01 << PORT_PORTN_INEN_PIN19_Pos) 1080 #define PORT_PORTN_INEN_PIN20_Pos 20 1081 #define PORT_PORTN_INEN_PIN20_Msk (0x01 << PORT_PORTN_INEN_PIN20_Pos) 1082 #define PORT_PORTN_INEN_PIN21_Pos 21 1083 #define PORT_PORTN_INEN_PIN21_Msk (0x01 << PORT_PORTN_INEN_PIN21_Pos) 1084 #define PORT_PORTN_INEN_PIN22_Pos 22 1085 #define PORT_PORTN_INEN_PIN22_Msk (0x01 << PORT_PORTN_INEN_PIN22_Pos) 1086 #define PORT_PORTN_INEN_PIN23_Pos 23 1087 #define PORT_PORTN_INEN_PIN23_Msk (0x01 << PORT_PORTN_INEN_PIN23_Pos) 1088 1089 #define PORT_PORTP_INEN_PIN0_Pos 0 1090 #define PORT_PORTP_INEN_PIN0_Msk (0x01 << PORT_PORTP_INEN_PIN0_Pos) 1091 #define PORT_PORTP_INEN_PIN1_Pos 1 1092 #define PORT_PORTP_INEN_PIN1_Msk (0x01 << PORT_PORTP_INEN_PIN1_Pos) 1093 #define PORT_PORTP_INEN_PIN2_Pos 2 1094 #define PORT_PORTP_INEN_PIN2_Msk (0x01 << PORT_PORTP_INEN_PIN2_Pos) 1095 #define PORT_PORTP_INEN_PIN3_Pos 3 1096 #define PORT_PORTP_INEN_PIN3_Msk (0x01 << PORT_PORTP_INEN_PIN3_Pos) 1097 #define PORT_PORTP_INEN_PIN4_Pos 4 1098 #define PORT_PORTP_INEN_PIN4_Msk (0x01 << PORT_PORTP_INEN_PIN4_Pos) 1099 #define PORT_PORTP_INEN_PIN5_Pos 5 1100 #define PORT_PORTP_INEN_PIN5_Msk (0x01 << PORT_PORTP_INEN_PIN5_Pos) 1101 #define PORT_PORTP_INEN_PIN6_Pos 6 1102 #define PORT_PORTP_INEN_PIN6_Msk (0x01 << PORT_PORTP_INEN_PIN6_Pos) 1103 #define PORT_PORTP_INEN_PIN7_Pos 7 1104 #define PORT_PORTP_INEN_PIN7_Msk (0x01 << PORT_PORTP_INEN_PIN7_Pos) 1105 #define PORT_PORTP_INEN_PIN8_Pos 8 1106 #define PORT_PORTP_INEN_PIN8_Msk (0x01 << PORT_PORTP_INEN_PIN8_Pos) 1107 #define PORT_PORTP_INEN_PIN9_Pos 9 1108 #define PORT_PORTP_INEN_PIN9_Msk (0x01 << PORT_PORTP_INEN_PIN9_Pos) 1109 #define PORT_PORTP_INEN_PIN10_Pos 10 1110 #define PORT_PORTP_INEN_PIN10_Msk (0x01 << PORT_PORTP_INEN_PIN10_Pos) 1111 #define PORT_PORTP_INEN_PIN11_Pos 11 1112 #define PORT_PORTP_INEN_PIN11_Msk (0x01 << PORT_PORTP_INEN_PIN11_Pos) 1113 #define PORT_PORTP_INEN_PIN12_Pos 12 1114 #define PORT_PORTP_INEN_PIN12_Msk (0x01 << PORT_PORTP_INEN_PIN12_Pos) 1115 #define PORT_PORTP_INEN_PIN13_Pos 13 1116 #define PORT_PORTP_INEN_PIN13_Msk (0x01 << PORT_PORTP_INEN_PIN13_Pos) 1117 #define PORT_PORTP_INEN_PIN14_Pos 14 1118 #define PORT_PORTP_INEN_PIN14_Msk (0x01 << PORT_PORTP_INEN_PIN14_Pos) 1119 #define PORT_PORTP_INEN_PIN15_Pos 15 1120 #define PORT_PORTP_INEN_PIN15_Msk (0x01 << PORT_PORTP_INEN_PIN15_Pos) 1121 #define PORT_PORTP_INEN_PIN16_Pos 16 1122 #define PORT_PORTP_INEN_PIN16_Msk (0x01 << PORT_PORTP_INEN_PIN16_Pos) 1123 #define PORT_PORTP_INEN_PIN17_Pos 17 1124 #define PORT_PORTP_INEN_PIN17_Msk (0x01 << PORT_PORTP_INEN_PIN17_Pos) 1125 #define PORT_PORTP_INEN_PIN18_Pos 18 1126 #define PORT_PORTP_INEN_PIN18_Msk (0x01 << PORT_PORTP_INEN_PIN18_Pos) 1127 #define PORT_PORTP_INEN_PIN19_Pos 19 1128 #define PORT_PORTP_INEN_PIN19_Msk (0x01 << PORT_PORTP_INEN_PIN19_Pos) 1129 #define PORT_PORTP_INEN_PIN20_Pos 20 1130 #define PORT_PORTP_INEN_PIN20_Msk (0x01 << PORT_PORTP_INEN_PIN20_Pos) 1131 #define PORT_PORTP_INEN_PIN21_Pos 21 1132 #define PORT_PORTP_INEN_PIN21_Msk (0x01 << PORT_PORTP_INEN_PIN21_Pos) 1133 #define PORT_PORTP_INEN_PIN22_Pos 22 1134 #define PORT_PORTP_INEN_PIN22_Msk (0x01 << PORT_PORTP_INEN_PIN22_Pos) 1135 #define PORT_PORTP_INEN_PIN23_Pos 23 1136 #define PORT_PORTP_INEN_PIN23_Msk (0x01 << PORT_PORTP_INEN_PIN23_Pos) 1137 1138 1139 1140 1141 typedef struct { 1142 __IO uint32_t DATA; 1143 #define PIN0 0 1144 #define PIN1 1 1145 #define PIN2 2 1146 #define PIN3 3 1147 #define PIN4 4 1148 #define PIN5 5 1149 #define PIN6 6 1150 #define PIN7 7 1151 #define PIN8 8 1152 #define PIN9 9 1153 #define PIN10 10 1154 #define PIN11 11 1155 #define PIN12 12 1156 #define PIN13 13 1157 #define PIN14 14 1158 #define PIN15 15 1159 #define PIN16 16 1160 #define PIN17 17 1161 #define PIN18 18 1162 #define PIN19 19 1163 #define PIN20 20 1164 #define PIN21 21 1165 #define PIN22 22 1166 #define PIN23 23 1167 #define PIN24 24 1168 1169 __IO uint32_t DIR; //0 输入 1 输出 1170 1171 __IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 电平触发中断 0 边沿触发中断 1172 1173 __IO uint32_t INTBE; //Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择 1174 1175 __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 上升沿/高电平触发中断 0 下降沿/低电平触发中断 1176 1177 __IO uint32_t INTEN; //1 中断使能 0 中断禁止 1178 1179 __IO uint32_t INTRAWSTAT; //中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件 0 没有检测到中断触发条件 1180 1181 __IO uint32_t INTSTAT; //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0 1182 1183 __IO uint32_t INTCLR; //写1清除中断标志，只对边沿触发中断有用 1184 } GPIO_TypeDef; 1185 1186 1187 1188 1189 typedef struct { 1190 __IO uint32_t LDVAL; //定时器加载值，使能后定时器从此数值开始向下递减计数 1191 1192 __I uint32_t CVAL; //定时器当前值，LDVAL-CVAL 可计算出计时时长 1193 1194 __IO uint32_t CTRL; 1195 } TIMR_TypeDef; 1196 1197 1198 #define TIMR_CTRL_EN_Pos 0 //此位赋1导致TIMR从LDVAL开始向下递减计数 1199 #define TIMR_CTRL_EN_Msk (0x01 << TIMR_CTRL_EN_Pos) 1200 #define TIMR_CTRL_CLKSRC_Pos 1 //时钟源：0 内部系统时钟 1 外部引脚脉冲计数 1201 #define TIMR_CTRL_CLKSRC_Msk (0x01 << TIMR_CTRL_CLKSRC_Pos) 1202 #define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRx的计数时钟为TIMRx-1的溢出信号 1203 #define TIMR_CTRL_CASCADE_Msk (0x01 << TIMR_CTRL_CASCADE_Pos) 1204 1205 1206 typedef struct { 1207 __IO uint32_t PCTRL; //Pulse Control，脉宽测量模块控制寄存器 1208 1209 __I uint32_t PCVAL; //脉宽测量定时器当前值 1210 1211 uint32_t RESERVED[2]; 1212 1213 __IO uint32_t IE; 1214 1215 __IO uint32_t IF; 1216 1217 __IO uint32_t HALT; 1218 } TIMRG_TypeDef; 1219 1220 1221 #define TIMRG_PCTRL_EN_Pos 0 //开始测量脉宽，脉宽内32位计数器从0开始向上计数 1222 #define TIMRG_PCTRL_EN_Msk (0x01 << TIMRG_PCTRL_EN_Pos) 1223 #define TIMRG_PCTRL_HIGH_Pos 1 //0 测量低电平长度 1 测量高电平长度 1224 #define TIMRG_PCTRL_HIGH_Msk (0x01 << TIMRG_PCTRL_HIGH_Pos) 1225 #define TIMRG_PCTRL_CLKSRC_Pos 2 //时钟源：0 内部系统时钟 1 脉宽测量模块变成一个计数器，不再具有脉宽测量功能 1226 #define TIMRG_PCTRL_CLKSRC_Msk (0x01 << TIMRG_PCTRL_CLKSRC_Pos) 1227 1228 #define TIMRG_IE_TIMR0_Pos 0 1229 #define TIMRG_IE_TIMR0_Msk (0x01 << TIMRG_IE_TIMR0_Pos) 1230 #define TIMRG_IE_TIMR1_Pos 1 1231 #define TIMRG_IE_TIMR1_Msk (0x01 << TIMRG_IE_TIMR1_Pos) 1232 #define TIMRG_IE_TIMR2_Pos 2 1233 #define TIMRG_IE_TIMR2_Msk (0x01 << TIMRG_IE_TIMR2_Pos) 1234 #define TIMRG_IE_TIMR3_Pos 3 1235 #define TIMRG_IE_TIMR3_Msk (0x01 << TIMRG_IE_TIMR3_Pos) 1236 #define TIMRG_IE_TIMR4_Pos 4 1237 #define TIMRG_IE_TIMR4_Msk (0x01 << TIMRG_IE_TIMR4_Pos) 1238 #define TIMRG_IE_TIMR5_Pos 5 1239 #define TIMRG_IE_TIMR5_Msk (0x01 << TIMRG_IE_TIMR5_Pos) 1240 #define TIMRG_IE_PULSE_Pos 16 1241 #define TIMRG_IE_PULSE_Msk (0x01 << TIMRG_IE_PULSE_Pos) 1242 1243 #define TIMRG_IF_TIMR0_Pos 0 //写1清零 1244 #define TIMRG_IF_TIMR0_Msk (0x01 << TIMRG_IF_TIMR0_Pos) 1245 #define TIMRG_IF_TIMR1_Pos 1 1246 #define TIMRG_IF_TIMR1_Msk (0x01 << TIMRG_IF_TIMR1_Pos) 1247 #define TIMRG_IF_TIMR2_Pos 2 1248 #define TIMRG_IF_TIMR2_Msk (0x01 << TIMRG_IF_TIMR2_Pos) 1249 #define TIMRG_IF_TIMR3_Pos 3 1250 #define TIMRG_IF_TIMR3_Msk (0x01 << TIMRG_IF_TIMR3_Pos) 1251 #define TIMRG_IF_TIMR4_Pos 4 1252 #define TIMRG_IF_TIMR4_Msk (0x01 << TIMRG_IF_TIMR4_Pos) 1253 #define TIMRG_IF_TIMR5_Pos 5 1254 #define TIMRG_IF_TIMR5_Msk (0x01 << TIMRG_IF_TIMR5_Pos) 1255 #define TIMRG_IF_PULSE_Pos 16 1256 #define TIMRG_IF_PULSE_Msk (0x01 << TIMRG_IF_PULSE_Pos) 1257 1258 #define TIMRG_HALT_TIMR0_Pos 0 //1 暂停计数 1259 #define TIMRG_HALT_TIMR0_Msk (0x01 << TIMRG_HALT_TIMR0_Pos) 1260 #define TIMRG_HALT_TIMR1_Pos 1 1261 #define TIMRG_HALT_TIMR1_Msk (0x01 << TIMRG_HALT_TIMR1_Pos) 1262 #define TIMRG_HALT_TIMR2_Pos 2 1263 #define TIMRG_HALT_TIMR2_Msk (0x01 << TIMRG_HALT_TIMR2_Pos) 1264 #define TIMRG_HALT_TIMR3_Pos 3 1265 #define TIMRG_HALT_TIMR3_Msk (0x01 << TIMRG_HALT_TIMR3_Pos) 1266 #define TIMRG_HALT_TIMR4_Pos 4 1267 #define TIMRG_HALT_TIMR4_Msk (0x01 << TIMRG_HALT_TIMR4_Pos) 1268 #define TIMRG_HALT_TIMR5_Pos 5 1269 #define TIMRG_HALT_TIMR5_Msk (0x01 << TIMRG_HALT_TIMR5_Pos) 1270 1271 1272 1273 1274 typedef struct { 1275 __IO uint32_t DATA; 1276 1277 __IO uint32_t CTRL; 1278 1279 __IO uint32_t BAUD; 1280 1281 __IO uint32_t FIFO; 1282 1283 __IO uint32_t LINCR; 1284 1285 union { 1286 __IO uint32_t CTSCR; 1287 1288 __IO uint32_t RTSCR; 1289 }; 1290 } UART_TypeDef; 1291 1292 1293 #define UART_DATA_DATA_Pos 0 1294 #define UART_DATA_DATA_Msk (0x1FF << UART_DATA_DATA_Pos) 1295 #define UART_DATA_VALID_Pos 9 //当DATA字段有有效的接收数据时，该位硬件置1，读取数据后自动清零 1296 #define UART_DATA_VALID_Msk (0x01 << UART_DATA_VALID_Pos) 1297 #define UART_DATA_PAERR_Pos 10 //Parity Error 1298 #define UART_DATA_PAERR_Msk (0x01 << UART_DATA_PAERR_Pos) 1299 1300 #define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 正在发送数据 1 空闲状态，没有数据发送 1301 #define UART_CTRL_TXIDLE_Msk (0x01 << UART_CTRL_TXIDLE_Pos) 1302 #define UART_CTRL_TXFF_Pos 1 //TX FIFO Full 1303 #define UART_CTRL_TXFF_Msk (0x01 << UART_CTRL_TXFF_Pos) 1304 #define UART_CTRL_TXIE_Pos 2 //TX 中断使能: 1 TX FF 中数据少于设定个数时产生中断 1305 #define UART_CTRL_TXIE_Msk (0x01 << UART_CTRL_TXIE_Pos) 1306 #define UART_CTRL_RXNE_Pos 3 //RX FIFO Not Empty 1307 #define UART_CTRL_RXNE_Msk (0x01 << UART_CTRL_RXNE_Pos) 1308 #define UART_CTRL_RXIE_Pos 4 //RX 中断使能: 1 RX FF 中数据达到设定个数时产生中断 1309 #define UART_CTRL_RXIE_Msk (0x01 << UART_CTRL_RXIE_Pos) 1310 #define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflow，写1清零 1311 #define UART_CTRL_RXOV_Msk (0x01 << UART_CTRL_RXOV_Pos) 1312 #define UART_CTRL_TXDOIE_Pos 6 //TX Done 中断使能，发送FIFO空且发送发送移位寄存器已将最后一位发送出去 1313 #define UART_CTRL_TXDOIE_Msk (0x01 << UART_CTRL_TXDOIE_Pos) 1314 #define UART_CTRL_EN_Pos 9 1315 #define UART_CTRL_EN_Msk (0x01 << UART_CTRL_EN_Pos) 1316 #define UART_CTRL_LOOP_Pos 10 1317 #define UART_CTRL_LOOP_Msk (0x01 << UART_CTRL_LOOP_Pos) 1318 #define UART_CTRL_BAUDEN_Pos 13 //必须写1 1319 #define UART_CTRL_BAUDEN_Msk (0x01 << UART_CTRL_BAUDEN_Pos) 1320 #define UART_CTRL_TOIE_Pos 14 //TimeOut 中断使能，接收到上个字符后，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据 1321 #define UART_CTRL_TOIE_Msk (0x01 << UART_CTRL_TOIE_Pos) 1322 #define UART_CTRL_BRKDET_Pos 15 //LIN Break Detect，检测到LIN Break，即RX线上检测到连续11位低电平 1323 #define UART_CTRL_BRKDET_Msk (0x01 << UART_CTRL_BRKDET_Pos) 1324 #define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect 中断使能 1325 #define UART_CTRL_BRKIE_Msk (0x01 << UART_CTRL_BRKIE_Pos) 1326 #define UART_CTRL_GENBRK_Pos 17 //Generate LIN Break，发送LIN Break 1327 #define UART_CTRL_GENBRK_Msk (0x01 << UART_CTRL_GENBRK_Pos) 1328 #define UART_CTRL_DATA9b_Pos 18 //1 9位数据位 0 8位数据位 1329 #define UART_CTRL_DATA9b_Msk (0x01 << UART_CTRL_DATA9b_Pos) 1330 #define UART_CTRL_PARITY_Pos 19 //000 无校验 001 奇校验 011 偶校验 101 固定为1 111 固定为0 1331 #define UART_CTRL_PARITY_Msk (0x07 << UART_CTRL_PARITY_Pos) 1332 #define UART_CTRL_STOP2b_Pos 22 //1 2位停止位 0 1位停止位 1333 #define UART_CTRL_STOP2b_Msk (0x03 << UART_CTRL_STOP2b_Pos) 1334 #define UART_CTRL_TOTIME_Pos 24 //TimeOut 时长 = TOTIME/(BAUDRAUD/10) 秒 1335 #define UART_CTRL_TOTIME_Msk (0xFFu<< UART_CTRL_TOTIME_Pos) 1336 1337 #define UART_BAUD_BAUD_Pos 0 //串口波特率 = SYS_Freq/16/BAUD - 1 1338 #define UART_BAUD_BAUD_Msk (0x3FFF << UART_BAUD_BAUD_Pos) 1339 #define UART_BAUD_TXD_Pos 14 //通过此位可直接读取串口TXD引脚上的电平 1340 #define UART_BAUD_TXD_Msk (0x01 << UART_BAUD_TXD_Pos) 1341 #define UART_BAUD_RXD_Pos 15 //通过此位可直接读取串口RXD引脚上的电平 1342 #define UART_BAUD_RXD_Msk (0x01 << UART_BAUD_RXD_Pos) 1343 #define UART_BAUD_RXTOIF_Pos 16 //接收&超时的中断标志 = RXIF | TOIF 1344 #define UART_BAUD_RXTOIF_Msk (0x01 << UART_BAUD_RXTOIF_Pos) 1345 #define UART_BAUD_TXIF_Pos 17 //发送中断标志 = TXTHRF & TXIE 1346 #define UART_BAUD_TXIF_Msk (0x01 << UART_BAUD_TXIF_Pos) 1347 #define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect 中断标志，检测到LIN Break时若BRKIE=1，此位由硬件置位 1348 #define UART_BAUD_BRKIF_Msk (0x01 << UART_BAUD_BRKIF_Pos) 1349 #define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flag，RX FIFO中数据达到设定个数（RXLVL >= RXTHR）时硬件置1 1350 #define UART_BAUD_RXTHRF_Msk (0x01 << UART_BAUD_RXTHRF_Pos) 1351 #define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flag，TX FIFO中数据少于设定个数（TXLVL <= TXTHR）时硬件置1 1352 #define UART_BAUD_TXTHRF_Msk (0x01 << UART_BAUD_TXTHRF_Pos) 1353 #define UART_BAUD_TOIF_Pos 21 //TimeOut 中断标志，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据时若TOIE=1，此位由硬件置位 1354 #define UART_BAUD_TOIF_Msk (0x01 << UART_BAUD_TOIF_Pos) 1355 #define UART_BAUD_RXIF_Pos 22 //接收中断标志 = RXTHRF & RXIE 1356 #define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos) 1357 #define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable，写1启动自动波特率校准，完成后自动清零 1358 #define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos) 1359 #define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位 脉宽计算波特率，要求发送端发送0xFF 1360 // 1 2位，通过测起始位加1位数据位脉宽计算波特率，要求发送端发送0xFE 1361 // 1 4位，通过测起始位加3位数据位脉宽计算波特率，要求发送端发送0xF8 1362 // 1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80 1363 #define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos) 1364 #define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error，0 自动波特率校准成功 1 自动波特率校准失败 1365 #define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos) 1366 #define UART_BAUD_TXDOIF_Pos 27 //TX Done 中断标志，发送FIFO空且发送发送移位寄存器已将最后一位发送出去 1367 #define UART_BAUD_TXDOIF_Msk (0x01 << UART_BAUD_TXDOIF_Pos) 1368 1369 #define UART_FIFO_RXLVL_Pos 0 //RX FIFO Level，RX FIFO 中字符个数 1370 #define UART_FIFO_RXLVL_Msk (0xFF << UART_FIFO_RXLVL_Pos) 1371 #define UART_FIFO_TXLVL_Pos 8 //TX FIFO Level，TX FIFO 中字符个数 1372 #define UART_FIFO_TXLVL_Msk (0xFF << UART_FIFO_TXLVL_Pos) 1373 #define UART_FIFO_RXTHR_Pos 16 //RX FIFO Threshold，RX中断触发门限，中断使能时 RXLVL >= RXTHR 触发RX中断 1374 #define UART_FIFO_RXTHR_Msk (0xFF << UART_FIFO_RXTHR_Pos) 1375 #define UART_FIFO_TXTHR_Pos 24 //TX FIFO Threshold，TX中断触发门限，中断使能时 TXLVL <= TXTHR 触发TX中断 1376 #define UART_FIFO_TXTHR_Msk (0xFFu<< UART_FIFO_TXTHR_Pos) 1377 1378 #define UART_LINCR_BRKDETIE_Pos 0 //检测到LIN Break中断使能 1379 #define UART_LINCR_BRKDETIE_Msk (0x01 << UART_LINCR_BRKDETIE_Pos) 1380 #define UART_LINCR_BRKDETIF_Pos 1 //检测到LIN Break中断状态 1381 #define UART_LINCR_BRKDETIF_Msk (0x01 << UART_LINCR_BRKDETIF_Pos) 1382 #define UART_LINCR_GENBRKIE_Pos 2 //发送LIN Break完成中断使能 1383 #define UART_LINCR_GENBRKIE_Msk (0x01 << UART_LINCR_GENBRKIE_Pos) 1384 #define UART_LINCR_GENBRKIF_Pos 3 //发送LIN Break完成中断状态 1385 #define UART_LINCR_GENBRKIF_Msk (0x01 << UART_LINCR_GENBRKIF_Pos) 1386 #define UART_LINCR_GENBRK_Pos 4 //发送LIN Break，发送完成自动清零 1387 #define UART_LINCR_GENBRK_Msk (0x01 << UART_LINCR_GENBRK_Pos) 1388 1389 #define UART_CTSCR_EN_Pos 0 //CTS流控使能 1390 #define UART_CTSCR_EN_Msk (0x01 << UART_CTSCR_EN_Pos) 1391 #define UART_CTSCR_POL_Pos 2 //CTS信号极性，0 低有效，CTS输入为低表示可以发送数据 1392 #define UART_CTSCR_POL_Msk (0x01 << UART_CTSCR_POL_Pos) 1393 #define UART_CTSCR_STAT_Pos 7 //CTS信号的当前状态 1394 #define UART_CTSCR_STAT_Msk (0x01 << UART_CTSCR_STAT_Pos) 1395 1396 #define UART_RTSCR_EN_Pos 1 //RTS流控使能 1397 #define UART_RTSCR_EN_Msk (0x01 << UART_RTSCR_EN_Pos) 1398 #define UART_RTSCR_POL_Pos 3 //RTS信号极性 0 低有效，RTS输入为低表示可以接收数据 1399 #define UART_RTSCR_POL_Msk (0x01 << UART_RTSCR_POL_Pos) 1400 #define UART_RTSCR_THR_Pos 4 //RTS流控的触发阈值 0 1字节 1 2字节 2 4字节 3 6字节 1401 #define UART_RTSCR_THR_Msk (0x07 << UART_RTSCR_THR_Pos) 1402 #define UART_RTSCR_STAT_Pos 8 //RTS信号的当前状态 1403 #define UART_RTSCR_STAT_Msk (0x01 << UART_RTSCR_STAT_Pos) 1404 1405 1406 1407 1408 typedef struct { 1409 __IO uint32_t CTRL; 1410 1411 __IO uint32_t DATA; 1412 1413 __IO uint32_t STAT; 1414 1415 __IO uint32_t IE; 1416 1417 __IO uint32_t IF; 1418 } SPI_TypeDef; 1419 1420 1421 #define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPI工作时钟 = SYS_Freq/pow(2, CLKDIV+2) 1422 #define SPI_CTRL_CLKDIV_Msk (0x07 << SPI_CTRL_CLKDIV_Pos) 1423 #define SPI_CTRL_EN_Pos 3 1424 #define SPI_CTRL_EN_Msk (0x01 << SPI_CTRL_EN_Pos) 1425 #define SPI_CTRL_SIZE_Pos 4 //Data Size Select, 取值3--15，表示4--16位 1426 #define SPI_CTRL_SIZE_Msk (0x0F << SPI_CTRL_SIZE_Pos) 1427 #define SPI_CTRL_CPHA_Pos 8 //0 在SCLK的第一个跳变沿采样数据 1 在SCLK的第二个跳变沿采样数据 1428 #define SPI_CTRL_CPHA_Msk (0x01 << SPI_CTRL_CPHA_Pos) 1429 #define SPI_CTRL_CPOL_Pos 9 //0 空闲状态下SCLK为低电平 1 空闲状态下SCLK为高电平 1430 #define SPI_CTRL_CPOL_Msk (0x01 << SPI_CTRL_CPOL_Pos) 1431 #define SPI_CTRL_FFS_Pos 10 //Frame Format Select, 0 SPI 1 TI SSI 2 SPI 3 SPI 1432 #define SPI_CTRL_FFS_Msk (0x03 << SPI_CTRL_FFS_Pos) 1433 #define SPI_CTRL_MSTR_Pos 12 //Master, 1 主模式 0 从模式 1434 #define SPI_CTRL_MSTR_Msk (0x01 << SPI_CTRL_MSTR_Pos) 1435 #define SPI_CTRL_FAST_Pos 13 //1 SPI工作时钟 = SYS_Freq/2 0 SPI工作时钟由SPI->CTRL.CLKDIV设置 1436 #define SPI_CTRL_FAST_Msk (0x01 << SPI_CTRL_FAST_Pos) 1437 #define SPI_CTRL_FILTE_Pos 16 //1 对SPI输入信号进行去抖操作 0 对SPI输入信号不进行去抖操作 1438 #define SPI_CTRL_FILTE_Msk (0x01 << SPI_CTRL_FILTE_Pos) 1439 #define SPI_CTRL_SSN_H_Pos 17 //0 传输过程中SSN始终为0 1 传输过程中每字符之间会将SSN拉高半个SCLK周期 1440 #define SPI_CTRL_SSN_H_Msk (0x01 << SPI_CTRL_SSN_H_Pos) 1441 #define SPI_CTRL_TFCLR_Pos 24 //TX FIFO Clear 1442 #define SPI_CTRL_TFCLR_Msk (0x01 << SPI_CTRL_TFCLR_Pos) 1443 #define SPI_CTRL_RFCLR_Pos 25 //RX FIFO Clear 1444 #define SPI_CTRL_RFCLR_Msk (0x01 << SPI_CTRL_RFCLR_Pos) 1445 1446 #define SPI_STAT_WTC_Pos 0 //Word Transmit Complete，每传输完成一个数据字由硬件置1，软件写1清零 1447 #define SPI_STAT_WTC_Msk (0x01 << SPI_STAT_WTC_Pos) 1448 #define SPI_STAT_TFE_Pos 1 //发送FIFO Empty 1449 #define SPI_STAT_TFE_Msk (0x01 << SPI_STAT_TFE_Pos) 1450 #define SPI_STAT_TFNF_Pos 2 //发送FIFO Not Full 1451 #define SPI_STAT_TFNF_Msk (0x01 << SPI_STAT_TFNF_Pos) 1452 #define SPI_STAT_RFNE_Pos 3 //接收FIFO Not Empty 1453 #define SPI_STAT_RFNE_Msk (0x01 << SPI_STAT_RFNE_Pos) 1454 #define SPI_STAT_RFF_Pos 4 //接收FIFO Full 1455 #define SPI_STAT_RFF_Msk (0x01 << SPI_STAT_RFF_Pos) 1456 #define SPI_STAT_RFOVF_Pos 5 //接收FIFO Overflow 1457 #define SPI_STAT_RFOVF_Msk (0x01 << SPI_STAT_RFOVF_Pos) 1458 #define SPI_STAT_TFLVL_Pos 6 //发送FIFO中数据个数， 0 TFNF=0时表示FIFO内有8个数据，TFNF=1时表示FIFO内有0个数据 1--7 FIFO内有1--7个数据 1459 #define SPI_STAT_TFLVL_Msk (0x07 << SPI_STAT_TFLVL_Pos) 1460 #define SPI_STAT_RFLVL_Pos 9 //接收FIFO中数据个数， 0 RFF=1时表示FIFO内有8个数据， RFF=0时表示FIFO内有0个数据 1--7 FIFO内有1--7个数据 1461 #define SPI_STAT_RFLVL_Msk (0x07 << SPI_STAT_RFLVL_Pos) 1462 #define SPI_STAT_BUSY_Pos 15 1463 #define SPI_STAT_BUSY_Msk (0x01 << SPI_STAT_BUSY_Pos) 1464 1465 #define SPI_IE_RFOVF_Pos 0 1466 #define SPI_IE_RFOVF_Msk (0x01 << SPI_IE_RFOVF_Pos) 1467 #define SPI_IE_RFF_Pos 1 1468 #define SPI_IE_RFF_Msk (0x01 << SPI_IE_RFF_Pos) 1469 #define SPI_IE_RFHF_Pos 2 //~rxfifo_full & (rxfifo_level == 4) 1470 #define SPI_IE_RFHF_Msk (0x01 << SPI_IE_RFHF_Pos) 1471 #define SPI_IE_TFE_Pos 3 1472 #define SPI_IE_TFE_Msk (0x01 << SPI_IE_TFE_Pos) 1473 #define SPI_IE_TFHF_Pos 4 //~txfifo_full & (txfifo_level == 4) 1474 #define SPI_IE_TFHF_Msk (0x01 << SPI_IE_TFHF_Pos) 1475 #define SPI_IE_WTC_Pos 8 //Word Transmit Complete 1476 #define SPI_IE_WTC_Msk (0x01 << SPI_IE_WTC_Pos) 1477 #define SPI_IE_FTC_Pos 9 //Frame Transmit Complete 1478 #define SPI_IE_FTC_Msk (0x01 << SPI_IE_FTC_Pos) 1479 1480 #define SPI_IF_RFOVF_Pos 0 //写1清零 1481 #define SPI_IF_RFOVF_Msk (0x01 << SPI_IF_RFOVF_Pos) 1482 #define SPI_IF_RFF_Pos 1 1483 #define SPI_IF_RFF_Msk (0x01 << SPI_IF_RFF_Pos) 1484 #define SPI_IF_RFHF_Pos 2 1485 #define SPI_IF_RFHF_Msk (0x01 << SPI_IF_RFHF_Pos) 1486 #define SPI_IF_TFE_Pos 3 1487 #define SPI_IF_TFE_Msk (0x01 << SPI_IF_TFE_Pos) 1488 #define SPI_IF_TFHF_Pos 4 1489 #define SPI_IF_TFHF_Msk (0x01 << SPI_IF_TFHF_Pos) 1490 #define SPI_IF_WTC_Pos 8 //Word Transmit Complete，每传输完成一个数据字由硬件置1 1491 #define SPI_IF_WTC_Msk (0x01 << SPI_IF_WTC_Pos) 1492 #define SPI_IF_FTC_Pos 9 //Frame Transmit Complete，WTC置位时若TX FIFO是空的，则FTC置位 1493 #define SPI_IF_FTC_Msk (0x01 << SPI_IF_FTC_Pos) 1494 1495 1496 1497 1498 typedef struct { 1499 __IO uint32_t CLKDIV; //[15:0] 须将内部工作频率分到SCL频率的5倍，即CLKDIV = SYS_Freq/5/SCL_Freq - 1 1500 1501 __IO uint32_t CTRL; 1502 1503 __IO uint32_t MSTDAT; 1504 1505 __IO uint32_t MSTCMD; 1506 1507 __IO uint32_t SLVCR; 1508 1509 __IO uint32_t SLVIF; 1510 1511 __IO uint32_t SLVTX; 1512 1513 __IO uint32_t SLVRX; 1514 } I2C_TypeDef; 1515 1516 1517 #define I2C_CTRL_MSTIE_Pos 6 1518 #define I2C_CTRL_MSTIE_Msk (0x01 << I2C_CTRL_MSTIE_Pos) 1519 #define I2C_CTRL_EN_Pos 7 1520 #define I2C_CTRL_EN_Msk (0x01 << I2C_CTRL_EN_Pos) 1521 1522 #define I2C_MSTCMD_IF_Pos 0 //1 有等待处理的中断，写1清零 有两种情况下此位硬件置位：1、一个字节传输完成 2、总线访问权丢失 1523 #define I2C_MSTCMD_IF_Msk (0x01 << I2C_MSTCMD_IF_Pos) 1524 #define I2C_MSTCMD_TIP_Pos 1 //Transmission In Process 1525 #define I2C_MSTCMD_TIP_Msk (0x01 << I2C_MSTCMD_TIP_Pos) 1526 #define I2C_MSTCMD_ACK_Pos 3 //接收模式下，0 向发送端反馈ACK 1 向发送端反馈NACK 1527 #define I2C_MSTCMD_ACK_Msk (0x01 << I2C_MSTCMD_ACK_Pos) 1528 #define I2C_MSTCMD_WR_Pos 4 // 向Slave写数据时，把这一位写1，自动清零 1529 #define I2C_MSTCMD_WR_Msk (0x01 << I2C_MSTCMD_WR_Pos) 1530 #define I2C_MSTCMD_RD_Pos 5 //写：从Slave读数据时，把这一位写1，自动清零 读：当I2C模块失去总线的访问权时硬件置1 1531 #define I2C_MSTCMD_RD_Msk (0x01 << I2C_MSTCMD_RD_Pos) 1532 #define I2C_MSTCMD_BUSY_Pos 6 //读：当检测到START之后，这一位变1；当检测到STOP之后，这一位变0 1533 #define I2C_MSTCMD_BUSY_Msk (0x01 << I2C_MSTCMD_BUSY_Pos) 1534 #define I2C_MSTCMD_STO_Pos 6 //写：产生STOP，自动清零 1535 #define I2C_MSTCMD_STO_Msk (0x01 << I2C_MSTCMD_STO_Pos) 1536 #define I2C_MSTCMD_RXACK_Pos 7 //读：接收到的Slave的ACK位，0 收到ACK 1 收到NACK 1537 #define I2C_MSTCMD_RXACK_Msk (0x01 << I2C_MSTCMD_RXACK_Pos) 1538 #define I2C_MSTCMD_STA_Pos 7 //写：产生START，自动清零 1539 #define I2C_MSTCMD_STA_Msk (0x01 << I2C_MSTCMD_STA_Pos) 1540 1541 #define I2C_SLVCR_IM_RXEND_Pos 0 //接收完成中断禁止 1542 #define I2C_SLVCR_IM_RXEND_Msk (0x01 << I2C_SLVCR_IM_RXEND_Pos) 1543 #define I2C_SLVCR_IM_TXEND_Pos 1 //发送完成中断禁止 1544 #define I2C_SLVCR_IM_TXEND_Msk (0x01 << I2C_SLVCR_IM_TXEND_Pos) 1545 #define I2C_SLVCR_IM_STADET_Pos 2 //检测到起始中断禁止 1546 #define I2C_SLVCR_IM_STADET_Msk (0x01 << I2C_SLVCR_IM_STADET_Pos) 1547 #define I2C_SLVCR_IM_STODET_Pos 3 //检测到停止中断禁止 1548 #define I2C_SLVCR_IM_STODET_Msk (0x01 << I2C_SLVCR_IM_STODET_Pos) 1549 #define I2C_SLVCR_IM_RDREQ_Pos 4 //接收到读请求中断禁止 1550 #define I2C_SLVCR_IM_RDREQ_Msk (0x01 << I2C_SLVCR_IM_RDREQ_Pos) 1551 #define I2C_SLVCR_IM_WRREQ_Pos 5 //接收到写请求中断禁止 1552 #define I2C_SLVCR_IM_WRREQ_Msk (0x01 << I2C_SLVCR_IM_WRREQ_Pos) 1553 #define I2C_SLVCR_ADDR7b_Pos 16 //1 7位地址模式 0 10位地址模式 1554 #define I2C_SLVCR_ADDR7b_Msk (0x01 << I2C_SLVCR_ADDR7b_Pos) 1555 #define I2C_SLVCR_ACK_Pos 17 //1 应答ACK 0 应答NACK 1556 #define I2C_SLVCR_ACK_Msk (0x01 << I2C_SLVCR_ACK_Pos) 1557 #define I2C_SLVCR_SLAVE_Pos 18 //1 从机模式 0 主机模式 1558 #define I2C_SLVCR_SLAVE_Msk (0x01 << I2C_SLVCR_SLAVE_Pos) 1559 #define I2C_SLVCR_DEBOUNCE_Pos 19 //去抖动使能 1560 #define I2C_SLVCR_DEBOUNCE_Msk (0x01 << I2C_SLVCR_DEBOUNCE_Pos) 1561 #define I2C_SLVCR_ADDR_Pos 20 //从机地址 1562 #define I2C_SLVCR_ADDR_Msk (0x3FF << I2C_SLVCR_ADDR_Pos) 1563 1564 #define I2C_SLVIF_RXEND_Pos 0 //接收完成中断标志，写1清零 1565 #define I2C_SLVIF_RXEND_Msk (0x01 << I2C_SLVIF_RXEND_Pos) 1566 #define I2C_SLVIF_TXEND_Pos 1 //发送完成中断标志，写1清零 1567 #define I2C_SLVIF_TXEND_Msk (0x01 << I2C_SLVIF_TXEND_Pos) 1568 #define I2C_SLVIF_STADET_Pos 2 //检测到起始中断标志，写1清零 1569 #define I2C_SLVIF_STADET_Msk (0x01 << I2C_SLVIF_STADET_Pos) 1570 #define I2C_SLVIF_STODET_Pos 3 //检测到停止中断标志，写1清零 1571 #define I2C_SLVIF_STODET_Msk (0x01 << I2C_SLVIF_STODET_Pos) 1572 #define I2C_SLVIF_RDREQ_Pos 4 //接收到读请求中断标志 1573 #define I2C_SLVIF_RDREQ_Msk (0x01 << I2C_SLVIF_RDREQ_Pos) 1574 #define I2C_SLVIF_WRREQ_Pos 5 //接收到写请求中断标志 1575 #define I2C_SLVIF_WRREQ_Msk (0x01 << I2C_SLVIF_WRREQ_Pos) 1576 #define I2C_SLVIF_ACTIVE_Pos 6 //slave 有效 1577 #define I2C_SLVIF_ACTIVE_Msk (0x01 << I2C_SLVIF_ACTIVE_Pos) 1578 1579 1580 1581 1582 typedef struct { 1583 __IO uint32_t CTRL; 1584 1585 __IO uint32_t START; 1586 1587 __IO uint32_t IE; 1588 1589 __IO uint32_t IF; 1590 1591 struct { 1592 __IO uint32_t STAT; 1593 1594 __IO uint32_t DATA; 1595 1596 uint32_t RESERVED[2]; 1597 } CH[8]; 1598 1599 __IO uint32_t CTRL1; 1600 1601 __IO uint32_t CTRL2; 1602 1603 uint32_t RESERVED[2]; 1604 1605 __IO uint32_t CALIBSET; 1606 1607 __IO uint32_t CALIBEN; 1608 } ADC_TypeDef; 1609 1610 1611 #define ADC_CTRL_CH0_Pos 0 //通道选中 1612 #define ADC_CTRL_CH0_Msk (0x01 << ADC_CTRL_CH0_Pos) 1613 #define ADC_CTRL_CH1_Pos 1 1614 #define ADC_CTRL_CH1_Msk (0x01 << ADC_CTRL_CH1_Pos) 1615 #define ADC_CTRL_CH2_Pos 2 1616 #define ADC_CTRL_CH2_Msk (0x01 << ADC_CTRL_CH2_Pos) 1617 #define ADC_CTRL_CH3_Pos 3 1618 #define ADC_CTRL_CH3_Msk (0x01 << ADC_CTRL_CH3_Pos) 1619 #define ADC_CTRL_CH4_Pos 4 1620 #define ADC_CTRL_CH4_Msk (0x01 << ADC_CTRL_CH4_Pos) 1621 #define ADC_CTRL_CH5_Pos 5 1622 #define ADC_CTRL_CH5_Msk (0x01 << ADC_CTRL_CH5_Pos) 1623 #define ADC_CTRL_CH6_Pos 6 1624 #define ADC_CTRL_CH6_Msk (0x01 << ADC_CTRL_CH6_Pos) 1625 #define ADC_CTRL_CH7_Pos 7 1626 #define ADC_CTRL_CH7_Msk (0x01 << ADC_CTRL_CH7_Pos) 1627 #define ADC_CTRL_AVG_Pos 8 //0 1次采样 1 2次采样取平均值 3 4次采样取平均值 7 8次采样取平均值 15 16次采样取平均值 1628 #define ADC_CTRL_AVG_Msk (0x0F << ADC_CTRL_AVG_Pos) 1629 #define ADC_CTRL_EN_Pos 12 1630 #define ADC_CTRL_EN_Msk (0x01 << ADC_CTRL_EN_Pos) 1631 #define ADC_CTRL_CONT_Pos 13 //Continuous conversion，只在软件启动模式下有效，0 单次转换，转换完成后START位自动清除停止转换 1632 #define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) // 1 连续转换，启动后一直采样、转换，直到软件清除START位 1633 #define ADC_CTRL_TRIG_Pos 14 //转换触发方式：0 软件启动转换 1 PWM触发 1634 #define ADC_CTRL_TRIG_Msk (0x01 << ADC_CTRL_TRIG_Pos) 1635 #define ADC_CTRL_CLKSRC_Pos 15 //0 VCO 1 HRC 1636 #define ADC_CTRL_CLKSRC_Msk (0x01 << ADC_CTRL_CLKSRC_Pos) 1637 #define ADC_CTRL_FIFOCLR_Pos 24 //[24] CH0_FIFO_CLR [25] CH1_FIFO_CLR ... [31] CH7_FIFO_CLR 1638 #define ADC_CTRL_FIFOCLR_Msk (0xFFu<< ADC_CTRL_FIFOCLR_Pos) 1639 1640 #define ADC_START_GO_Pos 0 //软件触发模式下，写1启动ADC采样和转换，在单次模式下转换完成后硬件自动清零，在扫描模式下必须软件写0停止ADC转换 1641 #define ADC_START_GO_Msk (0x01 << ADC_START_GO_Pos) 1642 #define ADC_START_BUSY_Pos 4 1643 #define ADC_START_BUSY_Msk (0x01 << ADC_START_BUSY_Pos) 1644 1645 #define ADC_IE_CH0EOC_Pos 0 //End Of Convertion 1646 #define ADC_IE_CH0EOC_Msk (0x01 << ADC_IE_CH0EOC_Pos) 1647 #define ADC_IE_CH0OVF_Pos 1 //Overflow 1648 #define ADC_IE_CH0OVF_Msk (0x01 << ADC_IE_CH0OVF_Pos) 1649 #define ADC_IE_CH0HFULL_Pos 2 //FIFO Half Full 1650 #define ADC_IE_CH0HFULL_Msk (0x01 << ADC_IE_CH0HFULL_Pos) 1651 #define ADC_IE_CH0FULL_Pos 3 //FIFO Full 1652 #define ADC_IE_CH0FULL_Msk (0x01 << ADC_IE_CH0FULL_Pos) 1653 #define ADC_IE_CH1EOC_Pos 4 1654 #define ADC_IE_CH1EOC_Msk (0x01 << ADC_IE_CH1EOC_Pos) 1655 #define ADC_IE_CH1OVF_Pos 5 1656 #define ADC_IE_CH1OVF_Msk (0x01 << ADC_IE_CH1OVF_Pos) 1657 #define ADC_IE_CH1HFULL_Pos 6 1658 #define ADC_IE_CH1HFULL_Msk (0x01 << ADC_IE_CH1HFULL_Pos) 1659 #define ADC_IE_CH1FULL_Pos 7 1660 #define ADC_IE_CH1FULL_Msk (0x01 << ADC_IE_CH1FULL_Pos) 1661 #define ADC_IE_CH2EOC_Pos 8 1662 #define ADC_IE_CH2EOC_Msk (0x01 << ADC_IE_CH2EOC_Pos) 1663 #define ADC_IE_CH2OVF_Pos 9 1664 #define ADC_IE_CH2OVF_Msk (0x01 << ADC_IE_CH2OVF_Pos) 1665 #define ADC_IE_CH2HFULL_Pos 10 1666 #define ADC_IE_CH2HFULL_Msk (0x01 << ADC_IE_CH2HFULL_Pos) 1667 #define ADC_IE_CH2FULL_Pos 11 1668 #define ADC_IE_CH2FULL_Msk (0x01 << ADC_IE_CH2FULL_Pos) 1669 #define ADC_IE_CH3EOC_Pos 12 1670 #define ADC_IE_CH3EOC_Msk (0x01 << ADC_IE_CH3EOC_Pos) 1671 #define ADC_IE_CH3OVF_Pos 13 1672 #define ADC_IE_CH3OVF_Msk (0x01 << ADC_IE_CH3OVF_Pos) 1673 #define ADC_IE_CH3HFULL_Pos 14 1674 #define ADC_IE_CH3HFULL_Msk (0x01 << ADC_IE_CH3HFULL_Pos) 1675 #define ADC_IE_CH3FULL_Pos 15 1676 #define ADC_IE_CH3FULL_Msk (0x01 << ADC_IE_CH3FULL_Pos) 1677 #define ADC_IE_CH4EOC_Pos 16 1678 #define ADC_IE_CH4EOC_Msk (0x01 << ADC_IE_CH4EOC_Pos) 1679 #define ADC_IE_CH4OVF_Pos 17 1680 #define ADC_IE_CH4OVF_Msk (0x01 << ADC_IE_CH4OVF_Pos) 1681 #define ADC_IE_CH4HFULL_Pos 18 1682 #define ADC_IE_CH4HFULL_Msk (0x01 << ADC_IE_CH4HFULL_Pos) 1683 #define ADC_IE_CH4FULL_Pos 19 1684 #define ADC_IE_CH4FULL_Msk (0x01 << ADC_IE_CH4FULL_Pos) 1685 #define ADC_IE_CH5EOC_Pos 20 1686 #define ADC_IE_CH5EOC_Msk (0x01 << ADC_IE_CH5EOC_Pos) 1687 #define ADC_IE_CH5OVF_Pos 21 1688 #define ADC_IE_CH5OVF_Msk (0x01 << ADC_IE_CH5OVF_Pos) 1689 #define ADC_IE_CH5HFULL_Pos 22 1690 #define ADC_IE_CH5HFULL_Msk (0x01 << ADC_IE_CH5HFULL_Pos) 1691 #define ADC_IE_CH5FULL_Pos 23 1692 #define ADC_IE_CH5FULL_Msk (0x01 << ADC_IE_CH5FULL_Pos) 1693 #define ADC_IE_CH6EOC_Pos 24 1694 #define ADC_IE_CH6EOC_Msk (0x01 << ADC_IE_CH6EOC_Pos) 1695 #define ADC_IE_CH6OVF_Pos 25 1696 #define ADC_IE_CH6OVF_Msk (0x01 << ADC_IE_CH6OVF_Pos) 1697 #define ADC_IE_CH6HFULL_Pos 26 1698 #define ADC_IE_CH6HFULL_Msk (0x01 << ADC_IE_CH6HFULL_Pos) 1699 #define ADC_IE_CH6FULL_Pos 27 1700 #define ADC_IE_CH6FULL_Msk (0x01 << ADC_IE_CH6FULL_Pos) 1701 #define ADC_IE_CH7EOC_Pos 28 1702 #define ADC_IE_CH7EOC_Msk (0x01 << ADC_IE_CH7EOC_Pos) 1703 #define ADC_IE_CH7OVF_Pos 29 1704 #define ADC_IE_CH7OVF_Msk (0x01 << ADC_IE_CH7OVF_Pos) 1705 #define ADC_IE_CH7HFULL_Pos 30 1706 #define ADC_IE_CH7HFULL_Msk (0x01 << ADC_IE_CH7HFULL_Pos) 1707 #define ADC_IE_CH7FULL_Pos 31 1708 #define ADC_IE_CH7FULL_Msk (0x01u<< ADC_IE_CH7FULL_Pos) 1709 1710 #define ADC_IF_CH0EOC_Pos 0 //写1清零 1711 #define ADC_IF_CH0EOC_Msk (0x01 << ADC_IF_CH0EOC_Pos) 1712 #define ADC_IF_CH0OVF_Pos 1 //写1清零 1713 #define ADC_IF_CH0OVF_Msk (0x01 << ADC_IF_CH0OVF_Pos) 1714 #define ADC_IF_CH0HFULL_Pos 2 //写1清零 1715 #define ADC_IF_CH0HFULL_Msk (0x01 << ADC_IF_CH0HFULL_Pos) 1716 #define ADC_IF_CH0FULL_Pos 3 //写1清零 1717 #define ADC_IF_CH0FULL_Msk (0x01 << ADC_IF_CH0FULL_Pos) 1718 #define ADC_IF_CH1EOC_Pos 4 1719 #define ADC_IF_CH1EOC_Msk (0x01 << ADC_IF_CH1EOC_Pos) 1720 #define ADC_IF_CH1OVF_Pos 5 1721 #define ADC_IF_CH1OVF_Msk (0x01 << ADC_IF_CH1OVF_Pos) 1722 #define ADC_IF_CH1HFULL_Pos 6 1723 #define ADC_IF_CH1HFULL_Msk (0x01 << ADC_IF_CH1HFULL_Pos) 1724 #define ADC_IF_CH1FULL_Pos 7 1725 #define ADC_IF_CH1FULL_Msk (0x01 << ADC_IF_CH1FULL_Pos) 1726 #define ADC_IF_CH2EOC_Pos 8 1727 #define ADC_IF_CH2EOC_Msk (0x01 << ADC_IF_CH2EOC_Pos) 1728 #define ADC_IF_CH2OVF_Pos 9 1729 #define ADC_IF_CH2OVF_Msk (0x01 << ADC_IF_CH2OVF_Pos) 1730 #define ADC_IF_CH2HFULL_Pos 10 1731 #define ADC_IF_CH2HFULL_Msk (0x01 << ADC_IF_CH2HFULL_Pos) 1732 #define ADC_IF_CH2FULL_Pos 11 1733 #define ADC_IF_CH2FULL_Msk (0x01 << ADC_IF_CH2FULL_Pos) 1734 #define ADC_IF_CH3EOC_Pos 12 1735 #define ADC_IF_CH3EOC_Msk (0x01 << ADC_IF_CH3EOC_Pos) 1736 #define ADC_IF_CH3OVF_Pos 13 1737 #define ADC_IF_CH3OVF_Msk (0x01 << ADC_IF_CH3OVF_Pos) 1738 #define ADC_IF_CH3HFULL_Pos 14 1739 #define ADC_IF_CH3HFULL_Msk (0x01 << ADC_IF_CH3HFULL_Pos) 1740 #define ADC_IF_CH3FULL_Pos 15 1741 #define ADC_IF_CH3FULL_Msk (0x01 << ADC_IF_CH3FULL_Pos) 1742 #define ADC_IF_CH4EOC_Pos 16 1743 #define ADC_IF_CH4EOC_Msk (0x01 << ADC_IF_CH4EOC_Pos) 1744 #define ADC_IF_CH4OVF_Pos 17 1745 #define ADC_IF_CH4OVF_Msk (0x01 << ADC_IF_CH4OVF_Pos) 1746 #define ADC_IF_CH4HFULL_Pos 18 1747 #define ADC_IF_CH4HFULL_Msk (0x01 << ADC_IF_CH4HFULL_Pos) 1748 #define ADC_IF_CH4FULL_Pos 19 1749 #define ADC_IF_CH4FULL_Msk (0x01 << ADC_IF_CH4FULL_Pos) 1750 #define ADC_IF_CH5EOC_Pos 20 1751 #define ADC_IF_CH5EOC_Msk (0x01 << ADC_IF_CH5EOC_Pos) 1752 #define ADC_IF_CH5OVF_Pos 21 1753 #define ADC_IF_CH5OVF_Msk (0x01 << ADC_IF_CH5OVF_Pos) 1754 #define ADC_IF_CH5HFULL_Pos 22 1755 #define ADC_IF_CH5HFULL_Msk (0x01 << ADC_IF_CH5HFULL_Pos) 1756 #define ADC_IF_CH5FULL_Pos 23 1757 #define ADC_IF_CH5FULL_Msk (0x01 << ADC_IF_CH5FULL_Pos) 1758 #define ADC_IF_CH6EOC_Pos 24 1759 #define ADC_IF_CH6EOC_Msk (0x01 << ADC_IF_CH6EOC_Pos) 1760 #define ADC_IF_CH6OVF_Pos 25 1761 #define ADC_IF_CH6OVF_Msk (0x01 << ADC_IF_CH6OVF_Pos) 1762 #define ADC_IF_CH6HFULL_Pos 26 1763 #define ADC_IF_CH6HFULL_Msk (0x01 << ADC_IF_CH6HFULL_Pos) 1764 #define ADC_IF_CH6FULL_Pos 27 1765 #define ADC_IF_CH6FULL_Msk (0x01 << ADC_IF_CH6FULL_Pos) 1766 #define ADC_IF_CH7EOC_Pos 28 1767 #define ADC_IF_CH7EOC_Msk (0x01 << ADC_IF_CH7EOC_Pos) 1768 #define ADC_IF_CH7OVF_Pos 29 1769 #define ADC_IF_CH7OVF_Msk (0x01 << ADC_IF_CH7OVF_Pos) 1770 #define ADC_IF_CH7HFULL_Pos 30 1771 #define ADC_IF_CH7HFULL_Msk (0x01 << ADC_IF_CH7HFULL_Pos) 1772 #define ADC_IF_CH7FULL_Pos 31 1773 #define ADC_IF_CH7FULL_Msk (0x01 << ADC_IF_CH7FULL_Pos) 1774 1775 #define ADC_STAT_EOC_Pos 0 //写1清零 1776 #define ADC_STAT_EOC_Msk (0x01 << ADC_STAT_EOC_Pos) 1777 #define ADC_STAT_OVF_Pos 1 //读数据寄存器清除 1778 #define ADC_STAT_OVF_Msk (0x01 << ADC_STAT_OVF_Pos) 1779 #define ADC_STAT_HFULL_Pos 2 1780 #define ADC_STAT_HFULL_Msk (0x01 << ADC_STAT_HFULL_Pos) 1781 #define ADC_STAT_FULL_Pos 3 1782 #define ADC_STAT_FULL_Msk (0x01 << ADC_STAT_FULL_Pos) 1783 #define ADC_STAT_EMPTY_Pos 4 1784 #define ADC_STAT_EMPTY_Msk (0x01 << ADC_STAT_EMPTY_Pos) 1785 1786 #define ADC_CTRL1_RIN_Pos 4 //输入阻抗：0 无穷大 1 105K 2 90K 3 75K 4 60K 5 45K 6 30K 7 15K 1787 #define ADC_CTRL1_RIN_Msk (0x07 << ADC_CTRL1_RIN_Pos) 1788 1789 #define ADC_CTRL2_RESET_Pos 0 //数字电路复位 1790 #define ADC_CTRL2_RESET_Msk (0x01 << ADC_CTRL2_RESET_Pos) 1791 #define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCM，ADC与PGA输出共模电平选择 1792 #define ADC_CTRL2_ADCEVCM_Msk (0x01 << ADC_CTRL2_ADCEVCM_Pos) 1793 #define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCM，PGA输入共模电平选择 1794 #define ADC_CTRL2_PGAIVCM_Msk (0x01 << ADC_CTRL2_PGAIVCM_Pos) 1795 #define ADC_CTRL2_PGAGAIN_Pos 3 //0 25.1dB 1 21.6dB 2 11.1dB 3 3.5dB 4 0dB(1.8V) 5 -2.9dB 6 -5.3dB 1796 #define ADC_CTRL2_PGAGAIN_Msk (0x07 << ADC_CTRL2_PGAGAIN_Pos) 1797 #define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测量，或在需要1.2V外部REFP时节省成本 1798 #define ADC_CTRL2_REFPOUT_Msk (0x01 << ADC_CTRL2_REFPOUT_Pos 1799 #define ADC_CTRL2_CLKDIV_Pos 24 //时钟分频，只在时钟源为HRC时有效 1800 #define ADC_CTRL2_CLKDIV_Msk (0x1F << ADC_CTRL2_CLKDIV_Pos) 1801 #define ADC_CTRL2_PGAVCM_Pos 29 1802 #define ADC_CTRL2_PGAVCM_Msk (0x07u<< ADC_CTRL2_PGAVCM_Pos) 1803 1804 #define ADC_CALIBSET_OFFSET_Pos 0 1805 #define ADC_CALIBSET_OFFSET_Msk (0x1FF<< ADC_CALIBSET_OFFSET_Pos) 1806 #define ADC_CALIBSET_K_Pos 16 1807 #define ADC_CALIBSET_K_Msk (0x1FF<< ADC_CALIBSET_K_Pos) 1808 1809 #define ADC_CALIBEN_OFFSET_Pos 0 1810 #define ADC_CALIBEN_OFFSET_Msk (0x01 << ADC_CALIBEN_OFFSET_Pos) 1811 #define ADC_CALIBEN_K_Pos 1 1812 #define ADC_CALIBEN_K_Msk (0x01 << ADC_CALIBEN_K_Pos) 1813 1814 1815 1816 1817 typedef struct { 1818 __IO uint32_t MODE; //0 普通模式，A、B两路输出互相独立 1819 //1 互补模式，A、B两路输出都由PERA、HIGHA控制，B路输出与A路输出极性相反，且DZA、DZB控制A、B路输出上升沿推迟时间 1820 //2 单次模式，同普通模式，但一个周期后自动停止 1821 //3 对称模式，A、B两路输出互相独立，以两个计数周期产生一个波形输出周期，分辨率提升一倍、频率降低一倍 1822 //4 对称互补模式，对称模式和互补模式的综合 1823 1824 __IO uint32_t PERA; //[15:0] 周期 1825 1826 __IO uint32_t HIGHA; //[15:0] 高电平持续时长 1827 1828 __IO uint32_t DZA; //[9:0] 死区，即上升沿推迟时长，必须小于HIGHA 1829 1830 __IO uint32_t PERB; 1831 1832 __IO uint32_t HIGHB; 1833 1834 __IO uint32_t DZB; 1835 1836 __IO uint32_t INIOUT; //Init Output level，初始输出电平 1837 } PWM_TypeDef; 1838 1839 1840 #define PWM_INIOUT_PWMA_Pos 0 1841 #define PWM_INIOUT_PWMA_Msk (0x01 << PWM_INIOUT_PWMA_Pos) 1842 #define PWM_INIOUT_PWMB_Pos 1 1843 #define PWM_INIOUT_PWMB_Msk (0x01 << PWM_INIOUT_PWMB_Pos) 1844 1845 1846 typedef struct { 1847 __IO uint32_t FORCEH; 1848 1849 __IO uint32_t ADTRG0A; 1850 __IO uint32_t ADTRG0B; 1851 1852 __IO uint32_t ADTRG1A; 1853 __IO uint32_t ADTRG1B; 1854 1855 __IO uint32_t ADTRG2A; 1856 __IO uint32_t ADTRG2B; 1857 1858 __IO uint32_t ADTRG3A; 1859 __IO uint32_t ADTRG3B; 1860 1861 __IO uint32_t ADTRG4A; 1862 __IO uint32_t ADTRG4B; 1863 1864 __IO uint32_t ADTRG5A; 1865 __IO uint32_t ADTRG5B; 1866 1867 uint32_t RESERVED[3]; 1868 1869 __IO uint32_t HALT; //刹车控制 1870 1871 __IO uint32_t CHEN; 1872 1873 __IO uint32_t IE; 1874 1875 __IO uint32_t IF; 1876 1877 __IO uint32_t IM; //Interrupt Mask 1878 1879 __IO uint32_t IRS; //Interrupt Raw Stat 1880 } PWMG_TypeDef; 1881 1882 1883 #define PWMG_FORCEH_PWM0_Pos 0 1884 #define PWMG_FORCEH_PWM0_Msk (0x01 << PWMG_FORCEH_PWM0_Pos) 1885 #define PWMG_FORCEH_PWM1_Pos 1 1886 #define PWMG_FORCEH_PWM1_Msk (0x01 << PWMG_FORCEH_PWM1_Pos) 1887 #define PWMG_FORCEH_PWM2_Pos 2 1888 #define PWMG_FORCEH_PWM2_Msk (0x01 << PWMG_FORCEH_PWM2_Pos) 1889 #define PWMG_FORCEH_PWM3_Pos 3 1890 #define PWMG_FORCEH_PWM3_Msk (0x01 << PWMG_FORCEH_PWM3_Pos) 1891 #define PWMG_FORCEH_PWM4_Pos 4 1892 #define PWMG_FORCEH_PWM4_Msk (0x01 << PWMG_FORCEH_PWM4_Pos) 1893 #define PWMG_FORCEH_PWM5_Pos 5 1894 #define PWMG_FORCEH_PWM5_Msk (0x01 << PWMG_FORCEH_PWM5_Pos) 1895 1896 #define PWMG_ADTRG_VALUE_Pos 0 1897 #define PWMG_ADTRG_VALUE_Msk (0xFFFF << PWMG_ADTRG0A_VALUE_Pos) 1898 #define PWMG_ADTRG_EVEN_Pos 16 //1 偶数周期生效 0 奇数周期生效 1899 #define PWMG_ADTRG_EVEN_Msk (0x01 << PWMG_ADTRG0A_EVEN_Pos) 1900 #define PWMG_ADTRG_EN_Pos 17 1901 #define PWMG_ADTRG_EN_Msk (0x01 << PWMG_ADTRG0A_EN_Pos) 1902 1903 #define PWMG_HALT_EN_Pos 0 1904 #define PWMG_HALT_EN_Msk (0x01 << PWMG_HALT_EN_Pos) 1905 #define PWMG_HALT_PWM0_Pos 1 1906 #define PWMG_HALT_PWM0_Msk (0x01 << PWMG_HALT_PWM0_Pos) 1907 #define PWMG_HALT_PWM1_Pos 2 1908 #define PWMG_HALT_PWM1_Msk (0x01 << PWMG_HALT_PWM1_Pos) 1909 #define PWMG_HALT_PWM2_Pos 3 1910 #define PWMG_HALT_PWM2_Msk (0x01 << PWMG_HALT_PWM2_Pos) 1911 #define PWMG_HALT_PWM3_Pos 4 1912 #define PWMG_HALT_PWM3_Msk (0x01 << PWMG_HALT_PWM3_Pos) 1913 #define PWMG_HALT_PWM4_Pos 5 1914 #define PWMG_HALT_PWM4_Msk (0x01 << PWMG_HALT_PWM4_Pos) 1915 #define PWMG_HALT_PWM5_Pos 6 1916 #define PWMG_HALT_PWM5_Msk (0x01 << PWMG_HALT_PWM5_Pos) 1917 #define PWMG_HALT_STOPCNT_Pos 7 //1 刹车时将PWM计数器清零，停止计数 0 刹车时，PWM计数器继续计数 1918 #define PWMG_HALT_STOPCNT_Msk (0x01 << PWMG_HALT_STOPCNT_Pos) 1919 #define PWMG_HALT_INLVL_Pos 8 //1 刹车输入高电平有效 1920 #define PWMG_HALT_INLVL_Msk (0x01 << PWMG_HALT_INLVL_Pos) 1921 #define PWMG_HALT_OUTLVL_Pos 9 //1 刹车过程中输出高电平 1922 #define PWMG_HALT_OUTLVL_Msk (0x01 << PWMG_HALT_OUTLVL_Pos) 1923 #define PWMG_HALT_STAT_Pos 10 //1 正在刹车 1924 #define PWMG_HALT_STAT_Msk (0x01 << PWMG_HALT_STAT_Pos) 1925 1926 #define PWMG_CHEN_PWM0A_Pos 0 1927 #define PWMG_CHEN_PWM0A_Msk (0x01 << PWMG_CHEN_PWM0A_Pos) 1928 #define PWMG_CHEN_PWM0B_Pos 1 1929 #define PWMG_CHEN_PWM0B_Msk (0x01 << PWMG_CHEN_PWM0B_Pos) 1930 #define PWMG_CHEN_PWM1A_Pos 2 1931 #define PWMG_CHEN_PWM1A_Msk (0x01 << PWMG_CHEN_PWM1A_Pos) 1932 #define PWMG_CHEN_PWM1B_Pos 3 1933 #define PWMG_CHEN_PWM1B_Msk (0x01 << PWMG_CHEN_PWM1B_Pos) 1934 #define PWMG_CHEN_PWM2A_Pos 4 1935 #define PWMG_CHEN_PWM2A_Msk (0x01 << PWMG_CHEN_PWM2A_Pos) 1936 #define PWMG_CHEN_PWM2B_Pos 5 1937 #define PWMG_CHEN_PWM2B_Msk (0x01 << PWMG_CHEN_PWM2B_Pos) 1938 #define PWMG_CHEN_PWM3A_Pos 6 1939 #define PWMG_CHEN_PWM3A_Msk (0x01 << PWMG_CHEN_PWM3A_Pos) 1940 #define PWMG_CHEN_PWM3B_Pos 7 1941 #define PWMG_CHEN_PWM3B_Msk (0x01 << PWMG_CHEN_PWM3B_Pos) 1942 #define PWMG_CHEN_PWM4A_Pos 8 1943 #define PWMG_CHEN_PWM4A_Msk (0x01 << PWMG_CHEN_PWM4A_Pos) 1944 #define PWMG_CHEN_PWM4B_Pos 9 1945 #define PWMG_CHEN_PWM4B_Msk (0x01 << PWMG_CHEN_PWM4B_Pos) 1946 #define PWMG_CHEN_PWM5A_Pos 10 1947 #define PWMG_CHEN_PWM5A_Msk (0x01 << PWMG_CHEN_PWM5A_Pos) 1948 #define PWMG_CHEN_PWM5B_Pos 11 1949 #define PWMG_CHEN_PWM5B_Msk (0x01 << PWMG_CHEN_PWM5B_Pos) 1950 1951 1952 #define PWMG_IE_NEWP0A_Pos 0 1953 #define PWMG_IE_NEWP0A_Msk (0x01 << PWMG_IE_NEWP0A_Pos) 1954 #define PWMG_IE_NEWP0B_Pos 1 1955 #define PWMG_IE_NEWP0B_Msk (0x01 << PWMG_IE_NEWP0B_Pos) 1956 #define PWMG_IE_NEWP1A_Pos 2 1957 #define PWMG_IE_NEWP1A_Msk (0x01 << PWMG_IE_NEWP1A_Pos) 1958 #define PWMG_IE_NEWP1B_Pos 3 1959 #define PWMG_IE_NEWP1B_Msk (0x01 << PWMG_IE_NEWP1B_Pos) 1960 #define PWMG_IE_NEWP2A_Pos 4 1961 #define PWMG_IE_NEWP2A_Msk (0x01 << PWMG_IE_NEWP2A_Pos) 1962 #define PWMG_IE_NEWP2B_Pos 5 1963 #define PWMG_IE_NEWP2B_Msk (0x01 << PWMG_IE_NEWP2B_Pos) 1964 #define PWMG_IE_NEWP3A_Pos 6 1965 #define PWMG_IE_NEWP3A_Msk (0x01 << PWMG_IE_NEWP3A_Pos) 1966 #define PWMG_IE_NEWP3B_Pos 7 1967 #define PWMG_IE_NEWP3B_Msk (0x01 << PWMG_IE_NEWP3B_Pos) 1968 #define PWMG_IE_NEWP4A_Pos 8 1969 #define PWMG_IE_NEWP4A_Msk (0x01 << PWMG_IE_NEWP4A_Pos) 1970 #define PWMG_IE_NEWP4B_Pos 9 1971 #define PWMG_IE_NEWP4B_Msk (0x01 << PWMG_IE_NEWP4B_Pos) 1972 #define PWMG_IE_NEWP5A_Pos 10 1973 #define PWMG_IE_NEWP5A_Msk (0x01 << PWMG_IE_NEWP5A_Pos) 1974 #define PWMG_IE_NEWP5B_Pos 11 1975 #define PWMG_IE_NEWP5B_Msk (0x01 << PWMG_IE_NEWP5B_Pos) 1976 #define PWMG_IE_HEND0A_Pos 12 1977 #define PWMG_IE_HEND0A_Msk (0x01 << PWMG_IE_HEND0A_Pos) 1978 #define PWMG_IE_HEND0B_Pos 13 1979 #define PWMG_IE_HEND0B_Msk (0x01 << PWMG_IE_HEND0B_Pos) 1980 #define PWMG_IE_HEND1A_Pos 14 1981 #define PWMG_IE_HEND1A_Msk (0x01 << PWMG_IE_HEND1A_Pos) 1982 #define PWMG_IE_HEND1B_Pos 15 1983 #define PWMG_IE_HEND1B_Msk (0x01 << PWMG_IE_HEND1B_Pos) 1984 #define PWMG_IE_HEND2A_Pos 16 1985 #define PWMG_IE_HEND2A_Msk (0x01 << PWMG_IE_HEND2A_Pos) 1986 #define PWMG_IE_HEND2B_Pos 17 1987 #define PWMG_IE_HEND2B_Msk (0x01 << PWMG_IE_HEND2B_Pos) 1988 #define PWMG_IE_HEND3A_Pos 18 1989 #define PWMG_IE_HEND3A_Msk (0x01 << PWMG_IE_HEND3A_Pos) 1990 #define PWMG_IE_HEND3B_Pos 19 1991 #define PWMG_IE_HEND3B_Msk (0x01 << PWMG_IE_HEND3B_Pos) 1992 #define PWMG_IE_HEND4A_Pos 20 1993 #define PWMG_IE_HEND4A_Msk (0x01 << PWMG_IE_HEND4A_Pos) 1994 #define PWMG_IE_HEND4B_Pos 21 1995 #define PWMG_IE_HEND4B_Msk (0x01 << PWMG_IE_HEND4B_Pos) 1996 #define PWMG_IE_HEND5A_Pos 22 1997 #define PWMG_IE_HEND5A_Msk (0x01 << PWMG_IE_HEND5A_Pos) 1998 #define PWMG_IE_HEND5B_Pos 23 1999 #define PWMG_IE_HEND5B_Msk (0x01 << PWMG_IE_HEND5B_Pos) 2000 #define PWMG_IE_HALT_Pos 24 2001 #define PWMG_IE_HALT_Msk (0x01 << PWMG_IE_HALT_Pos) 2002 2003 #define PWMG_IF_NEWP0A_Pos 0 2004 #define PWMG_IF_NEWP0A_Msk (0x01 << PWMG_IF_NEWP0A_Pos) 2005 #define PWMG_IF_NEWP0B_Pos 1 2006 #define PWMG_IF_NEWP0B_Msk (0x01 << PWMG_IF_NEWP0B_Pos) 2007 #define PWMG_IF_NEWP1A_Pos 2 2008 #define PWMG_IF_NEWP1A_Msk (0x01 << PWMG_IF_NEWP1A_Pos) 2009 #define PWMG_IF_NEWP1B_Pos 3 2010 #define PWMG_IF_NEWP1B_Msk (0x01 << PWMG_IF_NEWP1B_Pos) 2011 #define PWMG_IF_NEWP2A_Pos 4 2012 #define PWMG_IF_NEWP2A_Msk (0x01 << PWMG_IF_NEWP2A_Pos) 2013 #define PWMG_IF_NEWP2B_Pos 5 2014 #define PWMG_IF_NEWP2B_Msk (0x01 << PWMG_IF_NEWP2B_Pos) 2015 #define PWMG_IF_NEWP3A_Pos 6 2016 #define PWMG_IF_NEWP3A_Msk (0x01 << PWMG_IF_NEWP3A_Pos) 2017 #define PWMG_IF_NEWP3B_Pos 7 2018 #define PWMG_IF_NEWP3B_Msk (0x01 << PWMG_IF_NEWP3B_Pos) 2019 #define PWMG_IF_NEWP4A_Pos 8 2020 #define PWMG_IF_NEWP4A_Msk (0x01 << PWMG_IF_NEWP4A_Pos) 2021 #define PWMG_IF_NEWP4B_Pos 9 2022 #define PWMG_IF_NEWP4B_Msk (0x01 << PWMG_IF_NEWP4B_Pos) 2023 #define PWMG_IF_NEWP5A_Pos 10 2024 #define PWMG_IF_NEWP5A_Msk (0x01 << PWMG_IF_NEWP5A_Pos) 2025 #define PWMG_IF_NEWP5B_Pos 11 2026 #define PWMG_IF_NEWP5B_Msk (0x01 << PWMG_IF_NEWP5B_Pos) 2027 #define PWMG_IF_HEND0A_Pos 12 2028 #define PWMG_IF_HEND0A_Msk (0x01 << PWMG_IF_HEND0A_Pos) 2029 #define PWMG_IF_HEND0B_Pos 13 2030 #define PWMG_IF_HEND0B_Msk (0x01 << PWMG_IF_HEND0B_Pos) 2031 #define PWMG_IF_HEND1A_Pos 14 2032 #define PWMG_IF_HEND1A_Msk (0x01 << PWMG_IF_HEND1A_Pos) 2033 #define PWMG_IF_HEND1B_Pos 15 2034 #define PWMG_IF_HEND1B_Msk (0x01 << PWMG_IF_HEND1B_Pos) 2035 #define PWMG_IF_HEND2A_Pos 16 2036 #define PWMG_IF_HEND2A_Msk (0x01 << PWMG_IF_HEND2A_Pos) 2037 #define PWMG_IF_HEND2B_Pos 17 2038 #define PWMG_IF_HEND2B_Msk (0x01 << PWMG_IF_HEND2B_Pos) 2039 #define PWMG_IF_HEND3A_Pos 18 2040 #define PWMG_IF_HEND3A_Msk (0x01 << PWMG_IF_HEND3A_Pos) 2041 #define PWMG_IF_HEND3B_Pos 19 2042 #define PWMG_IF_HEND3B_Msk (0x01 << PWMG_IF_HEND3B_Pos) 2043 #define PWMG_IF_HEND4A_Pos 20 2044 #define PWMG_IF_HEND4A_Msk (0x01 << PWMG_IF_HEND4A_Pos) 2045 #define PWMG_IF_HEND4B_Pos 21 2046 #define PWMG_IF_HEND4B_Msk (0x01 << PWMG_IF_HEND4B_Pos) 2047 #define PWMG_IF_HEND5A_Pos 22 2048 #define PWMG_IF_HEND5A_Msk (0x01 << PWMG_IF_HEND5A_Pos) 2049 #define PWMG_IF_HEND5B_Pos 23 2050 #define PWMG_IF_HEND5B_Msk (0x01 << PWMG_IF_HEND5B_Pos) 2051 #define PWMG_IF_HALT_Pos 24 2052 #define PWMG_IF_HALT_Msk (0x01 << PWMG_IF_HALT_Pos) 2053 2054 #define PWMG_IM_NEWP0A_Pos 0 //Interrupt Mask 2055 #define PWMG_IM_NEWP0A_Msk (0x01 << PWMG_IM_NEWP0A_Pos) 2056 #define PWMG_IM_NEWP0B_Pos 1 2057 #define PWMG_IM_NEWP0B_Msk (0x01 << PWMG_IM_NEWP0B_Pos) 2058 #define PWMG_IM_NEWP1A_Pos 2 2059 #define PWMG_IM_NEWP1A_Msk (0x01 << PWMG_IM_NEWP1A_Pos) 2060 #define PWMG_IM_NEWP1B_Pos 3 2061 #define PWMG_IM_NEWP1B_Msk (0x01 << PWMG_IM_NEWP1B_Pos) 2062 #define PWMG_IM_NEWP2A_Pos 4 2063 #define PWMG_IM_NEWP2A_Msk (0x01 << PWMG_IM_NEWP2A_Pos) 2064 #define PWMG_IM_NEWP2B_Pos 5 2065 #define PWMG_IM_NEWP2B_Msk (0x01 << PWMG_IM_NEWP2B_Pos) 2066 #define PWMG_IM_NEWP3A_Pos 6 2067 #define PWMG_IM_NEWP3A_Msk (0x01 << PWMG_IM_NEWP3A_Pos) 2068 #define PWMG_IM_NEWP3B_Pos 7 2069 #define PWMG_IM_NEWP3B_Msk (0x01 << PWMG_IM_NEWP3B_Pos) 2070 #define PWMG_IM_NEWP4A_Pos 8 2071 #define PWMG_IM_NEWP4A_Msk (0x01 << PWMG_IM_NEWP4A_Pos) 2072 #define PWMG_IM_NEWP4B_Pos 9 2073 #define PWMG_IM_NEWP4B_Msk (0x01 << PWMG_IM_NEWP4B_Pos) 2074 #define PWMG_IM_NEWP5A_Pos 10 2075 #define PWMG_IM_NEWP5A_Msk (0x01 << PWMG_IM_NEWP5A_Pos) 2076 #define PWMG_IM_NEWP5B_Pos 11 2077 #define PWMG_IM_NEWP5B_Msk (0x01 << PWMG_IM_NEWP5B_Pos) 2078 #define PWMG_IM_HEND0A_Pos 12 2079 #define PWMG_IM_HEND0A_Msk (0x01 << PWMG_IM_HEND0A_Pos) 2080 #define PWMG_IM_HEND0B_Pos 13 2081 #define PWMG_IM_HEND0B_Msk (0x01 << PWMG_IM_HEND0B_Pos) 2082 #define PWMG_IM_HEND1A_Pos 14 2083 #define PWMG_IM_HEND1A_Msk (0x01 << PWMG_IM_HEND1A_Pos) 2084 #define PWMG_IM_HEND1B_Pos 15 2085 #define PWMG_IM_HEND1B_Msk (0x01 << PWMG_IM_HEND1B_Pos) 2086 #define PWMG_IM_HEND2A_Pos 16 2087 #define PWMG_IM_HEND2A_Msk (0x01 << PWMG_IM_HEND2A_Pos) 2088 #define PWMG_IM_HEND2B_Pos 17 2089 #define PWMG_IM_HEND2B_Msk (0x01 << PWMG_IM_HEND2B_Pos) 2090 #define PWMG_IM_HEND3A_Pos 18 2091 #define PWMG_IM_HEND3A_Msk (0x01 << PWMG_IM_HEND3A_Pos) 2092 #define PWMG_IM_HEND3B_Pos 19 2093 #define PWMG_IM_HEND3B_Msk (0x01 << PWMG_IM_HEND3B_Pos) 2094 #define PWMG_IM_HEND4A_Pos 20 2095 #define PWMG_IM_HEND4A_Msk (0x01 << PWMG_IM_HEND4A_Pos) 2096 #define PWMG_IM_HEND4B_Pos 21 2097 #define PWMG_IM_HEND4B_Msk (0x01 << PWMG_IM_HEND4B_Pos) 2098 #define PWMG_IM_HEND5A_Pos 22 2099 #define PWMG_IM_HEND5A_Msk (0x01 << PWMG_IM_HEND5A_Pos) 2100 #define PWMG_IM_HEND5B_Pos 23 2101 #define PWMG_IM_HEND5B_Msk (0x01 << PWMG_IM_HEND5B_Pos) 2102 #define PWMG_IM_HALT_Pos 24 2103 #define PWMG_IM_HALT_Msk (0x01 << PWMG_IM_HALT_Pos) 2104 2105 #define PWMG_IRS_NEWP0A_Pos 0 //Interrupt Raw State 2106 #define PWMG_IRS_NEWP0A_Msk (0x01 << PWMG_IRS_NEWP0A_Pos) 2107 #define PWMG_IRS_NEWP0B_Pos 1 2108 #define PWMG_IRS_NEWP0B_Msk (0x01 << PWMG_IRS_NEWP0B_Pos) 2109 #define PWMG_IRS_NEWP1A_Pos 2 2110 #define PWMG_IRS_NEWP1A_Msk (0x01 << PWMG_IRS_NEWP1A_Pos) 2111 #define PWMG_IRS_NEWP1B_Pos 3 2112 #define PWMG_IRS_NEWP1B_Msk (0x01 << PWMG_IRS_NEWP1B_Pos) 2113 #define PWMG_IRS_NEWP2A_Pos 4 2114 #define PWMG_IRS_NEWP2A_Msk (0x01 << PWMG_IRS_NEWP2A_Pos) 2115 #define PWMG_IRS_NEWP2B_Pos 5 2116 #define PWMG_IRS_NEWP2B_Msk (0x01 << PWMG_IRS_NEWP2B_Pos) 2117 #define PWMG_IRS_NEWP3A_Pos 6 2118 #define PWMG_IRS_NEWP3A_Msk (0x01 << PWMG_IRS_NEWP3A_Pos) 2119 #define PWMG_IRS_NEWP3B_Pos 7 2120 #define PWMG_IRS_NEWP3B_Msk (0x01 << PWMG_IRS_NEWP3B_Pos) 2121 #define PWMG_IRS_NEWP4A_Pos 8 2122 #define PWMG_IRS_NEWP4A_Msk (0x01 << PWMG_IRS_NEWP4A_Pos) 2123 #define PWMG_IRS_NEWP4B_Pos 9 2124 #define PWMG_IRS_NEWP4B_Msk (0x01 << PWMG_IRS_NEWP4B_Pos) 2125 #define PWMG_IRS_NEWP5A_Pos 10 2126 #define PWMG_IRS_NEWP5A_Msk (0x01 << PWMG_IRS_NEWP5A_Pos) 2127 #define PWMG_IRS_NEWP5B_Pos 11 2128 #define PWMG_IRS_NEWP5B_Msk (0x01 << PWMG_IRS_NEWP5B_Pos) 2129 #define PWMG_IRS_HEND0A_Pos 12 2130 #define PWMG_IRS_HEND0A_Msk (0x01 << PWMG_IRS_HEND0A_Pos) 2131 #define PWMG_IRS_HEND0B_Pos 13 2132 #define PWMG_IRS_HEND0B_Msk (0x01 << PWMG_IRS_HEND0B_Pos) 2133 #define PWMG_IRS_HEND1A_Pos 14 2134 #define PWMG_IRS_HEND1A_Msk (0x01 << PWMG_IRS_HEND1A_Pos) 2135 #define PWMG_IRS_HEND1B_Pos 15 2136 #define PWMG_IRS_HEND1B_Msk (0x01 << PWMG_IRS_HEND1B_Pos) 2137 #define PWMG_IRS_HEND2A_Pos 16 2138 #define PWMG_IRS_HEND2A_Msk (0x01 << PWMG_IRS_HEND2A_Pos) 2139 #define PWMG_IRS_HEND2B_Pos 17 2140 #define PWMG_IRS_HEND2B_Msk (0x01 << PWMG_IRS_HEND2B_Pos) 2141 #define PWMG_IRS_HEND3A_Pos 18 2142 #define PWMG_IRS_HEND3A_Msk (0x01 << PWMG_IRS_HEND3A_Pos) 2143 #define PWMG_IRS_HEND3B_Pos 19 2144 #define PWMG_IRS_HEND3B_Msk (0x01 << PWMG_IRS_HEND3B_Pos) 2145 #define PWMG_IRS_HEND4A_Pos 20 2146 #define PWMG_IRS_HEND4A_Msk (0x01 << PWMG_IRS_HEND4A_Pos) 2147 #define PWMG_IRS_HEND4B_Pos 21 2148 #define PWMG_IRS_HEND4B_Msk (0x01 << PWMG_IRS_HEND4B_Pos) 2149 #define PWMG_IRS_HEND5A_Pos 22 2150 #define PWMG_IRS_HEND5A_Msk (0x01 << PWMG_IRS_HEND5A_Pos) 2151 #define PWMG_IRS_HEND5B_Pos 23 2152 #define PWMG_IRS_HEND5B_Msk (0x01 << PWMG_IRS_HEND5B_Pos) 2153 #define PWMG_IRS_HALT_Pos 24 2154 #define PWMG_IRS_HALT_Msk (0x01 << PWMG_IRS_HALT_Pos) 2155 2156 2157 2158 2159 typedef struct { 2160 __IO uint32_t EN; //[0] ENABLE 2161 2162 __IO uint32_t IE; //只有为1时，IF[CHx]在DMA传输结束时才能变为1，否则将一直保持在0 2163 2164 __IO uint32_t IM; //当为1时，即使IF[CHx]为1，dma_int也不会因此变1 2165 2166 __IO uint32_t IF; //写1清零 2167 2168 uint32_t RESERVED[12]; 2169 2170 struct { 2171 __IO uint32_t CR; 2172 2173 __IO uint32_t AM; //Adress Mode 2174 2175 __IO uint32_t SRC; 2176 2177 __IO uint32_t SRCSGADDR1; //只在Scatter Gather模式下使用 2178 2179 __IO uint32_t SRCSGADDR2; //只在Scatter Gather模式下使用 2180 2181 __IO uint32_t SRCSGADDR3; //只在Scatter Gather模式下使用 2182 2183 __IO uint32_t SRCSGLEN; //只在Scatter Gather模式下使用 2184 2185 __IO uint32_t DST; 2186 2187 __IO uint32_t DSTSGADDR1; //只在Scatter Gather模式下使用 2188 2189 __IO uint32_t DSTSGADDR2; //只在Scatter Gather模式下使用 2190 2191 __IO uint32_t DSTSGADDR3; //只在Scatter Gather模式下使用 2192 2193 __IO uint32_t DSTSGLEN; //只在Scatter Gather模式下使用 2194 2195 uint32_t RESERVED[4]; 2196 } CH[3]; 2197 } DMA_TypeDef; 2198 2199 2200 #define DMA_IE_CH0_Pos 0 2201 #define DMA_IE_CH0_Msk (0x01 << DMA_IE_CH0_Pos) 2202 #define DMA_IE_CH1_Pos 1 2203 #define DMA_IE_CH1_Msk (0x01 << DMA_IE_CH1_Pos) 2204 #define DMA_IE_CH2_Pos 2 2205 #define DMA_IE_CH2_Msk (0x01 << DMA_IE_CH2_Pos) 2206 #define DMA_IE_CH3_Pos 3 2207 #define DMA_IE_CH3_Msk (0x01 << DMA_IE_CH3_Pos) 2208 #define DMA_IE_CH4_Pos 4 2209 #define DMA_IE_CH4_Msk (0x01 << DMA_IE_CH4_Pos) 2210 #define DMA_IE_CH5_Pos 5 2211 #define DMA_IE_CH5_Msk (0x01 << DMA_IE_CH5_Pos) 2212 #define DMA_IE_CH6_Pos 6 2213 #define DMA_IE_CH6_Msk (0x01 << DMA_IE_CH6_Pos) 2214 #define DMA_IE_CH7_Pos 7 2215 #define DMA_IE_CH7_Msk (0x01 << DMA_IE_CH7_Pos) 2216 2217 #define DMA_IM_CH0_Pos 0 2218 #define DMA_IM_CH0_Msk (0x01 << DMA_IM_CH0_Pos) 2219 #define DMA_IM_CH1_Pos 1 2220 #define DMA_IM_CH1_Msk (0x01 << DMA_IM_CH1_Pos) 2221 #define DMA_IM_CH2_Pos 2 2222 #define DMA_IM_CH2_Msk (0x01 << DMA_IM_CH2_Pos) 2223 #define DMA_IM_CH3_Pos 3 2224 #define DMA_IM_CH3_Msk (0x01 << DMA_IM_CH3_Pos) 2225 #define DMA_IM_CH4_Pos 4 2226 #define DMA_IM_CH4_Msk (0x01 << DMA_IM_CH4_Pos) 2227 #define DMA_IM_CH5_Pos 5 2228 #define DMA_IM_CH5_Msk (0x01 << DMA_IM_CH5_Pos) 2229 #define DMA_IM_CH6_Pos 6 2230 #define DMA_IM_CH6_Msk (0x01 << DMA_IM_CH6_Pos) 2231 #define DMA_IM_CH7_Pos 7 2232 #define DMA_IM_CH7_Msk (0x01 << DMA_IM_CH7_Pos) 2233 2234 #define DMA_IF_CH0_Pos 0 2235 #define DMA_IF_CH0_Msk (0x01 << DMA_IF_CH0_Pos) 2236 #define DMA_IF_CH1_Pos 1 2237 #define DMA_IF_CH1_Msk (0x01 << DMA_IF_CH1_Pos) 2238 #define DMA_IF_CH2_Pos 2 2239 #define DMA_IF_CH2_Msk (0x01 << DMA_IF_CH2_Pos) 2240 #define DMA_IF_CH3_Pos 3 2241 #define DMA_IF_CH3_Msk (0x01 << DMA_IF_CH3_Pos) 2242 #define DMA_IF_CH4_Pos 4 2243 #define DMA_IF_CH4_Msk (0x01 << DMA_IF_CH4_Pos) 2244 #define DMA_IF_CH5_Pos 5 2245 #define DMA_IF_CH5_Msk (0x01 << DMA_IF_CH5_Pos) 2246 #define DMA_IF_CH6_Pos 6 2247 #define DMA_IF_CH6_Msk (0x01 << DMA_IF_CH6_Pos) 2248 #define DMA_IF_CH7_Pos 7 2249 #define DMA_IF_CH7_Msk (0x01 << DMA_IF_CH7_Pos) 2250 2251 #define DMA_CR_LEN_Pos 0 //此通道传输总长度，0对应1字节，最大4096字节 2252 #define DMA_CR_LEN_Msk (0xFFF << DMA_CR_LEN_Pos) 2253 #define DMA_CR_RXEN_Pos 16 2254 #define DMA_CR_RXEN_Msk (0x01 << DMA_CR_RXEN_Pos) 2255 #define DMA_CR_TXEN_Pos 17 2256 #define DMA_CR_TXEN_Msk (0x01 << DMA_CR_TXEN_Pos) 2257 #define DMA_CR_AUTORE_Pos 18 //Auto Restart, 通道在传输完成后，是否自动重新启动 2258 #define DMA_CR_AUTORE_Msk (0x01 << DMA_CR_AUTORE_Pos) 2259 2260 #define DMA_AM_SRCAM_Pos 0 //Address Mode 0 地址固定 1 地址递增 2 scatter gather模式 2261 #define DMA_AM_SRCAM_Msk (0x03 << DMA_AM_SRCAM_Pos) 2262 #define DMA_AM_DSTAM_Pos 8 2263 #define DMA_AM_DSTAM_Msk (0x03 << DMA_AM_DSTAM_Pos) 2264 #define DMA_AM_BURST_Pos 16 2265 #define DMA_AM_BURST_Msk (0x01 << DMA_AM_BURST_Pos) 2266 2267 2268 2269 2270 typedef struct { 2271 __IO uint32_t CR; //Control Register 2272 2273 __O uint32_t CMD; //Command Register 2274 2275 __I uint32_t SR; //Status Register 2276 2277 __I uint32_t IF; //Interrupt Flag，读取清零 2278 2279 __IO uint32_t IE; //Interrupt Enable 2280 2281 uint32_t RESERVED; 2282 2283 __IO uint32_t BT0; //Bit Time Register 0 2284 2285 __IO uint32_t BT1; //Bit Time Register 1 2286 2287 uint32_t RESERVED2[3]; 2288 2289 __I uint32_t ALC; //Arbitration Lost Capture, 仲裁丢失捕捉 2290 2291 __I uint32_t ECC; //Error code capture, 错误代码捕捉 2292 2293 __IO uint32_t EWLIM; //Error Warning Limit, 错误报警限制 2294 2295 __IO uint32_t RXERR; //RX错误计数 2296 2297 __IO uint32_t TXERR; //TX错误计数 2298 2299 union { 2300 struct { //在复位时可读写，正常工作模式下不可访问 2301 __IO uint32_t ACR[4]; //Acceptance Check Register, 验收寄存器 2302 2303 __IO uint32_t AMR[4]; //Acceptance Mask Register, 验收屏蔽寄存器；对应位写0，ID必须和验收寄存器匹配 2304 2305 uint32_t RESERVED[5]; 2306 } FILTER; 2307 2308 struct { //在正常工作模式下可读写，复位时不可访问 2309 __IO uint32_t INFO; 2310 2311 __IO uint32_t DATA[12]; 2312 } FRAME; 2313 }; 2314 2315 __I uint32_t RMCNT; //Receive Message Count 2316 2317 uint32_t RESERVED3[66]; 2318 2319 struct { //TXFRAME的读接口 2320 __I uint32_t INFO; 2321 2322 __I uint32_t DATA[12]; 2323 } TXFRAME_R; 2324 } CAN_TypeDef; 2325 2326 2327 #define CAN_CR_RST_Pos 0 2328 #define CAN_CR_RST_Msk (0x01 << CAN_CR_RST_Pos) 2329 #define CAN_CR_LOM_Pos 1 //Listen Only Mode 2330 #define CAN_CR_LOM_Msk (0x01 << CAN_CR_LOM_Pos) 2331 #define CAN_CR_STM_Pos 2 //Self Test Mode, 此模式下即使没有应答，CAN控制器也可以成功发送 2332 #define CAN_CR_STM_Msk (0x01 << CAN_CR_STM_Pos) 2333 #define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 单个验收滤波器（32位） 0 两个验收滤波器（16位） 2334 #define CAN_CR_AFM_Msk (0x01 << CAN_CR_AFM_Pos) 2335 #define CAN_CR_SLEEP_Pos 4 //写1进入睡眠模式，有总线活动或中断时唤醒并自动清零此位 2336 #define CAN_CR_SLEEP_Msk (0x01 << CAN_CR_SLEEP_Pos) 2337 2338 #define CAN_CMD_TXREQ_Pos 0 //Transmission Request 2339 #define CAN_CMD_TXREQ_Msk (0x01 << CAN_CMD_TXREQ_Pos) 2340 #define CAN_CMD_ABTTX_Pos 1 //Abort Transmission 2341 #define CAN_CMD_ABTTX_Msk (0x01 << CAN_CMD_ABTTX_Pos) 2342 #define CAN_CMD_RRB_Pos 2 //Release Receive Buffer 2343 #define CAN_CMD_RRB_Msk (0x01 << CAN_CMD_RRB_Pos) 2344 #define CAN_CMD_CLROV_Pos 3 //Clear Data Overrun 2345 #define CAN_CMD_CLROV_Msk (0x01 << CAN_CMD_CLROV_Pos) 2346 #define CAN_CMD_SRR_Pos 4 //Self Reception Request 2347 #define CAN_CMD_SRR_Msk (0x01 << CAN_CMD_SRR_Pos) 2348 2349 #define CAN_SR_RXDA_Pos 0 //Receive Data Available，接收FIFO中有完整消息可以读取 2350 #define CAN_SR_RXDA_Msk (0x01 << CAN_SR_RXDA_Pos) 2351 #define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun，新接收的信息由于接收FIFO已满而丢掉 2352 #define CAN_SR_RXOV_Msk (0x01 << CAN_SR_RXOV_Pos) 2353 #define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release，0 正在处理前面的发送，现在不能写新的消息 1 可以写入新的消息发送 2354 #define CAN_SR_TXBR_Msk (0x01 << CAN_SR_TXBR_Pos) 2355 #define CAN_SR_TXOK_Pos 3 //Transmit OK，successfully completed 2356 #define CAN_SR_TXOK_Msk (0x01 << CAN_SR_TXOK_Pos) 2357 #define CAN_SR_RXBUSY_Pos 4 //Receive Busy，正在接收 2358 #define CAN_SR_RXBUSY_Msk (0x01 << CAN_SR_RXBUSY_Pos) 2359 #define CAN_SR_TXBUSY_Pos 5 //Transmit Busy，正在发送 2360 #define CAN_SR_TXBUSY_Msk (0x01 << CAN_SR_TXBUSY_Pos) 2361 #define CAN_SR_ERRWARN_Pos 6 //1 至少一个错误计数器达到 Warning Limit 2362 #define CAN_SR_ERRWARN_Msk (0x01 << CAN_SR_ERRWARN_Pos) 2363 #define CAN_SR_BUSOFF_Pos 7 //1 CAN 控制器处于总线关闭状态，没有参与到总线活动 2364 #define CAN_SR_BUSOFF_Msk (0x01 << CAN_SR_BUSOFF_Pos) 2365 2366 #define CAN_IF_RXDA_Pos 0 //IF.RXDA = SR.RXDA & IE.RXDA 2367 #define CAN_IF_RXDA_Msk (0x01 << CAN_IF_RXDA_Pos) 2368 #define CAN_IF_TXBR_Pos 1 //当IE.TXBR=1时，SR.TXBR由0变成1将置位此位 2369 #define CAN_IF_TXBR_Msk (0x01 << CAN_IF_TXBR_Pos) 2370 #define CAN_IF_ERRWARN_Pos 2 //当IE.ERRWARN=1时，SR.ERRWARN或SR.BUSOFF 0-to-1 或 1-to-0将置位此位 2371 #define CAN_IF_ERRWARN_Msk (0x01 << CAN_IF_ERRWARN_Pos) 2372 #define CAN_IF_RXOV_Pos 3 //IF.RXOV = SR.RXOV & IE.RXOV 2373 #define CAN_IF_RXOV_Msk (0x01 << CAN_IF_RXOV_Pos) 2374 #define CAN_IF_WKUP_Pos 4 //当IE.WKUP=1时，在睡眠模式下的CAN控制器检测到总线活动时硬件置位 2375 #define CAN_IF_WKUP_Msk (0x01 << CAN_IF_WKUP_Pos) 2376 #define CAN_IF_ERRPASS_Pos 5 // 2377 #define CAN_IF_ERRPASS_Msk (0x01 << CAN_IF_ERRPASS_Pos) 2378 #define CAN_IF_ARBLOST_Pos 6 //Arbitration Lost，当IE.ARBLOST=1时，CAN控制器丢失仲裁变成接收方时硬件置位 2379 #define CAN_IF_ARBLOST_Msk (0x01 << CAN_IF_ARBLOST_Pos) 2380 #define CAN_IF_BUSERR_Pos 7 //当IE.BUSERR=1时，CAN控制器检测到总线错误时硬件置位 2381 #define CAN_IF_BUSERR_Msk (0x01 << CAN_IF_BUSERR_Pos) 2382 2383 #define CAN_IE_RXDA_Pos 0 2384 #define CAN_IE_RXDA_Msk (0x01 << CAN_IE_RXDA_Pos) 2385 #define CAN_IE_TXBR_Pos 1 2386 #define CAN_IE_TXBR_Msk (0x01 << CAN_IE_TXBR_Pos) 2387 #define CAN_IE_ERRWARN_Pos 2 2388 #define CAN_IE_ERRWARN_Msk (0x01 << CAN_IE_ERRWARN_Pos) 2389 #define CAN_IE_RXOV_Pos 3 2390 #define CAN_IE_RXOV_Msk (0x01 << CAN_IE_RXOV_Pos) 2391 #define CAN_IE_WKUP_Pos 4 2392 #define CAN_IE_WKUP_Msk (0x01 << CAN_IE_WKUP_Pos) 2393 #define CAN_IE_ERRPASS_Pos 5 2394 #define CAN_IE_ERRPASS_Msk (0x01 << CAN_IE_ERRPASS_Pos) 2395 #define CAN_IE_ARBLOST_Pos 6 2396 #define CAN_IE_ARBLOST_Msk (0x01 << CAN_IE_ARBLOST_Pos) 2397 #define CAN_IE_BUSERR_Pos 7 2398 #define CAN_IE_BUSERR_Msk (0x01 << CAN_IE_BUSERR_Pos) 2399 2400 #define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaler，CAN时间单位=2*Tsysclk*(BRP+1) 2401 #define CAN_BT0_BRP_Msk (0x3F << CAN_BT0_BRP_Pos) 2402 #define CAN_BT0_SJW_Pos 6 //Synchronization Jump Width 2403 #define CAN_BT0_SJW_Msk (0x03 << CAN_BT0_SJW_Pos) 2404 2405 #define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CAN时间单位 * (TSEG1+1) 2406 #define CAN_BT1_TSEG1_Msk (0x0F << CAN_BT1_TSEG1_Pos) 2407 #define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CAN时间单位 * (TSEG2+1) 2408 #define CAN_BT1_TSEG2_Msk (0x07 << CAN_BT1_TSEG2_Pos) 2409 #define CAN_BT1_SAM_Pos 7 //采样次数 0: sampled once 1: sampled three times 2410 #define CAN_BT1_SAM_Msk (0x01 << CAN_BT1_SAM_Pos) 2411 2412 #define CAN_ECC_SEGCODE_Pos 0 //Segment Code 2413 #define CAN_ECC_SEGCODE_Msk (0x1F << CAN_ECC_SEGCODE_Pos) 2414 #define CAN_ECC_DIR_Pos 5 //0 error occurred during transmission 1 during reception 2415 #define CAN_ECC_DIR_Msk (0x01 << CAN_ECC_DIR_Pos) 2416 #define CAN_ECC_ERRCODE_Pos 6 //Error Code：0 Bit error 1 Form error 2 Stuff error 3 other error 2417 #define CAN_ECC_ERRCODE_Msk (0x03 << CAN_ECC_ERRCODE_Pos) 2418 2419 #define CAN_INFO_DLC_Pos 0 //Data Length Control 2420 #define CAN_INFO_DLC_Msk (0x0F << CAN_INFO_DLC_Pos) 2421 #define CAN_INFO_RTR_Pos 6 //Remote Frame，1 远程帧 0 数据帧 2422 #define CAN_INFO_RTR_Msk (0x01 << CAN_INFO_RTR_Pos) 2423 #define CAN_INFO_FF_Pos 7 //Frame Format，0 标准帧格式 1 扩展帧格式 2424 #define CAN_INFO_FF_Msk (0x01 << CAN_INFO_FF_Pos) 2425 2426 2427 2428 2429 typedef struct { 2430 __IO uint32_t IE; //[0] 为0的时候，IF[0]维持为0 2431 2432 __IO uint32_t IF; //[0] 当完成指定长度的数据传输时置1，写1清零 2433 2434 __IO uint32_t IM; //[0] 当该寄存器为1时，LCDC的中断不会输出给系统的中断控制寄存器 2435 2436 __IO uint32_t START; 2437 2438 __IO uint32_t SRCADDR; //数据源地址寄存器，必须字对齐（即地址的低2位必须是0） 2439 2440 __IO uint32_t CR0; 2441 2442 __IO uint32_t CR1; 2443 2444 __IO uint32_t PRECMDV; //在MPU接口中，发送数据前，RS拉低的那一拍，数据总线上的值 2445 } LCD_TypeDef; 2446 2447 2448 #define LCD_START_GO_Pos 1 //写1开始传输数据，数据传输结束后自动清零 2449 #define LCD_START_GO_Msk (0x01 << LCD_START_GO_Pos) 2450 #define LCD_START_BURST_Pos 2 2451 #define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos) 2452 2453 #define LCD_CR0_VPIX_Pos 0 //当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767 2454 //当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767 2455 #define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos) 2456 #define LCD_CR0_HPIX_Pos 10 //当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023 2457 //当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023 2458 #define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos) 2459 #define LCD_CR0_DCLK_Pos 20 //0 DOTCLK一直翻转 1 DOTCLK在空闲时停在1 2460 #define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos) 2461 #define LCD_CR0_HLOW_Pos 21 //输出HSYNC低电平持续多少个DOTCLK周期，0表示1个周期 2462 #define LCD_CR0_HLOW_Msk (0x03 << LCD_CR0_HLOW_Pos) 2463 2464 #define LCD_CR1_VFP_Pos 1 2465 #define LCD_CR1_VFP_Msk (0x07 << LCD_CR1_VFP_Pos) 2466 #define LCD_CR1_VBP_Pos 4 2467 #define LCD_CR1_VBP_Msk (0x1F << LCD_CR1_VBP_Pos) 2468 #define LCD_CR1_HFP_Pos 9 2469 #define LCD_CR1_HFP_Msk (0x1F << LCD_CR1_HFP_Pos) 2470 #define LCD_CR1_HBP_Pos 14 2471 #define LCD_CR1_HBP_Msk (0x7F << LCD_CR1_HBP_Pos) 2472 #define LCD_CR1_DCLKDIV_Pos 21 //DOTCLK相对于模块时钟的分频比，0表示2分频，1表示4分频 ... 2473 #define LCD_CR1_DCLKDIV_Msk (0x1F << LCD_CR1_DCLKDIV_Pos) 2474 #define LCD_CR1_DCLKINV_Pos 26 //1 输出DOTCLK反向，应用于用DOTCLK下降沿采样数据的屏 2475 #define LCD_CR1_DCLKINV_Msk (0x01 << LCD_CR1_DCLKINV_Pos) 2476 2477 2478 2479 2480 typedef struct { 2481 __IO uint32_t DMA_MEM_ADDR; 2482 2483 __IO uint32_t BLK; //Block Size and Count 2484 2485 __IO uint32_t ARG; //Argument 2486 2487 __IO uint32_t CMD; //Command 2488 2489 __IO uint32_t RESP[4]; //Response 2490 2491 __IO uint32_t DATA; 2492 2493 __IO uint32_t STAT; 2494 2495 __IO uint32_t CR1; 2496 2497 __IO uint32_t CR2; 2498 2499 __IO uint32_t IF; 2500 2501 __IO uint32_t IM; //Interrupt Mask (Interrupt Flag Enable) 2502 2503 __IO uint32_t IE; //Interrupt Enalbe 2504 2505 __IO uint32_t CMD12ERR; 2506 } SDIO_TypeDef; 2507 2508 2509 #define SDIO_BLK_SIZE_Pos 0 //0x200 512字节 0x400 1024字节 0x800 2048字节 2510 #define SDIO_BLK_SIZE_Msk (0xFFF << SDIO_BLK_SIZE_Pos) 2511 #define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer 1 1块 2 2块 ... ... 2512 #define SDIO_BLK_COUNT_Msk (0xFFF << SDIO_BLK_COUNT_Pos) 2513 2514 #define SDIO_CMD_DMAEN_Pos 0 2515 #define SDIO_CMD_DMAEN_Msk (0x01 << SDIO_CMD_DMAEN_Pos) 2516 #define SDIO_CMD_BLKCNTEN_Pos 1 2517 #define SDIO_CMD_BLKCNTEN_Msk (0x01 << SDIO_CMD_BLKCNTEN_Pos) 2518 #define SDIO_CMD_AUTOCMD12_Pos 2 2519 #define SDIO_CMD_AUTOCMD12_Msk (0x01 << SDIO_CMD_AUTOCMD12_Pos) 2520 #define SDIO_CMD_DIRREAD_Pos 4 //0 Write, Host to Card 1 Read, Card to Host 2521 #define SDIO_CMD_DIRREAD_Msk (0x01 << SDIO_CMD_DIRREAD_Pos) 2522 #define SDIO_CMD_MULTBLK_Pos 5 //0 Single Block 1 Multiple Block 2523 #define SDIO_CMD_MULTBLK_Msk (0x01 << SDIO_CMD_MULTBLK_Pos) 2524 #define SDIO_CMD_RESPTYPE_Pos 16 //响应类型，0 无响应 1 136位响应 2 48位响应 3 48位响应，Busy after response 2525 #define SDIO_CMD_RESPTYPE_Msk (0x03 << SDIO_CMD_RESPTYPE_Pos) 2526 #define SDIO_CMD_CRCCHECK_Pos 19 //Command CRC Check Enable 2527 #define SDIO_CMD_CRCCHECK_Msk (0x01 << SDIO_CMD_CRCCHECK_Pos) 2528 #define SDIO_CMD_IDXCHECK_Pos 20 //Command Index Check Enable 2529 #define SDIO_CMD_IDXCHECK_Msk (0x01 << SDIO_CMD_IDXCHECK_Pos) 2530 #define SDIO_CMD_HAVEDATA_Pos 21 //0 No Data Present 1 Data Present 2531 #define SDIO_CMD_HAVEDATA_Msk (0x01 << SDIO_CMD_HAVEDATA_Pos) 2532 #define SDIO_CMD_CMDTYPE_Pos 22 //0 NORMAL 1 SUSPEND 2 RESUME 3 ABORT 2533 #define SDIO_CMD_CMDTYPE_Msk (0x03 << SDIO_CMD_CMDTYPE_Pos) 2534 #define SDIO_CMD_CMDINDX_Pos 24 //Command Index，CMD0-63、ACMD0-63 2535 #define SDIO_CMD_CMDINDX_Msk (0x3F << SDIO_CMD_CMDINDX_Pos) 2536 2537 #define SDIO_CR1_4BIT_Pos 1 //1 4 bit mode 0 1 bit mode 2538 #define SDIO_CR1_4BIT_Msk (0x01 << SDIO_CR1_4BIT_Pos) 2539 #define SDIO_CR1_8BIT_Pos 5 //1 8 bit mode is selected 0 8 bit mode is not selected 2540 #define SDIO_CR1_8BIT_Msk (0x01 << SDIO_CR1_8BIT_Pos) 2541 #define SDIO_CR1_CDBIT_Pos 6 //0 No Card 1 Card Inserted 2542 #define SDIO_CR1_CDBIT_Msk (0x01 << SDIO_CR1_CDBIT_Pos) 2543 #define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBIT位 0 SD_Detect引脚 2544 #define SDIO_CR1_CDSRC_Msk (0x01 << SDIO_CR1_CDSRC_Pos) 2545 #define SDIO_CR1_PWRON_Pos 8 //1 Power on 0 Power off 2546 #define SDIO_CR1_PWRON_Msk (0x01 << SDIO_CR1_PWRON_Pos) 2547 #define SDIO_CR1_VOLT_Pos 9 //7 3.3V 6 3.0V 5 1.8V 2548 #define SDIO_CR1_VOLT_Msk (0x07 << SDIO_CR1_VOLT_Pos) 2549 2550 #define SDIO_CR2_CLKEN_Pos 0 //Internal Clock Enable 2551 #define SDIO_CR2_CLKEN_Msk (0x01 << SDIO_CR2_CLKEN_Pos) 2552 #define SDIO_CR2_CLKRDY_Pos 1 //Internal Clock Stable/Ready 2553 #define SDIO_CR2_CLKRDY_Msk (0x01 << SDIO_CR2_CLKRDY_Pos) 2554 #define SDIO_CR2_SDCLKEN_Pos 2 //SDCLK Enable 2555 #define SDIO_CR2_SDCLKEN_Msk (0x01 << SDIO_CR2_SDCLKEN_Pos) 2556 #define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 不分频 0x01 2分频 0x02 4分频 0x04 8分频 0x08 16分频 ... 0x80 256分频 2557 #define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos) 2558 #define SDIO_CR2_TIMEOUT_Pos 16 //0 TMCLK*2^13 1 TMCLK*2^14 ... 14 TMCLK*2^27 2559 #define SDIO_CR2_TIMEOUT_Msk (0x0F << SDIO_CR2_TIMEOUT_Pos) 2560 #define SDIO_CR2_RSTALL_Pos 24 //Software Reset for All 2561 #define SDIO_CR2_RSTALL_Msk (0x01 << SDIO_CR2_RSTALL_Pos) 2562 #define SDIO_CR2_RSTCMD_Pos 25 //Software Reset for CMD Line 2563 #define SDIO_CR2_RSTCMD_Msk (0x01 << SDIO_CR2_RSTCMD_Pos) 2564 #define SDIO_CR2_RSTDAT_Pos 26 //Software Reset for DAT Line 2565 #define SDIO_CR2_RSTDAT_Msk (0x01 << SDIO_CR2_RSTDAT_Pos) 2566 2567 #define SDIO_IF_CMDDONE_Pos 0 2568 #define SDIO_IF_CMDDONE_Msk (0x01 << SDIO_IF_CMDDONE_Pos) 2569 #define SDIO_IF_TRXDONE_Pos 1 2570 #define SDIO_IF_TRXDONE_Msk (0x01 << SDIO_IF_TRXDONE_Pos) 2571 #define SDIO_IF_BLKGAP_Pos 2 2572 #define SDIO_IF_BLKGAP_Msk (0x01 << SDIO_IF_BLKGAP_Pos) 2573 #define SDIO_IF_DMADONE_Pos 3 2574 #define SDIO_IF_DMADONE_Msk (0x01 << SDIO_IF_DMADONE_Pos) 2575 #define SDIO_IF_BUFWRRDY_Pos 4 2576 #define SDIO_IF_BUFWRRDY_Msk (0x01 << SDIO_IF_BUFWRRDY_Pos) 2577 #define SDIO_IF_BUFRDRDY_Pos 5 2578 #define SDIO_IF_BUFRDRDY_Msk (0x01 << SDIO_IF_BUFRDRDY_Pos) 2579 #define SDIO_IF_CARDINSR_Pos 6 2580 #define SDIO_IF_CARDINSR_Msk (0x01 << SDIO_IF_CARDINSR_Pos) 2581 #define SDIO_IF_CARDRMOV_Pos 7 2582 #define SDIO_IF_CARDRMOV_Msk (0x01 << SDIO_IF_CARDRMOV_Pos) 2583 #define SDIO_IF_CARD_Pos 8 2584 #define SDIO_IF_CARD_Msk (0x01 << SDIO_IF_CARD_Pos) 2585 #define SDIO_IF_ERROR_Pos 15 2586 #define SDIO_IF_ERROR_Msk (0x01 << SDIO_IF_ERROR_Pos) 2587 #define SDIO_IF_CMDTIMEOUT_Pos 16 2588 #define SDIO_IF_CMDTIMEOUT_Msk (0x01 << SDIO_IF_CMDTIMEOUT_Pos) 2589 #define SDIO_IF_CMDCRCERR_Pos 17 2590 #define SDIO_IF_CMDCRCERR_Msk (0x01 << SDIO_IF_CMDCRCERR_Pos) 2591 #define SDIO_IF_CMDENDERR_Pos 18 2592 #define SDIO_IF_CMDENDERR_Msk (0x01 << SDIO_IF_CMDENDCERR_Pos) 2593 #define SDIO_IF_CMDIDXERR_Pos 19 2594 #define SDIO_IF_CMDIDXERR_Msk (0x01 << SDIO_IF_CMDIDXCERR_Pos) 2595 #define SDIO_IF_DATTIMEOUT_Pos 20 2596 #define SDIO_IF_DATTIMEOUT_Msk (0x01 << SDIO_IF_DATTIMEOUT_Pos) 2597 #define SDIO_IF_DATCRCERR_Pos 21 2598 #define SDIO_IF_DATCRCERR_Msk (0x01 << SDIO_IF_DATCRCERR_Pos) 2599 #define SDIO_IF_DATENDERR_Pos 22 2600 #define SDIO_IF_DATENDERR_Msk (0x01 << SDIO_IF_DATENDCERR_Pos) 2601 #define SDIO_IF_CURLIMERR_Pos 23 2602 #define SDIO_IF_CURLIMERR_Msk (0x01 << SDIO_IF_CURLIMERR_Pos) 2603 #define SDIO_IF_CMD12ERR_Pos 24 2604 #define SDIO_IF_CMD12ERR_Msk (0x01 << SDIO_IF_CMD12ERR_Pos) 2605 #define SDIO_IF_DMAERR_Pos 25 2606 #define SDIO_IF_DMAERR_Msk (0x01 << SDIO_IF_DMAERR_Pos) 2607 #define SDIO_IF_RESPERR_Pos 28 2608 #define SDIO_IF_RESPERR_Msk (0x01 << SDIO_IF_RESPERR_Pos) 2609 2610 #define SDIO_IE_CMDDONE_Pos 0 //Command Complete Status Enable 2611 #define SDIO_IE_CMDDONE_Msk (0x01 << SDIO_IE_CMDDONE_Pos) 2612 #define SDIO_IE_TRXDONE_Pos 1 //Transfer Complete Status Enable 2613 #define SDIO_IE_TRXDONE_Msk (0x01 << SDIO_IE_TRXDONE_Pos) 2614 #define SDIO_IE_BLKGAP_Pos 2 //Block Gap Event Status Enable 2615 #define SDIO_IE_BLKGAP_Msk (0x01 << SDIO_IE_BLKGAP_Pos) 2616 #define SDIO_IE_DMADONE_Pos 3 //DMA Interrupt Status Enable 2617 #define SDIO_IE_DMADONE_Msk (0x01 << SDIO_IE_DMADONE_Pos) 2618 #define SDIO_IE_BUFWRRDY_Pos 4 //Buffer Write Ready Status Enable 2619 #define SDIO_IE_BUFWRRDY_Msk (0x01 << SDIO_IE_BUFWRRDY_Pos) 2620 #define SDIO_IE_BUFRDRDY_Pos 5 //Buffer Read Ready Status Enable 2621 #define SDIO_IE_BUFRDRDY_Msk (0x01 << SDIO_IE_BUFRDRDY_Pos) 2622 #define SDIO_IE_CARDINSR_Pos 6 //Card Insertion Status Enable 2623 #define SDIO_IE_CARDINSR_Msk (0x01 << SDIO_IE_CARDINSR_Pos) 2624 #define SDIO_IE_CARDRMOV_Pos 7 //Card Removal Status Enable 2625 #define SDIO_IE_CARDRMOV_Msk (0x01 << SDIO_IE_CARDRMOV_Pos) 2626 #define SDIO_IE_CARD_Pos 8 2627 #define SDIO_IE_CARD_Msk (0x01 << SDIO_IE_CARD_Pos) 2628 #define SDIO_IE_CMDTIMEOUT_Pos 16 //Command Timeout Error Status Enable 2629 #define SDIO_IE_CMDTIMEOUT_Msk (0x01 << SDIO_IE_CMDTIMEOUT_Pos) 2630 #define SDIO_IE_CMDCRCERR_Pos 17 //Command CRC Error Status Enable 2631 #define SDIO_IE_CMDCRCERR_Msk (0x01 << SDIO_IE_CMDCRCERR_Pos) 2632 #define SDIO_IE_CMDENDERR_Pos 18 //Command End Bit Error Status Enable 2633 #define SDIO_IE_CMDENDERR_Msk (0x01 << SDIO_IE_CMDENDCERR_Pos) 2634 #define SDIO_IE_CMDIDXERR_Pos 19 //Command Index Error Status Enable 2635 #define SDIO_IE_CMDIDXERR_Msk (0x01 << SDIO_IE_CMDIDXCERR_Pos) 2636 #define SDIO_IE_DATTIMEOUT_Pos 20 //Data Timeout Error Status Enable 2637 #define SDIO_IE_DATTIMEOUT_Msk (0x01 << SDIO_IE_DATTIMEOUT_Pos) 2638 #define SDIO_IE_DATCRCERR_Pos 21 //Data CRC Error Status Enable 2639 #define SDIO_IE_DATCRCERR_Msk (0x01 << SDIO_IE_DATCRCERR_Pos) 2640 #define SDIO_IE_DATENDERR_Pos 22 //Data End Bit Error Status Enable 2641 #define SDIO_IE_DATENDERR_Msk (0x01 << SDIO_IE_DATENDCERR_Pos) 2642 #define SDIO_IE_CURLIMERR_Pos 23 //Current Limit Error Status Enable 2643 #define SDIO_IE_CURLIMERR_Msk (0x01 << SDIO_IE_CURLIMERR_Pos) 2644 #define SDIO_IE_CMD12ERR_Pos 24 //Auto CMD12 Error Status Enable 2645 #define SDIO_IE_CMD12ERR_Msk (0x01 << SDIO_IE_CMD12ERR_Pos) 2646 #define SDIO_IE_DMAERR_Pos 25 //ADMA Error Status Enable 2647 #define SDIO_IE_DMAERR_Msk (0x01 << SDIO_IE_DMAERR_Pos) 2648 #define SDIO_IE_RESPERR_Pos 28 //Target Response Error Status Enable 2649 #define SDIO_IE_RESPERR_Msk (0x01 << SDIO_IE_RESPERR_Pos) 2650 2651 #define SDIO_IM_CMDDONE_Pos 0 2652 #define SDIO_IM_CMDDONE_Msk (0x01 << SDIO_IM_CMDDONE_Pos) 2653 #define SDIO_IM_TRXDONE_Pos 1 2654 #define SDIO_IM_TRXDONE_Msk (0x01 << SDIO_IM_TRXDONE_Pos) 2655 #define SDIO_IM_BLKGAP_Pos 2 2656 #define SDIO_IM_BLKGAP_Msk (0x01 << SDIO_IM_BLKGAP_Pos) 2657 #define SDIO_IM_DMADONE_Pos 3 2658 #define SDIO_IM_DMADONE_Msk (0x01 << SDIO_IM_DMADONE_Pos) 2659 #define SDIO_IM_BUFWRRDY_Pos 4 2660 #define SDIO_IM_BUFWRRDY_Msk (0x01 << SDIO_IM_BUFWRRDY_Pos) 2661 #define SDIO_IM_BUFRDRDY_Pos 5 2662 #define SDIO_IM_BUFRDRDY_Msk (0x01 << SDIO_IM_BUFRDRDY_Pos) 2663 #define SDIO_IM_CARDINSR_Pos 6 2664 #define SDIO_IM_CARDINSR_Msk (0x01 << SDIO_IM_CARDINSR_Pos) 2665 #define SDIO_IM_CARDRMOV_Pos 7 2666 #define SDIO_IM_CARDRMOV_Msk (0x01 << SDIO_IM_CARDRMOV_Pos) 2667 #define SDIO_IM_CARD_Pos 8 2668 #define SDIO_IM_CARD_Msk (0x01 << SDIO_IM_CARD_Pos) 2669 #define SDIO_IM_CMDTIMEOUT_Pos 16 2670 #define SDIO_IM_CMDTIMEOUT_Msk (0x01 << SDIO_IM_CMDTIMEOUT_Pos) 2671 #define SDIO_IM_CMDCRCERR_Pos 17 2672 #define SDIO_IM_CMDCRCERR_Msk (0x01 << SDIO_IM_CMDCRCERR_Pos) 2673 #define SDIO_IM_CMDENDERR_Pos 18 2674 #define SDIO_IM_CMDENDERR_Msk (0x01 << SDIO_IM_CMDENDCERR_Pos) 2675 #define SDIO_IM_CMDIDXERR_Pos 19 2676 #define SDIO_IM_CMDIDXERR_Msk (0x01 << SDIO_IM_CMDIDXCERR_Pos) 2677 #define SDIO_IM_DATTIMEOUT_Pos 20 2678 #define SDIO_IM_DATTIMEOUT_Msk (0x01 << SDIO_IM_DATTIMEOUT_Pos) 2679 #define SDIO_IM_DATCRCERR_Pos 21 2680 #define SDIO_IM_DATCRCERR_Msk (0x01 << SDIO_IM_DATCRCERR_Pos) 2681 #define SDIO_IM_DATENDERR_Pos 22 2682 #define SDIO_IM_DATENDERR_Msk (0x01 << SDIO_IM_DATENDCERR_Pos) 2683 #define SDIO_IM_CURLIMERR_Pos 23 2684 #define SDIO_IM_CURLIMERR_Msk (0x01 << SDIO_IM_CURLIMERR_Pos) 2685 #define SDIO_IM_CMD12ERR_Pos 24 2686 #define SDIO_IM_CMD12ERR_Msk (0x01 << SDIO_IM_CMD12ERR_Pos) 2687 #define SDIO_IM_DMAERR_Pos 25 2688 #define SDIO_IM_DMAERR_Msk (0x01 << SDIO_IM_DMAERR_Pos) 2689 #define SDIO_IM_RESPERR_Pos 28 2690 #define SDIO_IM_RESPERR_Msk (0x01 << SDIO_IM_RESPERR_Pos) 2691 2692 #define SDIO_CMD12ERR_NE_Pos 0 //Auto CMD12 not Executed 2693 #define SDIO_CMD12ERR_NE_Msk (0x01 << SDIO_CMD12ERR_NE_Pos) 2694 #define SDIO_CMD12ERR_TO_Pos 1 //Auto CMD12 Timeout Error 2695 #define SDIO_CMD12ERR_TO_Msk (0x01 << SDIO_CMD12ERR_TO_Pos) 2696 #define SDIO_CMD12ERR_CRC_Pos 2 //Auto CMD12 CRC Error 2697 #define SDIO_CMD12ERR_CRC_Msk (0x01 << SDIO_CMD12ERR_CRC_Pos) 2698 #define SDIO_CMD12ERR_END_Pos 3 //Auto CMD12 End Bit Error 2699 #define SDIO_CMD12ERR_END_Msk (0x01 << SDIO_CMD12ERR_END_Pos) 2700 #define SDIO_CMD12ERR_INDEX_Pos 4 //Auto CMD12 Index Error 2701 #define SDIO_CMD12ERR_INDEX_Msk (0x01 << SDIO_CMD12ERR_INDEX_Pos) 2702 2703 2704 2705 2706 typedef struct { 2707 __IO uint32_t DATA; 2708 __IO uint32_t ADDR; 2709 __IO uint32_t ERASE; 2710 __IO uint32_t CACHE; 2711 __IO uint32_t CFG0; 2712 __IO uint32_t CFG1; 2713 __IO uint32_t CFG2; 2714 __IO uint32_t CFG3; 2715 __IO uint32_t STAT; 2716 } FLASH_Typedef; 2717 2718 2719 #define FLASH_ERASE_REQ_Pos 31 2720 #define FLASH_ERASE_REQ_Msk (0x01u<< FLASH_ERASE_REQ_Pos) 2721 2722 #define FLASH_CACHE_PROG_Pos 2 2723 #define FLASH_CACHE_PROG_Msk (0x01 << FLASH_CACHE_PROG_Pos) 2724 #define FLASH_CACHE_CLEAR_Pos 3 2725 #define FLASH_CACHE_CLEAR_Msk (0x01 << FLASH_CACHE_CLEAR_Pos) 2726 2727 #define FLASH_STAT_ERASE_GOING_Pos 0 2728 #define FLASH_STAT_ERASE_GOING_Msk (0X01 << FLASH_STAT_ERASE_GOING_Pos) 2729 #define FLASH_STAT_PROG_GOING_Pos 1 2730 #define FLASH_STAT_PROG_GOING_Msk (0x01 << FLASH_STAT_PROG_GOING_Pos) 2731 #define FALSH_STAT_FIFO_EMPTY_Pos 3 2732 #define FLASH_STAT_FIFO_EMPTY_Msk (0x01 << FALSH_STAT_FIFO_EMPTY_Pos) 2733 #define FALSH_STAT_FIFO_FULL_Pos 4 2734 #define FLASH_STAT_FIFO_FULL_Msk (0x01 << FALSH_STAT_FIFO_FULL_Pos) 2735 2736 2737 2738 2739 typedef struct { 2740 __IO uint32_t CR; 2741 } SRAMC_TypeDef; 2742 2743 2744 #define SRAMC_CR_RWTIME_Pos 0 //读写操作持续多少个时钟周期。0表示1个时钟周期。最小设置为4 2745 #define SRAMC_CR_RWTIME_Msk (0x0F << SRAMC_CR_RWTIME_Pos) 2746 #define SRAMC_CR_BYTEIF_Pos 4 //外部SRAM数据宽度，0 16位 1 8位 2747 #define SRAMC_CR_BYTEIF_Msk (0x01 << SRAMC_CR_BYTEIF_Pos) 2748 #define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]为地址线 0 ADDR[23]为高字节使能，ADDR[22]为低字节使能 2749 #define SRAMC_CR_HBLBDIS_Msk (0x01 << SRAMC_CR_HBLBDIS_Pos) 2750 2751 2752 2753 typedef struct { 2754 __IO uint32_t CR0; 2755 2756 __IO uint32_t CR1; 2757 2758 __IO uint32_t REFRESH; 2759 2760 __IO uint32_t NOPNUM; //[15:0] 初始化完成后，在正常操作之前，发送多少个NOP命令 2761 2762 __IO uint32_t LATCH; 2763 2764 __IO uint32_t REFDONE; //[0] Frefresh Done，上电初始化完成 2765 } SDRAMC_TypeDef; 2766 2767 2768 #define SDRAMC_CR0_BURSTLEN_Pos 0 //必须取2，表示Burst Length为4 2769 #define SDRAMC_CR0_BURSTLEN_Msk (0x07 << SDRAMC_CR0_BURSTLEN_Pos) 2770 #define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latency， 2 2 3 3 2771 #define SDRAMC_CR0_CASDELAY_Msk (0x07 << SDRAMC_CR0_CASDELAY_Pos) 2772 2773 #define SDRAMC_CR1_TRP_Pos 0 2774 #define SDRAMC_CR1_TRP_Msk (0x07 << SDRAMC_CR1_TRP_Pos) 2775 #define SDRAMC_CR1_TRCD_Pos 3 2776 #define SDRAMC_CR1_TRCD_Msk (0x07 << SDRAMC_CR1_TRCD_Pos) 2777 #define SDRAMC_CR1_TRC_Pos 6 2778 #define SDRAMC_CR1_TRC_Msk (0x0F << SDRAMC_CR1_TRC_Pos) 2779 #define SDRAMC_CR1_TRAS_Pos 10 2780 #define SDRAMC_CR1_TRAS_Msk (0x07 << SDRAMC_CR1_TRAS_Pos) 2781 #define SDRAMC_CR1_TRRD_Pos 13 2782 #define SDRAMC_CR1_TRRD_Msk (0x03 << SDRAMC_CR1_TRRD_Pos) 2783 #define SDRAMC_CR1_TMRD_Pos 15 2784 #define SDRAMC_CR1_TMRD_Msk (0x07 << SDRAMC_CR1_TMRD_Pos) 2785 #define SDRAMC_CR1_32BIT_Pos 18 //SDRAMC的接口数据位宽，1 32bit 0 16bit 2786 #define SDRAMC_CR1_32BIT_Msk (0x01 << SDRAMC_CR1_32BIT_Pos) 2787 #define SDRAMC_CR1_BANK_Pos 19 //SDRAM每个颗粒有几个bank，0 2 banks 1 4 banks 2788 #define SDRAMC_CR1_BANK_Msk (0x01 << SDRAMC_CR1_BANK_Pos) 2789 #define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAM颗粒的位宽，1 32bit 0 16bit 2790 #define SDRAMC_CR1_CELL32BIT_Msk (0x01 << SDRAMC_CR1_CELL32BIT_Pos) 2791 #define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAM颗粒的容量，0 64Mb 1 128Mb 2 256Mb 3 16Mb 2792 #define SDRAMC_CR1_CELLSIZE_Msk (0x03 << SDRAMC_CR1_CELLSIZE_Pos) 2793 2794 #define SDRAMC_REFRESH_RATE_Pos 0 2795 #define SDRAMC_REFRESH_RATE_Msk (0xFFF << SDRAMC_REFRESH_RATE_Pos) 2796 #define SDRAMC_REFRESH_EN_Pos 12 2797 #define SDRAMC_REFRESH_EN_Msk (0x01 << SDRAMC_REFRESH_EN_Pos) 2798 2799 #define SDRAMC_LATCH_INEDGE_Pos 0 //哪个沿来锁存从SDRAM中读回的数据，0 上升沿 1 下降沿 2800 #define SDRAMC_LATCH_INEDGE_Msk (0x01 << SDRAMC_LATCH_INEDGE_Pos) 2801 #define SDRAMC_LATCH_OUTEDGE_Pos 1 //哪个沿去锁存送给SDRAM的数据，1 上升沿 0 下降沿 2802 #define SDRAMC_LATCH_OUTEDGE_Msk (0x01 << SDRAMC_LATCH_OUTEDGE_Pos) 2803 #define SDRAMC_LATCH_WAITST_Pos 2 2804 #define SDRAMC_LATCH_WAITST_Msk (0x01 << SDRAMC_LATCH_WAITST_Pos) 2805 2806 2807 2808 2809 typedef struct { 2810 __IO uint32_t IE; 2811 2812 __IO uint32_t IF; //写1清零 2813 2814 __IO uint32_t IM; 2815 2816 __IO uint32_t CR; 2817 2818 __IO uint32_t ADDR; 2819 2820 __IO uint32_t CMD; 2821 } NORFLC_TypeDef; 2822 2823 2824 #define NORFLC_IE_FINISH_Pos 0 2825 #define NORFLC_IE_FINISH_Msk (0x01 << NORFLC_IE_FINISH_Pos) 2826 #define NORFLC_IE_TIMEOUT_Pos 1 2827 #define NORFLC_IE_TIMEOUT_Msk (0x01 << NORFLC_IE_TIMEOUT_Pos) 2828 2829 #define NORFLC_IF_FINISH_Pos 0 2830 #define NORFLC_IF_FINISH_Msk (0x01 << NORFLC_IF_FINISH_Pos) 2831 #define NORFLC_IF_TIMEOUT_Pos 1 2832 #define NORFLC_IF_TIMEOUT_Msk (0x01 << NORFLC_IF_TIMEOUT_Pos) 2833 2834 #define NORFLC_IM_FINISH_Pos 0 2835 #define NORFLC_IM_FINISH_Msk (0x01 << NORFLC_IM_FINISH_Pos) 2836 #define NORFLC_IM_TIMEOUT_Pos 1 2837 #define NORFLC_IM_TIMEOUT_Msk (0x01 << NORFLC_IM_TIMEOUT_Pos) 2838 2839 #define NORFLC_CR_RDTIME_Pos 0 //Oen下降沿后多少个时钟周期后采样读回的数据。0表示1个时钟周期 2840 #define NORFLC_CR_RDTIME_Msk (0x1F << NORFLC_CR_RDTIME_Pos) 2841 #define NORFLC_CR_WRTIME_Pos 5 //输出Wen的低电平宽度。0表示1个时钟周期 2842 #define NORFLC_CR_WRTIME_Msk (0x07 << NORFLC_CR_WRTIME_Pos) 2843 #define NORFLC_CR_BYTEIF_Pos 8 //外部NOR FLASH数据宽度，1 8位 0 16位 2844 #define NORFLC_CR_BYTEIF_Msk (0x01 << NORFLC_CR_BYTEIF_Pos) 2845 2846 #define NORFLC_CMD_DATA_Pos 0 //在PROGRAM命令中，DATA是要写入NOR FLASH的数据；在READ命令中，DATA是从NOR FLASH读回的数据 2847 #define NORFLC_CMD_DATA_Msk (0xFFFF << NORFLC_CMD_DATA_Pos) 2848 #define NORFLC_CMD_CMD_Pos 16 //需要执行的命令，0 READ 1 RESET 2 AUTOMATIC SELECT 3 PROGRAM 4 CHIP ERASE 5 SECTOR ERASE 2849 #define NORFLC_CMD_CMD_Msk (0x07 << NORFLC_CMD_CMD_Pos) 2850 2851 2852 2853 2854 typedef struct { 2855 __IO uint32_t CR; 2856 2857 __O uint32_t DATAIN; 2858 2859 __IO uint32_t INIVAL; 2860 2861 __I uint32_t RESULT; 2862 } CRC_TypeDef; 2863 2864 2865 #define CRC_CR_EN_Pos 0 2866 #define CRC_CR_EN_Msk (0x01 << CRC_CR_EN_Pos) 2867 #define CRC_CR_OREV_Pos 1 //输出结果是否翻转 2868 #define CRC_CR_OREV_Msk (0x01 << CRC_CR_OREV_Pos) 2869 #define CRC_CR_ONOT_Pos 2 //输出结果是否取反 2870 #define CRC_CR_ONOT_Msk (0x01 << CRC_CR_ONOT_Pos) 2871 #define CRC_CR_CRC16_Pos 3 //1 CRC16 0 CRC32 2872 #define CRC_CR_CRC16_Msk (0x01 << CRC_CR_CRC16_Pos) 2873 #define CRC_CR_IBITS_Pos 4 //输入数据有效位数 0 32位 1 16位 2 8位 2874 #define CRC_CR_IBITS_Msk (0x03 << CRC_CR_IBITS_Pos) 2875 2876 2877 2878 2879 typedef struct { 2880 __IO uint32_t MINSEC; //分秒计数 2881 2882 __IO uint32_t DATHUR; //日时计数 2883 2884 __IO uint32_t MONDAY; //月周计数 2885 2886 __IO uint32_t YEAR; //[11:0] 年计数，支持1901-2199 2887 2888 __IO uint32_t MINSECAL; //分秒闹铃设置 2889 2890 __IO uint32_t DAYHURAL; //周时闹铃设置 2891 2892 __IO uint32_t LOAD; //将设置寄存器中的值同步到RTC中，同步完成自动清零 2893 2894 __IO uint32_t IE; 2895 2896 __IO uint32_t IF; //写1清零 2897 2898 __IO uint32_t EN; //[0] 1 RTC使能 2899 2900 __IO uint32_t CFGABLE; //[0] 1 RTC可配置 2901 2902 __IO uint32_t TRIM; //时钟调整 2903 2904 __IO uint32_t TRIMM; //时钟微调整 2905 } RTC_TypeDef; 2906 2907 2908 #define RTC_LOAD_TIME_Pos 0 2909 #define RTC_LOAD_TIME_Msk (0x01 << RTC_LOAD_TIME_Pos) 2910 #define RTC_LOAD_ALARM_Pos 1 2911 #define RTC_LOAD_ALARM_Msk (0x01 << RTC_LOAD_ALARM_Pos) 2912 2913 #define RTC_MINSEC_SEC_Pos 0 //秒计数，取值0--59 2914 #define RTC_MINSEC_SEC_Msk (0x3F << RTC_MINSEC_SEC_Pos) 2915 #define RTC_MINSEC_MIN_Pos 6 //分钟计数，取值0--59 2916 #define RTC_MINSEC_MIN_Msk (0x3F << RTC_MINSEC_MIN_Pos) 2917 2918 #define RTC_DATHUR_HOUR_Pos 0 //小时计数，取值0--23 2919 #define RTC_DATHUR_HOUR_Msk (0x1F << RTC_DATHUR_HOUR_Pos) 2920 #define RTC_DATHUR_DATE_Pos 5 //date of month，取值1--31 2921 #define RTC_DATHUR_DATE_Msk (0x1F << RTC_DATHUR_DATE_Pos) 2922 2923 #define RTC_MONDAY_DAY_Pos 0 //day of week，取值0--6 2924 #define RTC_MONDAY_DAY_Msk (0x07 << RTC_MONDAY_DAY_Pos) 2925 #define RTC_MONDAY_MON_Pos 3 //月份计数，取值1--12 2926 #define RTC_MONDAY_MON_Msk (0x0F << RTC_MONDAY_MON_Pos) 2927 2928 #define RTC_MINSECAL_SEC_Pos 0 //闹钟秒设置 2929 #define RTC_MINSECAL_SEC_Msk (0x3F << RTC_MINSECAL_SEC_Pos) 2930 #define RTC_MINSECAL_MIN_Pos 6 //闹钟分钟设置 2931 #define RTC_MINSECAL_MIN_Msk (0x3F << RTC_MINSECAL_MIN_Pos) 2932 2933 #define RTC_DAYHURAL_HOUR_Pos 0 //闹钟小时设置 2934 #define RTC_DAYHURAL_HOUR_Msk (0x1F << RTC_DAYHURAL_HOUR_Pos) 2935 #define RTC_DAYHURAL_SUN_Pos 5 //周日闹钟有效 2936 #define RTC_DAYHURAL_SUN_Msk (0x01 << RTC_DAYHURAL_SUN_Pos) 2937 #define RTC_DAYHURAL_MON_Pos 6 //周一闹钟有效 2938 #define RTC_DAYHURAL_MON_Msk (0x01 << RTC_DAYHURAL_MON_Pos) 2939 #define RTC_DAYHURAL_TUE_Pos 7 //周二闹钟有效 2940 #define RTC_DAYHURAL_TUE_Msk (0x01 << RTC_DAYHURAL_TUE_Pos) 2941 #define RTC_DAYHURAL_WED_Pos 8 //周三闹钟有效 2942 #define RTC_DAYHURAL_WED_Msk (0x01 << RTC_DAYHURAL_WED_Pos) 2943 #define RTC_DAYHURAL_THU_Pos 9 //周四闹钟有效 2944 #define RTC_DAYHURAL_THU_Msk (0x01 << RTC_DAYHURAL_THU_Pos) 2945 #define RTC_DAYHURAL_FRI_Pos 10 //周五闹钟有效 2946 #define RTC_DAYHURAL_FRI_Msk (0x01 << RTC_DAYHURAL_FRI_Pos) 2947 #define RTC_DAYHURAL_SAT_Pos 11 //周六闹钟有效 2948 #define RTC_DAYHURAL_SAT_Msk (0x01 << RTC_DAYHURAL_SAT_Pos) 2949 2950 #define RTC_IE_SEC_Pos 0 //秒中断使能 2951 #define RTC_IE_SEC_Msk (0x01 << RTC_IE_SEC_Pos) 2952 #define RTC_IE_MIN_Pos 1 2953 #define RTC_IE_MIN_Msk (0x01 << RTC_IE_MIN_Pos) 2954 #define RTC_IE_HOUR_Pos 2 2955 #define RTC_IE_HOUR_Msk (0x01 << RTC_IE_HOUR_Pos) 2956 #define RTC_IE_DATE_Pos 3 2957 #define RTC_IE_DATE_Msk (0x01 << RTC_IE_DATE_Pos) 2958 #define RTC_IE_ALARM_Pos 4 2959 #define RTC_IE_ALARM_Msk (0x01 << RTC_IE_ALARM_Pos) 2960 2961 #define RTC_IF_SEC_Pos 0 //写1清零 2962 #define RTC_IF_SEC_Msk (0x01 << RTC_IF_SEC_Pos) 2963 #define RTC_IF_MIN_Pos 1 2964 #define RTC_IF_MIN_Msk (0x01 << RTC_IF_MIN_Pos) 2965 #define RTC_IF_HOUR_Pos 2 2966 #define RTC_IF_HOUR_Msk (0x01 << RTC_IF_HOUR_Pos) 2967 #define RTC_IF_DATE_Pos 3 2968 #define RTC_IF_DATE_Msk (0x01 << RTC_IF_DATE_Pos) 2969 #define RTC_IF_ALARM_Pos 4 2970 #define RTC_IF_ALARM_Msk (0x01 << RTC_IF_ALARM_Pos) 2971 2972 #define RTC_TRIM_ADJ_Pos 0 //用于调整BASECNT的计数周期，默认为32768，如果DEC为1，则计数周期调整为32768-ADJ，否则调整为32768+ADJ 2973 #define RTC_TRIM_ADJ_Msk (0xFF << RTC_TRIM_ADJ_Pos) 2974 #define RTC_TRIM_DEC_Pos 8 2975 #define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos) 2976 2977 #define RTC_TRIMM_CYCLE_Pos 0 //用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1 2978 //cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推 2979 #define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos) 2980 #define RTC_TRIMM_INC_Pos 3 2981 #define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos) 2982 2983 2984 2985 2986 typedef struct { 2987 __IO uint32_t LOAD; //喂狗使计数器装载LOAD值 2988 2989 __I uint32_t VALUE; 2990 2991 __IO uint32_t CR; 2992 2993 __IO uint32_t IF; //计数到0时硬件置位，软件写1清除标志 2994 2995 __IO uint32_t FEED; //写0x55喂狗 2996 } WDT_TypeDef; 2997 2998 2999 #define WDT_CR_EN_Pos 0 3000 #define WDT_CR_EN_Msk (0x01 << WDT_CR_EN_Pos) 3001 #define WDT_CR_RSTEN_Pos 1 3002 #define WDT_CR_RSTEN_Msk (0x01 << WDT_CR_RSTEN_Pos) 3003 3004 3005 /******************************************************************************/ 3006 /* Peripheral memory map */ 3007 /******************************************************************************/ 3008 #define RAM_BASE 0x20000000 3009 #define AHB_BASE 0x40000000 3010 #define APB_BASE 0x40010000 3011 3012 #define NORFLC_BASE 0x60000000 3013 #define NORFLM_BASE 0x61000000 3014 3015 #define SRAMC_BASE 0x68000000 3016 #define SRAMM_BASE 0x69000000 3017 3018 #define SDRAMC_BASE 0x78000000 3019 #define SDRAMM_BASE 0x70000000 3020 3021 /* AHB Peripheral memory map */ 3022 #define SYS_BASE (AHB_BASE + 0x00000) 3023 3024 #define DMA_BASE (AHB_BASE + 0x01000) 3025 3026 #define LCD_BASE (AHB_BASE + 0x02000) 3027 3028 #define CRC_BASE (AHB_BASE + 0x03000) 3029 3030 #define SDIO_BASE (AHB_BASE + 0x04000) 3031 3032 /* APB Peripheral memory map */ 3033 #define PORT_BASE (APB_BASE + 0x00000) 3034 3035 #define GPIOA_BASE (APB_BASE + 0x01000) 3036 #define GPIOB_BASE (APB_BASE + 0x02000) 3037 #define GPIOC_BASE (APB_BASE + 0x03000) 3038 #define GPIOD_BASE (APB_BASE + 0x04000) 3039 #define GPIOM_BASE (APB_BASE + 0x05000) 3040 #define GPION_BASE (APB_BASE + 0x06000) 3041 #define GPIOP_BASE (APB_BASE + 0x08000) 3042 3043 #define TIMR0_BASE (APB_BASE + 0x07000) 3044 #define TIMR1_BASE (APB_BASE + 0x0700C) 3045 #define TIMR2_BASE (APB_BASE + 0x07018) 3046 #define TIMR3_BASE (APB_BASE + 0x07024) 3047 #define TIMR4_BASE (APB_BASE + 0x07030) 3048 #define TIMR5_BASE (APB_BASE + 0x0703C) 3049 #define TIMRG_BASE (APB_BASE + 0x07060) 3050 3051 #define WDT_BASE (APB_BASE + 0x09000) 3052 3053 #define PWM0_BASE (APB_BASE + 0x0A000) 3054 #define PWM1_BASE (APB_BASE + 0x0A020) 3055 #define PWM2_BASE (APB_BASE + 0x0A040) 3056 #define PWM3_BASE (APB_BASE + 0x0A060) 3057 #define PWM4_BASE (APB_BASE + 0x0A080) 3058 #define PWM5_BASE (APB_BASE + 0x0A0A0) 3059 #define PWMG_BASE (APB_BASE + 0x0A180) 3060 3061 #define RTC_BASE (APB_BASE + 0x0B000) 3062 3063 #define ADC0_BASE (APB_BASE + 0x0C000) 3064 #define ADC1_BASE (APB_BASE + 0x0D000) 3065 3066 #define FLASH_BASE (APB_BASE + 0x0F000) 3067 3068 #define UART0_BASE (APB_BASE + 0x10000) 3069 #define UART1_BASE (APB_BASE + 0x11000) 3070 #define UART2_BASE (APB_BASE + 0x12000) 3071 #define UART3_BASE (APB_BASE + 0x13000) 3072 3073 #define I2C0_BASE (APB_BASE + 0x18000) 3074 #define I2C1_BASE (APB_BASE + 0x19000) 3075 3076 #define SPI0_BASE (APB_BASE + 0x1C000) 3077 #define SPI1_BASE (APB_BASE + 0x1D000) 3078 3079 #define CAN_BASE (APB_BASE + 0x20000) 3080 3081 3082 /******************************************************************************/ 3083 /* Peripheral declaration */ 3084 /******************************************************************************/ 3085 #define SYS ((SYS_TypeDef *) SYS_BASE) 3086 3087 #define PORT ((PORT_TypeDef *) PORT_BASE) 3088 3089 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 3090 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 3091 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 3092 #define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) 3093 #define GPION ((GPIO_TypeDef *) GPION_BASE) 3094 #define GPIOP ((GPIO_TypeDef *) GPIOP_BASE) 3095 3096 #define TIMR0 ((TIMR_TypeDef *) TIMR0_BASE) 3097 #define TIMR1 ((TIMR_TypeDef *) TIMR1_BASE) 3098 #define TIMR2 ((TIMR_TypeDef *) TIMR2_BASE) 3099 #define TIMR3 ((TIMR_TypeDef *) TIMR3_BASE) 3100 #define TIMR4 ((TIMR_TypeDef *) TIMR4_BASE) 3101 #define TIMR5 ((TIMR_TypeDef *) TIMR5_BASE) 3102 #define TIMRG ((TIMRG_TypeDef*) TIMRG_BASE) 3103 3104 #define UART0 ((UART_TypeDef *) UART0_BASE) 3105 #define UART1 ((UART_TypeDef *) UART1_BASE) 3106 #define UART2 ((UART_TypeDef *) UART2_BASE) 3107 #define UART3 ((UART_TypeDef *) UART3_BASE) 3108 3109 #define SPI0 ((SPI_TypeDef *) SPI0_BASE) 3110 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 3111 3112 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) 3113 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 3114 3115 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) 3116 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 3117 3118 #define PWM0 ((PWM_TypeDef *) PWM0_BASE) 3119 #define PWM1 ((PWM_TypeDef *) PWM1_BASE) 3120 #define PWM2 ((PWM_TypeDef *) PWM2_BASE) 3121 #define PWM3 ((PWM_TypeDef *) PWM3_BASE) 3122 #define PWM4 ((PWM_TypeDef *) PWM4_BASE) 3123 #define PWM5 ((PWM_TypeDef *) PWM5_BASE) 3124 #define PWMG ((PWMG_TypeDef *) PWMG_BASE) 3125 3126 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 3127 3128 #define DMA ((DMA_TypeDef *) DMA_BASE) 3129 3130 #define CAN ((CAN_TypeDef *) CAN_BASE) 3131 3132 #define LCD ((LCD_TypeDef *) LCD_BASE) 3133 3134 #define CRC ((CRC_TypeDef *) CRC_BASE) 3135 3136 #define RTC ((RTC_TypeDef *) RTC_BASE) 3137 3138 #define WDT ((WDT_TypeDef *) WDT_BASE) 3139 3140 #define FLASH ((FLASH_Typedef*) FLASH_BASE) 3141 3142 #define SRAMC ((SRAMC_TypeDef*) SRAMC_BASE) 3143 3144 #define NORFLC ((NORFLC_TypeDef*) NORFLC_BASE) 3145 3146 #define SDRAMC ((SDRAMC_TypeDef*) SDRAMC_BASE) 3147 3148 3149 3150 typedef void (* Func_void_void) (void); 3151 3152 3153 #include "SWM320_port.h" 3154 #include "SWM320_gpio.h" 3155 #include "SWM320_exti.h" 3156 #include "SWM320_timr.h" 3157 #include "SWM320_uart.h" 3158 #include "SWM320_spi.h" 3159 #include "SWM320_i2c.h" 3160 #include "SWM320_pwm.h" 3161 #include "SWM320_adc.h" 3162 #include "SWM320_dma.h" 3163 #include "SWM320_lcd.h" 3164 #include "SWM320_can.h" 3165 #include "SWM320_sdio.h" 3166 #include "SWM320_flash.h" 3167 #include "SWM320_norflash.h" 3168 #include "SWM320_sdram.h" 3169 #include "SWM320_sram.h" 3170 #include "SWM320_crc.h" 3171 #include "SWM320_rtc.h" 3172 #include "SWM320_wdt.h" 3173 3174 3175 3176 #ifdef SW_LOG_RTT 3177 #define log_printf(...) SEGGER_RTT_printf(0, __VA_ARGS__) 3178 #else 3179 #define log_printf(...) printf(__VA_ARGS__) 3180 #endif 3181 3182 3183 #ifndef SW_LOG_LEVEL 3184 #define SW_LOG_LEVEL 0 3185 #endif 3186 3187 #if (SW_LOG_LEVEL > 0) 3188 #define SW_LOG_ERR(...) { \ 3189 log_printf("ERROR: "); \ 3190 log_printf(__VA_ARGS__); \ 3191 log_printf("\n"); \ 3192 } 3193 3194 #if (SW_LOG_LEVEL > 1) 3195 #define SW_LOG_WARN(...) { \ 3196 log_printf("WARN : "); \ 3197 log_printf(__VA_ARGS__); \ 3198 log_printf("\n"); \ 3199 } 3200 3201 #if (SW_LOG_LEVEL > 2) 3202 #define SW_LOG_INFO(...) { \ 3203 log_printf("INFO : "); \ 3204 log_printf(__VA_ARGS__); \ 3205 log_printf("\n"); \ 3206 } 3207 #else 3208 #define SW_LOG_INFO(...) 3209 #endif 3210 3211 #else 3212 #define SW_LOG_WARN(...) 3213 #define SW_LOG_INFO(...) 3214 #endif 3215 3216 #else 3217 #define SW_LOG_ERR(...) 3218 #define SW_LOG_WARN(...) 3219 #define SW_LOG_INFO(...) 3220 #endif 3221 3222 3223 #endif //__SWM320_H__ 3224