1 /** 2 * @file i2c_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 4 */ 5 6 /* **************************************************************************** 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included 17 * in all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Except as contained in this notice, the name of Maxim Integrated 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated 29 * Products, Inc. Branding Policy. 30 * 31 * The mere transfer of this software does not imply any licenses 32 * of trade secrets, proprietary technology, copyrights, patents, 33 * trademarks, maskwork rights, or any other form of intellectual 34 * property whatsoever. Maxim Integrated Products, Inc. retains all 35 * ownership rights. 36 * 37 * 38 *************************************************************************** */ 39 40 #ifndef _I2C_REGS_H_ 41 #define _I2C_REGS_H_ 42 43 /* **** Includes **** */ 44 #include <stdint.h> 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #if defined (__ICCARM__) 51 #pragma system_include 52 #endif 53 54 #if defined (__CC_ARM) 55 #pragma anon_unions 56 #endif 57 /// @cond 58 /* 59 If types are not defined elsewhere (CMSIS) define them here 60 */ 61 #ifndef __IO 62 #define __IO volatile 63 #endif 64 #ifndef __I 65 #define __I volatile const 66 #endif 67 #ifndef __O 68 #define __O volatile 69 #endif 70 #ifndef __R 71 #define __R volatile const 72 #endif 73 /// @endcond 74 75 /* **** Definitions **** */ 76 77 /** 78 * @ingroup i2c 79 * @defgroup i2c_registers I2C_Registers 80 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 81 * @details Inter-Integrated Circuit. 82 */ 83 84 /** 85 * @ingroup i2c_registers 86 * Structure type to access the I2C Registers. 87 */ 88 typedef struct { 89 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */ 90 __IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */ 91 __IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */ 92 __IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */ 93 __IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */ 94 __IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */ 95 __IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */ 96 __IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */ 97 __IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */ 98 __IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */ 99 __IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */ 100 __IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */ 101 __IO uint32_t master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */ 102 __IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */ 103 __IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */ 104 __IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */ 105 __IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */ 106 __IO uint32_t slave_addr; /**< <tt>\b 0x44:</tt> I2C SLAVE_ADDR Register */ 107 __IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */ 108 } mxc_i2c_regs_t; 109 110 /* Register offsets for module I2C */ 111 /** 112 * @ingroup i2c_registers 113 * @defgroup I2C_Register_Offsets Register Offsets 114 * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 115 * @{ 116 */ 117 #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 118 #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 119 #define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 120 #define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 121 #define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 122 #define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 123 #define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 124 #define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 125 #define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 126 #define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 127 #define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 128 #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 129 #define MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 130 #define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 131 #define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 132 #define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */ 133 #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 134 #define MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */ 135 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 136 /**@} end of group i2c_registers */ 137 138 /** 139 * @ingroup i2c_registers 140 * @defgroup I2C_CTRL I2C_CTRL 141 * @brief Control Register0. 142 * @{ 143 */ 144 #define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */ 145 #define MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */ 146 #define MXC_V_I2C_CTRL_I2C_EN_DIS ((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */ 147 #define MXC_S_I2C_CTRL_I2C_EN_DIS (MXC_V_I2C_CTRL_I2C_EN_DIS << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */ 148 #define MXC_V_I2C_CTRL_I2C_EN_EN ((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value */ 149 #define MXC_S_I2C_CTRL_I2C_EN_EN (MXC_V_I2C_CTRL_I2C_EN_EN << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */ 150 151 #define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */ 152 #define MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */ 153 #define MXC_V_I2C_CTRL_MST_SLAVE_MODE ((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */ 154 #define MXC_S_I2C_CTRL_MST_SLAVE_MODE (MXC_V_I2C_CTRL_MST_SLAVE_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */ 155 #define MXC_V_I2C_CTRL_MST_MASTER_MODE ((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */ 156 #define MXC_S_I2C_CTRL_MST_MASTER_MODE (MXC_V_I2C_CTRL_MST_MASTER_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */ 157 158 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */ 159 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR Mask */ 160 #define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS ((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */ 161 #define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS (MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS Setting */ 162 #define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN ((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */ 163 #define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN (MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN Setting */ 164 165 #define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */ 166 #define MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */ 167 #define MXC_V_I2C_CTRL_RX_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */ 168 #define MXC_S_I2C_CTRL_RX_MODE_DIS (MXC_V_I2C_CTRL_RX_MODE_DIS << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */ 169 #define MXC_V_I2C_CTRL_RX_MODE_EN ((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */ 170 #define MXC_S_I2C_CTRL_RX_MODE_EN (MXC_V_I2C_CTRL_RX_MODE_EN << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */ 171 172 #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */ 173 #define MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK Mask */ 174 #define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK ((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */ 175 #define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK (MXC_V_I2C_CTRL_RX_MODE_ACK_ACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting */ 176 #define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK ((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */ 177 #define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK (MXC_V_I2C_CTRL_RX_MODE_ACK_NACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting */ 178 179 #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ 180 #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ 181 #define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW ((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */ 182 #define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW (MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Setting */ 183 #define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL ((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */ 184 #define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL (MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting */ 185 186 #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ 187 #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ 188 #define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW ((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */ 189 #define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW (MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Setting */ 190 #define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA ((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */ 191 #define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA (MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting */ 192 193 #define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ 194 #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ 195 196 #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ 197 #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ 198 199 #define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */ 200 #define MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */ 201 #define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE ((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */ 202 #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Setting */ 203 #define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE ((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */ 204 #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Setting */ 205 206 #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ 207 #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ 208 #define MXC_V_I2C_CTRL_READ_WRITE ((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */ 209 #define MXC_S_I2C_CTRL_READ_WRITE (MXC_V_I2C_CTRL_READ_WRITE << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */ 210 #define MXC_V_I2C_CTRL_READ_READ ((uint32_t)0x1UL) /**< CTRL_READ_READ Value */ 211 #define MXC_S_I2C_CTRL_READ_READ (MXC_V_I2C_CTRL_READ_READ << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */ 212 213 #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS 12 /**< CTRL_SCL_CLK_STRECH_DIS Position */ 214 #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**< CTRL_SCL_CLK_STRECH_DIS Mask */ 215 #define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN ((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */ 216 #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_EN Setting */ 217 #define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS ((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */ 218 #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Setting */ 219 220 #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */ 221 #define MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE Mask */ 222 #define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */ 223 #define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS (MXC_V_I2C_CTRL_SCL_PP_MODE_DIS << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting */ 224 #define MXC_V_I2C_CTRL_SCL_PP_MODE_EN ((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */ 225 #define MXC_S_I2C_CTRL_SCL_PP_MODE_EN (MXC_V_I2C_CTRL_SCL_PP_MODE_EN << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting */ 226 227 #define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */ 228 #define MXC_F_I2C_CTRL_HS_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */ 229 #define MXC_V_I2C_CTRL_HS_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */ 230 #define MXC_S_I2C_CTRL_HS_MODE_DIS (MXC_V_I2C_CTRL_HS_MODE_DIS << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */ 231 #define MXC_V_I2C_CTRL_HS_MODE_EN ((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */ 232 #define MXC_S_I2C_CTRL_HS_MODE_EN (MXC_V_I2C_CTRL_HS_MODE_EN << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */ 233 234 /**@} end of group I2C_CTRL_Register */ 235 236 /** 237 * @ingroup i2c_registers 238 * @defgroup I2C_STATUS I2C_STATUS 239 * @brief Status Register. 240 * @{ 241 */ 242 #define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */ 243 #define MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask */ 244 #define MXC_V_I2C_STATUS_BUS_IDLE ((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */ 245 #define MXC_S_I2C_STATUS_BUS_IDLE (MXC_V_I2C_STATUS_BUS_IDLE << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */ 246 #define MXC_V_I2C_STATUS_BUS_BUSY ((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */ 247 #define MXC_S_I2C_STATUS_BUS_BUSY (MXC_V_I2C_STATUS_BUS_BUSY << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */ 248 249 #define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */ 250 #define MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ 251 #define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */ 252 #define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY Setting */ 253 #define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */ 254 #define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting */ 255 256 #define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ 257 #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 258 #define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL ((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */ 259 #define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL (MXC_V_I2C_STATUS_RX_FULL_NOT_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting */ 260 #define MXC_V_I2C_STATUS_RX_FULL_FULL ((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */ 261 #define MXC_S_I2C_STATUS_RX_FULL_FULL (MXC_V_I2C_STATUS_RX_FULL_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */ 262 263 #define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */ 264 #define MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ 265 #define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */ 266 #define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY Setting */ 267 #define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */ 268 #define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting */ 269 270 #define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ 271 #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 272 #define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */ 273 #define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY (MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY Setting */ 274 #define MXC_V_I2C_STATUS_TX_FULL_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */ 275 #define MXC_S_I2C_STATUS_TX_FULL_EMPTY (MXC_V_I2C_STATUS_TX_FULL_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */ 276 277 #define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */ 278 #define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE Mask */ 279 #define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Value */ 280 #define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Setting */ 281 #define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Value */ 282 #define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Setting */ 283 284 #define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */ 285 #define MXC_F_I2C_STATUS_STATUS ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ 286 #define MXC_V_I2C_STATUS_STATUS_IDLE ((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */ 287 #define MXC_S_I2C_STATUS_STATUS_IDLE (MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */ 288 #define MXC_V_I2C_STATUS_STATUS_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */ 289 #define MXC_S_I2C_STATUS_STATUS_MTX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting */ 290 #define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */ 291 #define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK Setting */ 292 #define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */ 293 #define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR Setting */ 294 #define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */ 295 #define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR Setting */ 296 #define MXC_V_I2C_STATUS_STATUS_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */ 297 #define MXC_S_I2C_STATUS_STATUS_SRX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting */ 298 #define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */ 299 #define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK Setting */ 300 #define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */ 301 #define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR Setting */ 302 #define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */ 303 #define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK Setting */ 304 #define MXC_V_I2C_STATUS_STATUS_TX ((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */ 305 #define MXC_S_I2C_STATUS_STATUS_TX (MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */ 306 #define MXC_V_I2C_STATUS_STATUS_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */ 307 #define MXC_S_I2C_STATUS_STATUS_RX_ACK (MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */ 308 #define MXC_V_I2C_STATUS_STATUS_RX ((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */ 309 #define MXC_S_I2C_STATUS_STATUS_RX (MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */ 310 #define MXC_V_I2C_STATUS_STATUS_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */ 311 #define MXC_S_I2C_STATUS_STATUS_TX_ACK (MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */ 312 #define MXC_V_I2C_STATUS_STATUS_NACK ((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */ 313 #define MXC_S_I2C_STATUS_STATUS_NACK (MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */ 314 #define MXC_V_I2C_STATUS_STATUS_BY_ST ((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */ 315 #define MXC_S_I2C_STATUS_STATUS_BY_ST (MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */ 316 317 /**@} end of group I2C_STATUS_Register */ 318 319 /** 320 * @ingroup i2c_registers 321 * @defgroup I2C_INT_FL0 I2C_INT_FL0 322 * @brief Interrupt Status Register. 323 * @{ 324 */ 325 #define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */ 326 #define MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */ 327 #define MXC_V_I2C_INT_FL0_DONE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */ 328 #define MXC_S_I2C_INT_FL0_DONE_INACTIVE (MXC_V_I2C_INT_FL0_DONE_INACTIVE << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */ 329 #define MXC_V_I2C_INT_FL0_DONE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */ 330 #define MXC_S_I2C_INT_FL0_DONE_PENDING (MXC_V_I2C_INT_FL0_DONE_PENDING << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */ 331 332 #define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */ 333 #define MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE Mask */ 334 #define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */ 335 #define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE (MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE Setting */ 336 #define MXC_V_I2C_INT_FL0_RX_MODE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */ 337 #define MXC_S_I2C_INT_FL0_RX_MODE_PENDING (MXC_V_I2C_INT_FL0_RX_MODE_PENDING << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING Setting */ 338 339 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 /**< INT_FL0_GEN_CALL_ADDR Position */ 340 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**< INT_FL0_GEN_CALL_ADDR Mask */ 341 #define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */ 342 #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Setting */ 343 #define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING ((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */ 344 #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_PENDING Setting */ 345 346 #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */ 347 #define MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH Mask */ 348 #define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */ 349 #define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE Setting */ 350 #define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */ 351 #define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING (MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING Setting */ 352 353 #define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */ 354 #define MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH Mask */ 355 #define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */ 356 #define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE Setting */ 357 #define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */ 358 #define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING (MXC_V_I2C_INT_FL0_RX_THRESH_PENDING << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING Setting */ 359 360 #define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */ 361 #define MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH Mask */ 362 #define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */ 363 #define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE Setting */ 364 #define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */ 365 #define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING (MXC_V_I2C_INT_FL0_TX_THRESH_PENDING << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING Setting */ 366 367 #define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */ 368 #define MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */ 369 #define MXC_V_I2C_INT_FL0_STOP_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */ 370 #define MXC_S_I2C_INT_FL0_STOP_INACTIVE (MXC_V_I2C_INT_FL0_STOP_INACTIVE << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */ 371 #define MXC_V_I2C_INT_FL0_STOP_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */ 372 #define MXC_S_I2C_INT_FL0_STOP_PENDING (MXC_V_I2C_INT_FL0_STOP_PENDING << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */ 373 374 #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */ 375 #define MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK Mask */ 376 #define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */ 377 #define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE Setting */ 378 #define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */ 379 #define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING (MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING Setting */ 380 381 #define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */ 382 #define MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */ 383 #define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */ 384 #define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE (MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting */ 385 #define MXC_V_I2C_INT_FL0_ARB_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */ 386 #define MXC_S_I2C_INT_FL0_ARB_ER_PENDING (MXC_V_I2C_INT_FL0_ARB_ER_PENDING << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting */ 387 388 #define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */ 389 #define MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */ 390 #define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */ 391 #define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE (MXC_V_I2C_INT_FL0_TO_ER_INACTIVE << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting */ 392 #define MXC_V_I2C_INT_FL0_TO_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */ 393 #define MXC_S_I2C_INT_FL0_TO_ER_PENDING (MXC_V_I2C_INT_FL0_TO_ER_PENDING << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */ 394 395 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 /**< INT_FL0_ADDR_NACK_ER Position */ 396 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**< INT_FL0_ADDR_NACK_ER Mask */ 397 #define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */ 398 #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Setting */ 399 #define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */ 400 #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_PENDING Setting */ 401 402 #define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */ 403 #define MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER Mask */ 404 #define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */ 405 #define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE (MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE Setting */ 406 #define MXC_V_I2C_INT_FL0_DATA_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */ 407 #define MXC_S_I2C_INT_FL0_DATA_ER_PENDING (MXC_V_I2C_INT_FL0_DATA_ER_PENDING << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING Setting */ 408 409 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 /**< INT_FL0_DO_NOT_RESP_ER Position */ 410 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**< INT_FL0_DO_NOT_RESP_ER Mask */ 411 #define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */ 412 #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Setting */ 413 #define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */ 414 #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Setting */ 415 416 #define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */ 417 #define MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER Mask */ 418 #define MXC_V_I2C_INT_FL0_START_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */ 419 #define MXC_S_I2C_INT_FL0_START_ER_INACTIVE (MXC_V_I2C_INT_FL0_START_ER_INACTIVE << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE Setting */ 420 #define MXC_V_I2C_INT_FL0_START_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */ 421 #define MXC_S_I2C_INT_FL0_START_ER_PENDING (MXC_V_I2C_INT_FL0_START_ER_PENDING << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING Setting */ 422 423 #define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */ 424 #define MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER Mask */ 425 #define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */ 426 #define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE (MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE Setting */ 427 #define MXC_V_I2C_INT_FL0_STOP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */ 428 #define MXC_S_I2C_INT_FL0_STOP_ER_PENDING (MXC_V_I2C_INT_FL0_STOP_ER_PENDING << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING Setting */ 429 430 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 /**< INT_FL0_TX_LOCK_OUT Position */ 431 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< INT_FL0_TX_LOCK_OUT Mask */ 432 433 /**@} end of group I2C_INT_FL0_Register */ 434 435 /** 436 * @ingroup i2c_registers 437 * @defgroup I2C_INT_EN0 I2C_INT_EN0 438 * @brief Interrupt Enable Register. 439 * @{ 440 */ 441 #define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */ 442 #define MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */ 443 #define MXC_V_I2C_INT_EN0_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */ 444 #define MXC_S_I2C_INT_EN0_DONE_DIS (MXC_V_I2C_INT_EN0_DONE_DIS << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */ 445 #define MXC_V_I2C_INT_EN0_DONE_EN ((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */ 446 #define MXC_S_I2C_INT_EN0_DONE_EN (MXC_V_I2C_INT_EN0_DONE_EN << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */ 447 448 #define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */ 449 #define MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE Mask */ 450 #define MXC_V_I2C_INT_EN0_RX_MODE_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */ 451 #define MXC_S_I2C_INT_EN0_RX_MODE_DIS (MXC_V_I2C_INT_EN0_RX_MODE_DIS << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */ 452 #define MXC_V_I2C_INT_EN0_RX_MODE_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */ 453 #define MXC_S_I2C_INT_EN0_RX_MODE_EN (MXC_V_I2C_INT_EN0_RX_MODE_EN << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */ 454 455 #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS 2 /**< INT_EN0_GEN_CTRL_ADDR Position */ 456 #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**< INT_EN0_GEN_CTRL_ADDR Mask */ 457 #define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS ((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */ 458 #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_DIS Setting */ 459 #define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN ((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */ 460 #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN Setting */ 461 462 #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */ 463 #define MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH Mask */ 464 #define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */ 465 #define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS (MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS Setting */ 466 #define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */ 467 #define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN (MXC_V_I2C_INT_EN0_ADDR_MATCH_EN << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN Setting */ 468 469 #define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */ 470 #define MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH Mask */ 471 #define MXC_V_I2C_INT_EN0_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */ 472 #define MXC_S_I2C_INT_EN0_RX_THRESH_DIS (MXC_V_I2C_INT_EN0_RX_THRESH_DIS << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS Setting */ 473 #define MXC_V_I2C_INT_EN0_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */ 474 #define MXC_S_I2C_INT_EN0_RX_THRESH_EN (MXC_V_I2C_INT_EN0_RX_THRESH_EN << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting */ 475 476 #define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */ 477 #define MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH Mask */ 478 #define MXC_V_I2C_INT_EN0_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */ 479 #define MXC_S_I2C_INT_EN0_TX_THRESH_DIS (MXC_V_I2C_INT_EN0_TX_THRESH_DIS << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS Setting */ 480 #define MXC_V_I2C_INT_EN0_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */ 481 #define MXC_S_I2C_INT_EN0_TX_THRESH_EN (MXC_V_I2C_INT_EN0_TX_THRESH_EN << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting */ 482 483 #define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */ 484 #define MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */ 485 #define MXC_V_I2C_INT_EN0_STOP_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */ 486 #define MXC_S_I2C_INT_EN0_STOP_DIS (MXC_V_I2C_INT_EN0_STOP_DIS << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */ 487 #define MXC_V_I2C_INT_EN0_STOP_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */ 488 #define MXC_S_I2C_INT_EN0_STOP_EN (MXC_V_I2C_INT_EN0_STOP_EN << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */ 489 490 #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */ 491 #define MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK Mask */ 492 #define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */ 493 #define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS (MXC_V_I2C_INT_EN0_ADDR_ACK_DIS << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting */ 494 #define MXC_V_I2C_INT_EN0_ADDR_ACK_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */ 495 #define MXC_S_I2C_INT_EN0_ADDR_ACK_EN (MXC_V_I2C_INT_EN0_ADDR_ACK_EN << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting */ 496 497 #define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */ 498 #define MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */ 499 #define MXC_V_I2C_INT_EN0_ARB_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */ 500 #define MXC_S_I2C_INT_EN0_ARB_ER_DIS (MXC_V_I2C_INT_EN0_ARB_ER_DIS << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */ 501 #define MXC_V_I2C_INT_EN0_ARB_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */ 502 #define MXC_S_I2C_INT_EN0_ARB_ER_EN (MXC_V_I2C_INT_EN0_ARB_ER_EN << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */ 503 504 #define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */ 505 #define MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */ 506 #define MXC_V_I2C_INT_EN0_TO_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */ 507 #define MXC_S_I2C_INT_EN0_TO_ER_DIS (MXC_V_I2C_INT_EN0_TO_ER_DIS << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */ 508 #define MXC_V_I2C_INT_EN0_TO_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */ 509 #define MXC_S_I2C_INT_EN0_TO_ER_EN (MXC_V_I2C_INT_EN0_TO_ER_EN << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */ 510 511 #define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */ 512 #define MXC_F_I2C_INT_EN0_ADDR_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER Mask */ 513 #define MXC_V_I2C_INT_EN0_ADDR_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */ 514 #define MXC_S_I2C_INT_EN0_ADDR_ER_DIS (MXC_V_I2C_INT_EN0_ADDR_ER_DIS << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */ 515 #define MXC_V_I2C_INT_EN0_ADDR_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */ 516 #define MXC_S_I2C_INT_EN0_ADDR_ER_EN (MXC_V_I2C_INT_EN0_ADDR_ER_EN << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */ 517 518 #define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */ 519 #define MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER Mask */ 520 #define MXC_V_I2C_INT_EN0_DATA_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */ 521 #define MXC_S_I2C_INT_EN0_DATA_ER_DIS (MXC_V_I2C_INT_EN0_DATA_ER_DIS << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */ 522 #define MXC_V_I2C_INT_EN0_DATA_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */ 523 #define MXC_S_I2C_INT_EN0_DATA_ER_EN (MXC_V_I2C_INT_EN0_DATA_ER_EN << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */ 524 525 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 /**< INT_EN0_DO_NOT_RESP_ER Position */ 526 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**< INT_EN0_DO_NOT_RESP_ER Mask */ 527 #define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */ 528 #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_DIS Setting */ 529 #define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */ 530 #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_EN Setting */ 531 532 #define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */ 533 #define MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER Mask */ 534 #define MXC_V_I2C_INT_EN0_START_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */ 535 #define MXC_S_I2C_INT_EN0_START_ER_DIS (MXC_V_I2C_INT_EN0_START_ER_DIS << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting */ 536 #define MXC_V_I2C_INT_EN0_START_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */ 537 #define MXC_S_I2C_INT_EN0_START_ER_EN (MXC_V_I2C_INT_EN0_START_ER_EN << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting */ 538 539 #define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */ 540 #define MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER Mask */ 541 #define MXC_V_I2C_INT_EN0_STOP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */ 542 #define MXC_S_I2C_INT_EN0_STOP_ER_DIS (MXC_V_I2C_INT_EN0_STOP_ER_DIS << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */ 543 #define MXC_V_I2C_INT_EN0_STOP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */ 544 #define MXC_S_I2C_INT_EN0_STOP_ER_EN (MXC_V_I2C_INT_EN0_STOP_ER_EN << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */ 545 546 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 /**< INT_EN0_TX_LOCK_OUT Position */ 547 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< INT_EN0_TX_LOCK_OUT Mask */ 548 #define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */ 549 #define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS Setting */ 550 #define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */ 551 #define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN Setting */ 552 553 /**@} end of group I2C_INT_EN0_Register */ 554 555 /** 556 * @ingroup i2c_registers 557 * @defgroup I2C_INT_FL1 I2C_INT_FL1 558 * @brief Interrupt Status Register 1. 559 * @{ 560 */ 561 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 /**< INT_FL1_RX_OVERFLOW Position */ 562 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**< INT_FL1_RX_OVERFLOW Mask */ 563 #define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */ 564 #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_INACTIVE Setting */ 565 #define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */ 566 #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING (MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_PENDING Setting */ 567 568 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 /**< INT_FL1_TX_UNDERFLOW Position */ 569 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< INT_FL1_TX_UNDERFLOW Mask */ 570 #define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */ 571 #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Setting */ 572 #define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */ 573 #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_PENDING Setting */ 574 575 /**@} end of group I2C_INT_FL1_Register */ 576 577 /** 578 * @ingroup i2c_registers 579 * @defgroup I2C_INT_EN1 I2C_INT_EN1 580 * @brief Interrupt Staus Register 1. 581 * @{ 582 */ 583 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 /**< INT_EN1_RX_OVERFLOW Position */ 584 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**< INT_EN1_RX_OVERFLOW Mask */ 585 #define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */ 586 #define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS (MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS Setting */ 587 #define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */ 588 #define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN (MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN Setting */ 589 590 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 /**< INT_EN1_TX_UNDERFLOW Position */ 591 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< INT_EN1_TX_UNDERFLOW Mask */ 592 #define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */ 593 #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS Setting */ 594 #define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */ 595 #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN Setting */ 596 597 /**@} end of group I2C_INT_EN1_Register */ 598 599 /** 600 * @ingroup i2c_registers 601 * @defgroup I2C_FIFO_LEN I2C_FIFO_LEN 602 * @brief FIFO Configuration Register. 603 * @{ 604 */ 605 #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */ 606 #define MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN Mask */ 607 608 #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */ 609 #define MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN Mask */ 610 611 /**@} end of group I2C_FIFO_LEN_Register */ 612 613 /** 614 * @ingroup i2c_registers 615 * @defgroup I2C_RX_CTRL0 I2C_RX_CTRL0 616 * @brief Receive Control Register 0. 617 * @{ 618 */ 619 #define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */ 620 #define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */ 621 #define MXC_V_I2C_RX_CTRL0_DNR_RESPOND ((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */ 622 #define MXC_S_I2C_RX_CTRL0_DNR_RESPOND (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */ 623 #define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY ((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */ 624 #define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY (MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Setting */ 625 626 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */ 627 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH Mask */ 628 #define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */ 629 #define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED (MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Setting */ 630 #define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */ 631 #define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH (MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH Setting */ 632 633 #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */ 634 #define MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH Mask */ 635 636 /**@} end of group I2C_RX_CTRL0_Register */ 637 638 /** 639 * @ingroup i2c_registers 640 * @defgroup I2C_RX_CTRL1 I2C_RX_CTRL1 641 * @brief Receive Control Register 1. 642 * @{ 643 */ 644 #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */ 645 #define MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT Mask */ 646 647 #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */ 648 #define MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO Mask */ 649 650 /**@} end of group I2C_RX_CTRL1_Register */ 651 652 /** 653 * @ingroup i2c_registers 654 * @defgroup I2C_TX_CTRL0 I2C_TX_CTRL0 655 * @brief Transmit Control Register 0. 656 * @{ 657 */ 658 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 /**< TX_CTRL0_TX_PRELOAD Position */ 659 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**< TX_CTRL0_TX_PRELOAD Mask */ 660 661 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 /**< TX_CTRL0_TX_READY_MODE Position */ 662 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< TX_CTRL0_TX_READY_MODE Mask */ 663 #define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN ((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */ 664 #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_EN Setting */ 665 #define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS ((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */ 666 #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_DIS Setting */ 667 668 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */ 669 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH Mask */ 670 #define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */ 671 #define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED (MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Setting */ 672 #define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */ 673 #define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH (MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH Setting */ 674 675 #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */ 676 #define MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH Mask */ 677 678 /**@} end of group I2C_TX_CTRL0_Register */ 679 680 /** 681 * @ingroup i2c_registers 682 * @defgroup I2C_TX_CTRL1 I2C_TX_CTRL1 683 * @brief Transmit Control Register 1. 684 * @{ 685 */ 686 #define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */ 687 #define MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY Mask */ 688 689 #define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */ 690 #define MXC_F_I2C_TX_CTRL1_TX_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST Mask */ 691 #define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW ((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */ 692 #define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW (MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Setting */ 693 #define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION ((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */ 694 #define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION (MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Setting */ 695 696 #define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */ 697 #define MXC_F_I2C_TX_CTRL1_TX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO Mask */ 698 699 /**@} end of group I2C_TX_CTRL1_Register */ 700 701 /** 702 * @ingroup i2c_registers 703 * @defgroup I2C_FIFO I2C_FIFO 704 * @brief Data Register. 705 * @{ 706 */ 707 #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 708 #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 709 710 /**@} end of group I2C_FIFO_Register */ 711 712 /** 713 * @ingroup i2c_registers 714 * @defgroup I2C_MASTER_CTRL I2C_MASTER_CTRL 715 * @brief Master Control Register. 716 * @{ 717 */ 718 #define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */ 719 #define MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START Mask */ 720 721 #define MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 /**< MASTER_CTRL_RESTART Position */ 722 #define MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**< MASTER_CTRL_RESTART Mask */ 723 724 #define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */ 725 #define MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP Mask */ 726 727 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 /**< MASTER_CTRL_SL_EX_ADDR Position */ 728 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**< MASTER_CTRL_SL_EX_ADDR Mask */ 729 #define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */ 730 #define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Setting */ 731 #define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */ 732 #define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Setting */ 733 734 #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS 8 /**< MASTER_CTRL_MASTER_CODE Position */ 735 #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**< MASTER_CTRL_MASTER_CODE Mask */ 736 737 #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS 11 /**< MASTER_CTRL_SCL_SPEED_UP Position */ 738 #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**< MASTER_CTRL_SCL_SPEED_UP Mask */ 739 #define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN ((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */ 740 #define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_EN Setting */ 741 #define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS ((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */ 742 #define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Setting */ 743 744 /**@} end of group I2C_MASTER_CTRL_Register */ 745 746 /** 747 * @ingroup i2c_registers 748 * @defgroup I2C_CLK_LO I2C_CLK_LO 749 * @brief Clock Low Register. 750 * @{ 751 */ 752 #define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */ 753 #define MXC_F_I2C_CLK_LO_CLK_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */ 754 755 /**@} end of group I2C_CLK_LO_Register */ 756 757 /** 758 * @ingroup i2c_registers 759 * @defgroup I2C_CLK_HI I2C_CLK_HI 760 * @brief Clock high Register. 761 * @{ 762 */ 763 #define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */ 764 #define MXC_F_I2C_CLK_HI_CKH ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */ 765 766 /**@} end of group I2C_CLK_HI_Register */ 767 768 /** 769 * @ingroup i2c_registers 770 * @defgroup I2C_HS_CLK I2C_HS_CLK 771 * @brief HS-Mode Clock Control Register 772 * @{ 773 */ 774 #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */ 775 #define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */ 776 777 #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */ 778 #define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */ 779 780 /**@} end of group I2C_HS_CLK_Register */ 781 782 /** 783 * @ingroup i2c_registers 784 * @defgroup I2C_TIMEOUT I2C_TIMEOUT 785 * @brief Timeout Register 786 * @{ 787 */ 788 #define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ 789 #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ 790 791 /**@} end of group I2C_TIMEOUT_Register */ 792 793 /** 794 * @ingroup i2c_registers 795 * @defgroup I2C_SLAVE_ADDR I2C_SLAVE_ADDR 796 * @brief Slave Address Register. 797 * @{ 798 */ 799 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR_SLAVE_ADDR Position */ 800 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< SLAVE_ADDR_SLAVE_ADDR Mask */ 801 802 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS 10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */ 803 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_DIS Mask */ 804 805 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS 11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */ 806 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_IDX Mask */ 807 808 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 /**< SLAVE_ADDR_EX_ADDR Position */ 809 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR Mask */ 810 #define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */ 811 #define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Setting */ 812 #define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */ 813 #define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Setting */ 814 815 /**@} end of group I2C_SLAVE_ADDR_Register */ 816 817 /** 818 * @ingroup i2c_registers 819 * @defgroup I2C_DMA I2C_DMA 820 * @brief DMA Register. 821 * @{ 822 */ 823 #define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ 824 #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ 825 #define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */ 826 #define MXC_S_I2C_DMA_TX_EN_DIS (MXC_V_I2C_DMA_TX_EN_DIS << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */ 827 #define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */ 828 #define MXC_S_I2C_DMA_TX_EN_EN (MXC_V_I2C_DMA_TX_EN_EN << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */ 829 830 #define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ 831 #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ 832 #define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */ 833 #define MXC_S_I2C_DMA_RX_EN_DIS (MXC_V_I2C_DMA_RX_EN_DIS << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */ 834 #define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */ 835 #define MXC_S_I2C_DMA_RX_EN_EN (MXC_V_I2C_DMA_RX_EN_EN << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */ 836 837 /**@} end of group I2C_DMA_Register */ 838 839 #ifdef __cplusplus 840 } 841 #endif 842 843 #endif /* _I2C_REGS_H_ */ 844