1 /** 2 * @file uart_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 4 */ 5 6 /* **************************************************************************** 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included 17 * in all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Except as contained in this notice, the name of Maxim Integrated 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated 29 * Products, Inc. Branding Policy. 30 * 31 * The mere transfer of this software does not imply any licenses 32 * of trade secrets, proprietary technology, copyrights, patents, 33 * trademarks, maskwork rights, or any other form of intellectual 34 * property whatsoever. Maxim Integrated Products, Inc. retains all 35 * ownership rights. 36 * 37 * 38 *************************************************************************** */ 39 40 #ifndef _UART_REGS_H_ 41 #define _UART_REGS_H_ 42 43 /* **** Includes **** */ 44 #include <stdint.h> 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #if defined (__ICCARM__) 51 #pragma system_include 52 #endif 53 54 #if defined (__CC_ARM) 55 #pragma anon_unions 56 #endif 57 /// @cond 58 /* 59 If types are not defined elsewhere (CMSIS) define them here 60 */ 61 #ifndef __IO 62 #define __IO volatile 63 #endif 64 #ifndef __I 65 #define __I volatile const 66 #endif 67 #ifndef __O 68 #define __O volatile 69 #endif 70 #ifndef __R 71 #define __R volatile const 72 #endif 73 /// @endcond 74 75 /* **** Definitions **** */ 76 77 /** 78 * @ingroup uart 79 * @defgroup uart_registers UART_Registers 80 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 81 * @details UART 82 */ 83 84 /** 85 * @ingroup uart_registers 86 * Structure type to access the UART Registers. 87 */ 88 typedef struct { 89 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> UART CTRL Register */ 90 __IO uint32_t thresh_ctrl; /**< <tt>\b 0x04:</tt> UART THRESH_CTRL Register */ 91 __I uint32_t status; /**< <tt>\b 0x08:</tt> UART STATUS Register */ 92 __IO uint32_t int_en; /**< <tt>\b 0x0C:</tt> UART INT_EN Register */ 93 __IO uint32_t int_fl; /**< <tt>\b 0x10:</tt> UART INT_FL Register */ 94 __IO uint32_t baud0; /**< <tt>\b 0x14:</tt> UART BAUD0 Register */ 95 __IO uint32_t baud1; /**< <tt>\b 0x18:</tt> UART BAUD1 Register */ 96 __IO uint32_t fifo; /**< <tt>\b 0x1C:</tt> UART FIFO Register */ 97 __IO uint32_t dma; /**< <tt>\b 0x20:</tt> UART DMA Register */ 98 __IO uint32_t tx_fifo; /**< <tt>\b 0x24:</tt> UART TX_FIFO Register */ 99 } mxc_uart_regs_t; 100 101 /* Register offsets for module UART */ 102 /** 103 * @ingroup uart_registers 104 * @defgroup UART_Register_Offsets Register Offsets 105 * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. 106 * @{ 107 */ 108 #define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */ 109 #define MXC_R_UART_THRESH_CTRL ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */ 110 #define MXC_R_UART_STATUS ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */ 111 #define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */ 112 #define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */ 113 #define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */ 114 #define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */ 115 #define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */ 116 #define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */ 117 #define MXC_R_UART_TX_FIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> 0x0024</tt> */ 118 /**@} end of group uart_registers */ 119 120 /** 121 * @ingroup uart_registers 122 * @defgroup UART_CTRL UART_CTRL 123 * @brief Control Register. 124 * @{ 125 */ 126 #define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ 127 #define MXC_F_UART_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ 128 #define MXC_V_UART_CTRL_ENABLE_DIS ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */ 129 #define MXC_S_UART_CTRL_ENABLE_DIS (MXC_V_UART_CTRL_ENABLE_DIS << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */ 130 #define MXC_V_UART_CTRL_ENABLE_EN ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value */ 131 #define MXC_S_UART_CTRL_ENABLE_EN (MXC_V_UART_CTRL_ENABLE_EN << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */ 132 133 #define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */ 134 #define MXC_F_UART_CTRL_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */ 135 #define MXC_V_UART_CTRL_PARITY_EN_DIS ((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */ 136 #define MXC_S_UART_CTRL_PARITY_EN_DIS (MXC_V_UART_CTRL_PARITY_EN_DIS << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */ 137 #define MXC_V_UART_CTRL_PARITY_EN_EN ((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */ 138 #define MXC_S_UART_CTRL_PARITY_EN_EN (MXC_V_UART_CTRL_PARITY_EN_EN << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */ 139 140 #define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */ 141 #define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */ 142 #define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */ 143 #define MXC_S_UART_CTRL_PARITY_EVEN (MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */ 144 #define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */ 145 #define MXC_S_UART_CTRL_PARITY_ODD (MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */ 146 #define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */ 147 #define MXC_S_UART_CTRL_PARITY_MARK (MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */ 148 #define MXC_V_UART_CTRL_PARITY_SPACE ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */ 149 #define MXC_S_UART_CTRL_PARITY_SPACE (MXC_V_UART_CTRL_PARITY_SPACE << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */ 150 151 #define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */ 152 #define MXC_F_UART_CTRL_PARMD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */ 153 #define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */ 154 #define MXC_S_UART_CTRL_PARMD_1 (MXC_V_UART_CTRL_PARMD_1 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_1 Setting */ 155 #define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */ 156 #define MXC_S_UART_CTRL_PARMD_0 (MXC_V_UART_CTRL_PARMD_0 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */ 157 158 #define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */ 159 #define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ 160 161 #define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */ 162 #define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ 163 164 #define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */ 165 #define MXC_F_UART_CTRL_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */ 166 #define MXC_V_UART_CTRL_BITACC_FRAME ((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */ 167 #define MXC_S_UART_CTRL_BITACC_FRAME (MXC_V_UART_CTRL_BITACC_FRAME << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */ 168 #define MXC_V_UART_CTRL_BITACC_BIT ((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */ 169 #define MXC_S_UART_CTRL_BITACC_BIT (MXC_V_UART_CTRL_BITACC_BIT << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */ 170 171 #define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */ 172 #define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ 173 #define MXC_V_UART_CTRL_CHAR_SIZE_5 ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */ 174 #define MXC_S_UART_CTRL_CHAR_SIZE_5 (MXC_V_UART_CTRL_CHAR_SIZE_5 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */ 175 #define MXC_V_UART_CTRL_CHAR_SIZE_6 ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */ 176 #define MXC_S_UART_CTRL_CHAR_SIZE_6 (MXC_V_UART_CTRL_CHAR_SIZE_6 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */ 177 #define MXC_V_UART_CTRL_CHAR_SIZE_7 ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */ 178 #define MXC_S_UART_CTRL_CHAR_SIZE_7 (MXC_V_UART_CTRL_CHAR_SIZE_7 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */ 179 #define MXC_V_UART_CTRL_CHAR_SIZE_8 ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */ 180 #define MXC_S_UART_CTRL_CHAR_SIZE_8 (MXC_V_UART_CTRL_CHAR_SIZE_8 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */ 181 182 #define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */ 183 #define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ 184 #define MXC_V_UART_CTRL_STOPBITS_1 ((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */ 185 #define MXC_S_UART_CTRL_STOPBITS_1 (MXC_V_UART_CTRL_STOPBITS_1 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */ 186 #define MXC_V_UART_CTRL_STOPBITS_1_5 ((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */ 187 #define MXC_S_UART_CTRL_STOPBITS_1_5 (MXC_V_UART_CTRL_STOPBITS_1_5 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */ 188 189 #define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */ 190 #define MXC_F_UART_CTRL_FLOW_CTRL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */ 191 #define MXC_V_UART_CTRL_FLOW_CTRL_EN ((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */ 192 #define MXC_S_UART_CTRL_FLOW_CTRL_EN (MXC_V_UART_CTRL_FLOW_CTRL_EN << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */ 193 #define MXC_V_UART_CTRL_FLOW_CTRL_DIS ((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */ 194 #define MXC_S_UART_CTRL_FLOW_CTRL_DIS (MXC_V_UART_CTRL_FLOW_CTRL_DIS << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */ 195 196 #define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */ 197 #define MXC_F_UART_CTRL_FLOW_POL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */ 198 #define MXC_V_UART_CTRL_FLOW_POL_0 ((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */ 199 #define MXC_S_UART_CTRL_FLOW_POL_0 (MXC_V_UART_CTRL_FLOW_POL_0 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */ 200 #define MXC_V_UART_CTRL_FLOW_POL_1 ((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */ 201 #define MXC_S_UART_CTRL_FLOW_POL_1 (MXC_V_UART_CTRL_FLOW_POL_1 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */ 202 203 #define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */ 204 #define MXC_F_UART_CTRL_NULL_MODEM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM Mask */ 205 #define MXC_V_UART_CTRL_NULL_MODEM_DIS ((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */ 206 #define MXC_S_UART_CTRL_NULL_MODEM_DIS (MXC_V_UART_CTRL_NULL_MODEM_DIS << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting */ 207 #define MXC_V_UART_CTRL_NULL_MODEM_EN ((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */ 208 #define MXC_S_UART_CTRL_NULL_MODEM_EN (MXC_V_UART_CTRL_NULL_MODEM_EN << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */ 209 210 #define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */ 211 #define MXC_F_UART_CTRL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask */ 212 #define MXC_V_UART_CTRL_BREAK_DIS ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value */ 213 #define MXC_S_UART_CTRL_BREAK_DIS (MXC_V_UART_CTRL_BREAK_DIS << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */ 214 #define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */ 215 #define MXC_S_UART_CTRL_BREAK_EN (MXC_V_UART_CTRL_BREAK_EN << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */ 216 217 #define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */ 218 #define MXC_F_UART_CTRL_CLKSEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ 219 #define MXC_V_UART_CTRL_CLKSEL_SYSTEM ((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */ 220 #define MXC_S_UART_CTRL_CLKSEL_SYSTEM (MXC_V_UART_CTRL_CLKSEL_SYSTEM << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */ 221 #define MXC_V_UART_CTRL_CLKSEL_ALTERNATE ((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */ 222 #define MXC_S_UART_CTRL_CLKSEL_ALTERNATE (MXC_V_UART_CTRL_CLKSEL_ALTERNATE << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */ 223 224 #define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */ 225 #define MXC_F_UART_CTRL_RX_TO ((uint32_t)(0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */ 226 227 /**@} end of group UART_CTRL_Register */ 228 229 /** 230 * @ingroup uart_registers 231 * @defgroup UART_THRESH_CTRL UART_THRESH_CTRL 232 * @brief Threshold Control register. 233 * @{ 234 */ 235 #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS 0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */ 236 #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< THRESH_CTRL_RX_FIFO_THRESH Mask */ 237 238 #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS 8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */ 239 #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< THRESH_CTRL_TX_FIFO_THRESH Mask */ 240 241 #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS 16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */ 242 #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< THRESH_CTRL_RTS_FIFO_THRESH Mask */ 243 244 /**@} end of group UART_THRESH_CTRL_Register */ 245 246 /** 247 * @ingroup uart_registers 248 * @defgroup UART_STATUS UART_STATUS 249 * @brief Status Register. 250 * @{ 251 */ 252 #define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ 253 #define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ 254 255 #define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ 256 #define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ 257 258 #define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */ 259 #define MXC_F_UART_STATUS_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */ 260 261 #define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */ 262 #define MXC_F_UART_STATUS_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */ 263 264 #define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */ 265 #define MXC_F_UART_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ 266 267 #define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ 268 #define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 269 270 #define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */ 271 #define MXC_F_UART_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ 272 273 #define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ 274 #define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 275 276 #define MXC_F_UART_STATUS_RX_FIFO_CNT_POS 8 /**< STATUS_RX_FIFO_CNT Position */ 277 #define MXC_F_UART_STATUS_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT Mask */ 278 279 #define MXC_F_UART_STATUS_TX_FIFO_CNT_POS 16 /**< STATUS_TX_FIFO_CNT Position */ 280 #define MXC_F_UART_STATUS_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT Mask */ 281 282 #define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */ 283 #define MXC_F_UART_STATUS_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */ 284 285 /**@} end of group UART_STATUS_Register */ 286 287 /** 288 * @ingroup uart_registers 289 * @defgroup UART_INT_EN UART_INT_EN 290 * @brief Interrupt Enable Register. 291 * @{ 292 */ 293 #define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ 294 #define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ 295 296 #define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ 297 #define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ 298 299 #define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */ 300 #define MXC_F_UART_INT_EN_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE Mask */ 301 302 #define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ 303 #define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ 304 305 #define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS 4 /**< INT_EN_RX_FIFO_THRESH Position */ 306 #define MXC_F_UART_INT_EN_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< INT_EN_RX_FIFO_THRESH Mask */ 307 308 #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */ 309 #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_EN_TX_FIFO_ALMOST_EMPTY Mask */ 310 311 #define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS 6 /**< INT_EN_TX_FIFO_THRESH Position */ 312 #define MXC_F_UART_INT_EN_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< INT_EN_TX_FIFO_THRESH Mask */ 313 314 #define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ 315 #define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ 316 317 #define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */ 318 #define MXC_F_UART_INT_EN_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT Mask */ 319 320 #define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ 321 #define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */ 322 323 /**@} end of group UART_INT_EN_Register */ 324 325 /** 326 * @ingroup uart_registers 327 * @defgroup UART_INT_FL UART_INT_FL 328 * @brief Interrupt Status Flags. 329 * @{ 330 */ 331 #define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS 0 /**< INT_FL_RX_FRAME_ERROR Position */ 332 #define MXC_F_UART_INT_FL_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< INT_FL_RX_FRAME_ERROR Mask */ 333 334 #define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS 1 /**< INT_FL_RX_PARITY_ERROR Position */ 335 #define MXC_F_UART_INT_FL_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< INT_FL_RX_PARITY_ERROR Mask */ 336 337 #define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */ 338 #define MXC_F_UART_INT_FL_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE Mask */ 339 340 #define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */ 341 #define MXC_F_UART_INT_FL_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN Mask */ 342 343 #define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS 4 /**< INT_FL_RX_FIFO_THRESH Position */ 344 #define MXC_F_UART_INT_FL_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< INT_FL_RX_FIFO_THRESH Mask */ 345 346 #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */ 347 #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_FL_TX_FIFO_ALMOST_EMPTY Mask */ 348 349 #define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS 6 /**< INT_FL_TX_FIFO_THRESH Position */ 350 #define MXC_F_UART_INT_FL_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< INT_FL_TX_FIFO_THRESH Mask */ 351 352 #define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ 353 #define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ 354 355 #define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */ 356 #define MXC_F_UART_INT_FL_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT Mask */ 357 358 #define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ 359 #define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */ 360 361 /**@} end of group UART_INT_FL_Register */ 362 363 /** 364 * @ingroup uart_registers 365 * @defgroup UART_BAUD0 UART_BAUD0 366 * @brief Baud rate register. Integer portion. 367 * @{ 368 */ 369 #define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ 370 #define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ 371 372 #define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */ 373 #define MXC_F_UART_BAUD0_FACTOR ((uint32_t)(0x3UL << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */ 374 #define MXC_V_UART_BAUD0_FACTOR_128 ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */ 375 #define MXC_S_UART_BAUD0_FACTOR_128 (MXC_V_UART_BAUD0_FACTOR_128 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */ 376 #define MXC_V_UART_BAUD0_FACTOR_64 ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */ 377 #define MXC_S_UART_BAUD0_FACTOR_64 (MXC_V_UART_BAUD0_FACTOR_64 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */ 378 #define MXC_V_UART_BAUD0_FACTOR_32 ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */ 379 #define MXC_S_UART_BAUD0_FACTOR_32 (MXC_V_UART_BAUD0_FACTOR_32 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */ 380 #define MXC_V_UART_BAUD0_FACTOR_16 ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */ 381 #define MXC_S_UART_BAUD0_FACTOR_16 (MXC_V_UART_BAUD0_FACTOR_16 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */ 382 383 /**@} end of group UART_BAUD0_Register */ 384 385 /** 386 * @ingroup uart_registers 387 * @defgroup UART_BAUD1 UART_BAUD1 388 * @brief Baud rate register. Decimal Setting. 389 * @{ 390 */ 391 #define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ 392 #define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ 393 394 /**@} end of group UART_BAUD1_Register */ 395 396 /** 397 * @ingroup uart_registers 398 * @defgroup UART_FIFO UART_FIFO 399 * @brief FIFO Data buffer. 400 * @{ 401 */ 402 #define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ 403 #define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ 404 405 /**@} end of group UART_FIFO_Register */ 406 407 /** 408 * @ingroup uart_registers 409 * @defgroup UART_DMA UART_DMA 410 * @brief DMA Configuration. 411 * @{ 412 */ 413 #define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */ 414 #define MXC_F_UART_DMA_TDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */ 415 #define MXC_V_UART_DMA_TDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */ 416 #define MXC_S_UART_DMA_TDMA_EN_DIS (MXC_V_UART_DMA_TDMA_EN_DIS << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */ 417 #define MXC_V_UART_DMA_TDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value */ 418 #define MXC_S_UART_DMA_TDMA_EN_EN (MXC_V_UART_DMA_TDMA_EN_EN << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */ 419 420 #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ 421 #define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ 422 #define MXC_V_UART_DMA_RXDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */ 423 #define MXC_S_UART_DMA_RXDMA_EN_DIS (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */ 424 #define MXC_V_UART_DMA_RXDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */ 425 #define MXC_S_UART_DMA_RXDMA_EN_EN (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */ 426 427 #define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */ 428 #define MXC_F_UART_DMA_TXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */ 429 430 #define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */ 431 #define MXC_F_UART_DMA_RXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL Mask */ 432 433 /**@} end of group UART_DMA_Register */ 434 435 /** 436 * @ingroup uart_registers 437 * @defgroup UART_TX_FIFO UART_TX_FIFO 438 * @brief Transmit FIFO Status register. 439 * @{ 440 */ 441 #define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */ 442 #define MXC_F_UART_TX_FIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */ 443 444 /**@} end of group UART_TX_FIFO_Register */ 445 446 #ifdef __cplusplus 447 } 448 #endif 449 450 #endif /* _UART_REGS_H_ */ 451