1 /*
2  * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0.
5  *
6  * @Date: 2021-04-25 13:59:44
7  * @LastEditTime: 2021-04-30 15:42:30
8  * @Description:  This files is for
9  *
10  * @Modify History:
11  *  Ver   Who        Date         Changes
12  * ----- ------     --------    --------------------------------------
13  */
14 #ifndef FT_BSP_SPI_HW_H
15 #define FT_BSP_SPI_HW_H
16 
17 #ifdef __cplusplus
18 extern "C"
19 {
20 #endif
21 
22 #include "ft_types.h"
23 
24 /* offset map of SPI register */
25 #define SPI_CTRL_R0 0x00       //Ctrl register 0
26 #define SPI_CTRL_R1 0x04       //Ctrl register 1
27 #define SPI_SSI_EN_R 0x08      //SPI enable register
28 #define SPI_MW_CR 0x0c         //Microwire ctrl register
29 #define SPI_SE_R 0x10          //Slave enable register
30 #define SPI_BAUD_R 0x14        //Baudrate set register
31 #define SPI_TXFTL_R 0x18       //Tx threshold register
32 #define SPI_RXFTL_R 0x1c       //Rx threshold register
33 #define SPI_TXFL_R 0x20        //Tx level register
34 #define SPI_RXFL_R 0x24        //Rx level register
35 #define SPI_S_R 0x28           //Status register
36 #define SPI_IM_R 0x2c          //Intr mask register
37 #define SPI_RIS_R 0x34         //Intr status register
38 #define SPI_TXOI_CR 0x38       //TX FIFO overflow intr clear register
39 #define SPI_RXOI_CR 0x3c       //RX FIFO overflow intr clear register
40 #define SPI_RXUI_CR 0x40       //TX FIFO underflow intr clear register
41 #define SPI_MSTI_CR 0x44       //Multi slave intr clear register
42 #define SPI_IC_R 0x48          //Intr clear register
43 #define SPI_DMA_CR 0x4c        //DMA ctrl register
44 #define SPI_DMA_TDL_R 0x50     //DMA TX Data level register
45 #define SPI_DMA_RDL_R 0x54     //DMA RX Data level register
46 #define SPI_ID_R 0x58          //Identification register
47 #define SPI_D_R 0xec           //Data register
48 #define SPI_RX_SAMPLE_DLY 0xfc //RX Data delay register
49 
50     typedef enum
51     {
52         SPI_CTRL_ID_0 = 0,
53         SPI_CTRL_ID_1,
54 
55         NUM_OF_SPI_CTRL,
56     } FSpi_CtrlId_t;
57 
58     typedef enum
59     {
60         SPI_DEV_ID_0 = 0,
61         SPI_DEV_ID_1,
62         SPI_DEV_ID_2,
63         SPI_DEV_ID_3,
64 
65         NUM_OF_SPI_DEV,
66     } FSpi_DevId_t;
67 
68     /* base address of SPI register */
69     const static u32 g_SpiBaseAddr[NUM_OF_SPI_CTRL] = {0x2800c000, 0x28013000};
70 
71     typedef union
72     {
73         u32 data;
74         struct
75         {
76             u32 Dfs : 4; /* 3:0, select data length */
77 #define SPI_DFS_DEFAULT 0x7
78             u32 Frf : 2; /* 5:4, selcet trans mode */
79 #define SPI_FRF_DEFAULT 0x0
80             u32 Scph : 1;               /* 6, serial clock phase */
81 #define SPI_SCPH_SW_CLK_AT_DATA_MID 0x0 /* second edge */
82 #define SPI_SCPH_SW_CLK_AT_DATA_BEG 0x1 /* first edge */
83             u32 Scpol : 1;              /* 7, serial clock Polarity */
84 #define SPI_SCPOL_NOT_ACT_LOW 0x0
85 #define SPI_SCPOL_NOT_ACT_HIGH 0x1
86             u32 Tmod : 2; /* 9:8, ctrl trans mode, indicate if tx rx data is valid */
87 #define SPI_TMOD_TX_RX_MODE 0x0
88 #define SPI_TMOD_TX_MODE 0x1
89 #define SPI_TMOD_RX_MODE 0x2
90 #define SPI_TMOD_EEPROM_MODE 0x3
91             u32 SlvOE : 1; /* 10, enable slave tx logic */
92 #define SPI_SLV_OE_ENABLE 0x0
93 #define SPI_SLV_OE_DISABLE 0x1
94             u32 Srl : 1; /* 11, shift register loopback */
95 #define SPI_SRL_NORMAL_MODE 0x0
96 #define SPI_SRL_TEST_MODE 0x1
97             u32 Cfs : 4; /* 15:12, ctrl data size, applied in Microwire mode */
98 #define SPI_CFS_DEFAULT 0x0
99             u32 Reserve : 16;
100         } val;
101     } FSpi_CtrlReg0_t;
102 
103     typedef union
104     {
105         u32 data;
106         struct
107         {
108             u32 ndf : 16; /* 15:0 valid when TMOD = 10, TMOD = 11 */
109 #define SPI_NDF_DEFAULT 16
110             u32 Reserve : 16;
111         } val;
112     } FSpi_CtrlReg1_t;
113 
114     typedef struct
115     {
116         u32 CPOL;
117         u32 CPHA;
118     } FSpi_ClockMode_t;
119 
120     static const FSpi_ClockMode_t g_FSpi_ClockMode[4] =
121         {
122             {.CPOL = SPI_SCPOL_NOT_ACT_LOW, .CPHA = SPI_SCPH_SW_CLK_AT_DATA_BEG},  /* low level logic, sample at rising edge, shift at falling edge  */
123             {.CPOL = SPI_SCPOL_NOT_ACT_LOW, .CPHA = SPI_SCPH_SW_CLK_AT_DATA_MID},  /* low level logic, sample at falling edge, shift at rising edge */
124             {.CPOL = SPI_SCPOL_NOT_ACT_HIGH, .CPHA = SPI_SCPH_SW_CLK_AT_DATA_MID}, /* high level logic, sample at falling edge, shift at rising edge */
125             {.CPOL = SPI_SCPOL_NOT_ACT_HIGH, .CPHA = SPI_SCPH_SW_CLK_AT_DATA_BEG}, /* high level logic, sample at rising edge, shift at falling edge */
126     };
127 
128     typedef union
129     {
130         u32 data;
131         struct
132         {
133             u32 SsiEn : 1; /* 0, enable or disable all SPI op */
134             u32 Reserve : 31;
135         } val;
136     } FSpi_SsiEnReg_t;
137 
138     typedef union
139     {
140         u32 data;
141         struct
142         {
143             u32 MwMod : 1; /* 0 microwire trans mode */
144 #define SPI_MWMODE_NO_CONTINUOUES 0
145 #define SPI_MWMODE_CONTINUOUES 1
146             u32 Mdd : 1; /* 1 microwire ctrl bit */
147 #define SPI_MWMDD_RXFROM_EXT_DEV 0
148 #define SPI_MWMDD_TXTO_EXT_DEV 1
149             u32 Mhs : 1; /* 2 microwire handshake */
150 #define SPI_MWMHS_DISABLE 0
151 #define SPI_MWMHS_ENABLE 1
152             u32 Reserve : 29;
153         } val;
154     } FSpi_MwcrReg_t;
155 
156     typedef union
157     {
158         u32 data;
159         struct
160         {
161             u32 SelSlave_0 : 1; /* 3:0, select specifc slave device */
162             u32 SelSlave_1 : 1;
163             u32 SelSlave_2 : 1;
164             u32 SelSlave_3 : 1;
165 #define SPI_SE_SELECTED 0x1
166 #define SPI_SE_UNSELECTED 0x0
167             u32 Reserve : 28;
168         } val;
169     } FSpi_SeReg_t;
170 
171     typedef union
172     {
173         u32 data;
174         struct
175         {
176             u32 Sckdv : 16; /* 15:0, SSI clk divider, must be times of 2 */
177 #define SPI_SCKDV_MIN (2)
178 #define SPI_SCKDV_4 (4)
179 #define SPI_SCKDV_8 (8)
180 #define SPI_SCKDV_16 (16)
181 #define SPI_SCKDV_32 (20)
182 #define SPI_SCKDV_64 (28)
183 #define SPI_SCKDV_128 (128)
184 #define SPI_SCKDV_256 (256)
185 #define SPI_SCKDV_1024 (1024)
186 #define SPI_SCKDV_4096 (4096)
187 #define SPI_SCKDV_12800 (12800)
188 #define SPI_SCKDV_56800 (56800)
189 #define SPI_SCKDV_MAX (65534)
190             u32 Reserve : 16;
191         } val;
192     } FSpi_BaudrReg_t;
193 
194     typedef union
195     {
196         u32 data;
197         struct
198         {
199             u32 Tft : 8; /* 7:0, TX FIFO threshold */
200             u32 Reserve : 24;
201         } val;
202 
203     } FSpi_TxFtlrReg_t;
204 
205     typedef union
206     {
207         u32 data;
208         struct
209         {
210             u32 Rft : 8; /* 7:0, RX FIFO threshold */
211             u32 Reserve : 24;
212         } val;
213 
214     } FSpi_RxFtlrReg_t;
215 
216     typedef union
217     {
218         u32 data;
219         struct
220         {
221             u32 Txtfl : 8; /* 7:0, TX FIFO level, num of valid num */
222             u32 Reserve : 24;
223         } val;
224 
225     } FSpi_TxFlrReg_t;
226 
227     typedef union
228     {
229         u32 data;
230         struct
231         {
232             u32 Rxtfl : 8; /* 7:0, RX FIFO level, num of valid num */
233             u32 Reserve : 24;
234         } val;
235 
236     } FSpi_RxFlrReg_t;
237 
238     typedef union
239     {
240         u32 data;
241         struct
242         {
243             u32 Busy : 1; /* 0, SPI bus busy bit */
244             u32 Tfnf : 1; /* 1, tx FIFO not empty */
245 #define SPI_TX_FIFO_FULL 0x0
246 #define SPI_TX_FIFO_NOT_FULL 0x1
247             u32 Tfe : 1; /* 2, tx FIFO empty */
248 #define SPI_TX_FIFO_NOT_EMPTY 0x0
249 #define SPI_TX_FIFO_EMPTY 0x1
250             u32 Rfne : 1; /* 3, rx FIFO not emptu */
251 #define SPI_RX_FIFO_EMPTY 0x0
252 #define SPI_RX_FIFO_NOT_EMPTY 0x1
253             u32 Rff : 1; /* 4, rx FIFO full */
254 #define SPI_RX_FIFO_NOT_FULL 0x0
255 #define SPI_RX_FIFO_FULL 0x1
256             u32 Txe : 1; /* 5, trans error */
257 #define SPI_TX_NO_ERR 0x0
258 #define SPI_TX_ERR 0x1
259             u32 Dcol : 1; /* 6, trans conflict error */
260 #define SPI_TX_NO_COLERR 0x0
261 #define SPI_TX_COLERR 0x1
262             u32 Reserve : 25;
263         } val;
264     } FSpi_StatusReg_t; /* Read-Only */
265 
266     typedef union
267     {
268         u32 IdCode : 32;
269     } FSpi_IDReg_t;
270 
271     typedef union
272     {
273         u32 data;
274         struct
275         {
276             u32 Dr : 16; /* 15:0, RX and TX fifo */
277 #define SPI_8BIT_MASK 0xFF
278 #define SPI_16BIT_MASK 0xFFFF
279             u32 Reserve : 16;
280         } val;
281     } FSpi_DataReg_t;
282 
283     typedef union
284     {
285         u32 data;
286         struct
287         {
288             u32 Rsd : 8; /* 7:0, RX data delay */
289 #define SPI_DEFAULT_RSD 0x6
290             u32 Reserve : 24;
291         } val;
292     } FSpi_RxSampleDlyReg_t;
293 
294 #define SPI_CTL_ID(pCtrl) ((pCtrl)->CtrlId)
295 #define SPI_BASE_ADDR(pCtrl) (g_SpiBaseAddr[SPI_CTL_ID(pCtrl)])
296 
297 /* select slave device */
298 #define SPI_SE_REG(pCtrl) ((FSpi_SeReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_SE_R))
299 /* set speed */
300 #define SPI_BAUDR_REG(pCtrl) ((FSpi_BaudrReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_BAUD_R))
301 #define FSPI_SET_BAUDR(pCtrl, div) (SPI_BAUDR_REG(pCtrl)->val.Sckdv = (div))
302 #define FSPI_GET_BAUDR(pCtrl) (SPI_BAUDR_REG(pCtrl)->val.Sckdv)
303 /* check status */
304 #define SPI_STATUS_REG(pCtrl) ((FSpi_StatusReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_S_R))
305 #define FSPI_TX_FIFO_NOT_EMPTY(pCtrl) (SPI_TX_FIFO_NOT_EMPTY == (SPI_STATUS_REG(pCtrl)->val.Tfe))
306 #define FSPI_RX_FIFO_EMPTY(pCtrl) (SPI_RX_FIFO_EMPTY == (SPI_STATUS_REG(pCtrl)->val.Rfne))
307 /* enable/disable spi bus */
308 #define SPI_SSIEN_REG(pCtrl) ((FSpi_SsiEnReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_SSI_EN_R))
309 #define FSPI_ENABLE(pCtrl) (SPI_SSIEN_REG(pCtrl)->val.SsiEn = 1)
310 #define FSPI_DISABLE(pCtrl) (SPI_SSIEN_REG(pCtrl)->val.SsiEn = 0)
311 /* shortcut to access register */
312 #define SPI_CTRL0_REG(pCtrl) ((FSpi_CtrlReg0_t *)(SPI_BASE_ADDR(pCtrl) + SPI_CTRL_R0))
313 #define SPI_CTRL1_REG(pCtrl) ((FSpi_CtrlReg1_t *)(SPI_BASE_ADDR(pCtrl) + SPI_CTRL_R1))
314 #define SPI_TXFTL_REG(pCtrl) ((FSpi_TxFtlrReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_TXFTL_R))
315 #define SPI_RXFTL_REG(pCtrl) ((FSpi_RxFtlrReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_RXFTL_R))
316 #define SPI_TXFL_REG(pCtrl) ((FSpi_TxFlrReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_TXFL_R))
317 #define SPI_RXFL_REG(pCtrl) ((FSpi_RxFlrReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_RXFL_R))
318 #define SPI_ID_REG(pCtrl) ((FSpi_IDReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_ID_R))
319 #define FSPI_GET_ID(pCtrl) (SPI_ID_REG(pCtrl)->IdCode)
320 #define SPI_DATA_REG(pCtrl) ((FSpi_DataReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_D_R))
321 #define FSPI_READ_DATA(pCtrl) (u16)(SPI_DATA_REG(pCtrl)->val.Dr)
322 #define FSPI_WRITE_DATA(pCtrl, dat) (SPI_DATA_REG(pCtrl)->val.Dr = (u16)(dat))
323 #define SPI_RXSAMPLE_DLY_REG(pCtrl) ((FSpi_RxSampleDlyReg_t *)(SPI_BASE_ADDR(pCtrl) + SPI_RX_SAMPLE_DLY))
324 #define SPI_MWCTRL_REG(pCtrl) ((FSpi_MwcrReg_t *)SPI_BASE_ADDR(pCtrl) + SPI_MW_CR)
325 
326 #ifdef __cplusplus
327 }
328 #endif
329 
330 #endif
331