Home
last modified time | relevance | path

Searched defs:P (Results 1 – 25 of 29) sorted by relevance

12

/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/
A Dhal_pinctrl_v2.c135 #define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) argument
136 #define RK_SET_DS_1(B, P, p, v) SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) argument
157 #define RK_SET_DS_0(B, P, p, v) SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) argument
158 #define RK_SET_DS_1(B, P, p, v) SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) argument
159 #define RK_SET_DS_2(B, P, p, v) SET_DS_2(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN) argument
190 #define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) argument
191 #define RK_SET_P_1(B, P, p, v) SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) argument
212 #define RK_SET_P_0(B, P, p, v) SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) argument
213 #define RK_SET_P_1(B, P, p, v) SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) argument
214 #define RK_SET_P_2(B, P, p, v) SET_P_2(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN) argument
[all …]
/bsp/nrf5x/nrf5340/board/
A Dnrfx_config.h371 #define NRF_PERIPH(P) P##_NS argument
373 #define NRF_PERIPH(P) P##_S argument
/bsp/microchip/same70/bsp/same70b/include/component/
A Dpio.h87 … uint32_t P:32; /**< bit: 0..31 PIO Enable */ member
238 … uint32_t P:32; /**< bit: 0..31 PIO Disable */ member
389 … uint32_t P:32; /**< bit: 0..31 PIO Status */ member
540 … uint32_t P:32; /**< bit: 0..31 Output Enable */ member
691 … uint32_t P:32; /**< bit: 0..31 Output Disable */ member
842 … uint32_t P:32; /**< bit: 0..31 Output Status */ member
993 … uint32_t P:32; /**< bit: 0..31 Input Filter Enable */ member
1144 … uint32_t P:32; /**< bit: 0..31 Input Filter Disable */ member
1295 … uint32_t P:32; /**< bit: 0..31 Input Filter Status */ member
1446 … uint32_t P:32; /**< bit: 0..31 Set Output Data */ member
[all …]
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_cau3.c3183 …CAU3_Type *base, const uint8_t *P, size_t sizeP, size_t sizeE, uint8_t *result, size_t *resultSize) in CAU3_PKHA_ModRR()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/
A Dhpm_mmc_regs.h53 __RW uint32_t P; /* 0xA4: Tracking Configuration coef trigger cfg P */ member
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Include/
A Defm32g_gpio.h40 GPIO_P_TypeDef P[6]; /**< Port configuration bits */ member
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Include/
A Defm32gg_gpio.h40 GPIO_P_TypeDef P[6]; /**< Port configuration bits */ member
/bsp/tae32f5300/Libraries/CMSIS/Device/Tai_action/TAE32F53xx/Include/
A Dtae32f53xx.h559 … __I uint32_t P; /*!< Address offset: 0x28: ECU P Data Read Register */ member
/bsp/apm32/libraries/APM32F4xx_Library/Device/Geehy/APM32F4xx/Include/
A Dapm32f4xx.h6891 __IOM uint32_t P; member
/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/
A Dmb9bf506r.h3593 __IO uint8_t P : 1; member
3855 __IO uint8_t P : 1; member
/bsp/renesas/rzt2m_rsk/rzt/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G074.h5722 …__IOM uint8_t P[25]; /*!< (@ 0x00000000) Port [0..24] Register … member
14578 …__IOM uint8_t P : 1; /*!< [4..4] Positive-Phase Output (P) Control … member
A DR9A07G075.h6003 …__IOM uint8_t P[25]; /*!< (@ 0x00000000) Port [0..24] Register … member
22300 …__IOM uint8_t P : 1; /*!< [4..4] Positive-Phase Output (P) Control … member
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/
A Dmb9b610s.h4611 __IO uint8_t P : 1; member
4873 __IO uint8_t P : 1; member
A Dmb9b610t.h4831 __IO uint8_t P : 1; member
5084 __IO uint8_t P : 1; member
/bsp/renesas/ra4m2-eco/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA4M2AD.h5912 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G084.h6010 …__IOM uint8_t P[25]; /*!< (@ 0x00000000) Port [0..24] Register … member
28022 …__IOM uint8_t P : 1; /*!< [4..4] Positive-Phase Output (P) Control … member
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2824 …__IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Reg… member
14702 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2824 …__IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Reg… member
14702 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
/bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2824 …__IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Reg… member
14702 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
/bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2824 …__IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Reg… member
14702 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
/bsp/renesas/rzn2l_etherkit/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR9A07G084.h6010 …__IOM uint8_t P[25]; /*!< (@ 0x00000000) Port [0..24] Register … member
28022 …__IOM uint8_t P : 1; /*!< [4..4] Positive-Phase Output (P) Control … member
/bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA4E2B9.h7508 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
/bsp/renesas/ra6e2-fpb/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA6E2BB.h7478 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA6M3AH.h10907 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
/bsp/renesas/ebf_qi_min_6m5/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA6M5BH.h8376 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member

Completed in 5487 milliseconds

12