1 /**************************************************************** 2 KPIT Cummins Infosystems Ltd, Pune, India. 1-April-2006. 3 4 This program is distributed in the hope that it will be useful, 5 but WITHOUT ANY WARRANTY; without even the implied warranty of 6 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 7 8 *****************************************************************/ 9 /****************************************************************/ 10 /* M16C/60 62P Include File */ 11 /****************************************************************/ 12 13 14 /*------------------------------------------------------ 15 Processor mode register 0 //0x0004 16 ------------------------------------------------------*/ 17 union st_pm0 { /* union PM0 */ 18 struct { /* Bit Access */ 19 unsigned char PM0_0:1; /* Processor mode bit 0 */ 20 unsigned char PM0_1:1; /* Processor mode bit 1 */ 21 unsigned char PM0_2:1; /* R/W mode select bit */ 22 unsigned char PM0_3:1; /* Software reset bit */ 23 unsigned char PM0_4:1; /* Multiplexed bus space select bit 0 */ 24 unsigned char PM0_5:1; /* Multiplexed bus space select bit 1 */ 25 unsigned char PM0_6:1; /* Port P40 to P43 function select bit */ 26 unsigned char PM0_7:1; /* BCLK output disable bit */ 27 } BIT; /* */ 28 unsigned char BYTE; /* Byte Access */ 29 }; /* */ 30 31 /*------------------------------------------------------ 32 Processor mode register 1 //0x0005 33 ------------------------------------------------------*/ 34 union st_pm1 { /* union PM1 */ 35 struct { /* Bit Access */ 36 unsigned char PM1_0:1; /* CS2 area switching bit */ 37 unsigned char PM1_1:1; /* Port P3_4 to P3_7 function select bit */ 38 unsigned char PM1_2:1; /* Watch dog timer function select bit */ 39 unsigned char PM1_3:1; /* Intermal reserved area expansion bit */ 40 unsigned char PM1_4:1; /* Memory area expansion bit */ 41 unsigned char PM1_5:1; /* Memory area expansion bit */ 42 unsigned char PM1_6:1; /* Reserved bit */ 43 unsigned char PM1_7:1; /* PM17 - Wait bit */ 44 } BIT; /* */ 45 unsigned char BYTE; /* Byte Access */ 46 }; /* */ 47 48 /*------------------------------------------------------ 49 System clock control register 0 //0x0006 50 ------------------------------------------------------*/ 51 union st_cm0 { /* union CM0 */ 52 struct { /* Bit Access */ 53 unsigned char CM0_0:1; /* Clock output function select bit */ 54 unsigned char CM0_1:1; /* Clock output function select bit */ 55 unsigned char CM0_2:1; /* WAIT peripheral function clock stop bit */ 56 unsigned char CM0_3:1; /* Xcin-Xcout drive capacity select bit*/ 57 unsigned char CM0_4:1; /* Port Xc select bit */ 58 unsigned char CM0_5:1; /* Main clock stop bit */ 59 unsigned char CM0_6:1; /* Main clock division select bit 0 */ 60 unsigned char CM0_7:1; /* System clock select bit */ 61 } BIT; /* */ 62 unsigned char BYTE; /* Byte Access */ 63 }; /* system clock control register 0 */ 64 65 66 /*------------------------------------------------------ 67 System clock control register 1 //0x0007 68 ------------------------------------------------------*/ 69 union st_cm1 { /* union CM1 */ 70 struct { /* Bit Access */ 71 unsigned char CM1_0:1; /* All clock stop control bit */ 72 unsigned char :1; /* Reserved bit always set to 0 */ 73 unsigned char :1; /* Reserved bit always set to 0 */ 74 unsigned char :1; /* Reserved bit always set to 0 */ 75 unsigned char :1; /* Reserved bit always set to 0 */ 76 unsigned char CM1_5:1; /* Xin-Xouts drive capacity select bit */ 77 unsigned char CM1_6:1; /* Main clock division select bit 1 */ 78 unsigned char CM1_7:1; /* Main clock division select bit 1 */ 79 } BIT; /* */ 80 unsigned char BYTE; /* Byte Access */ 81 }; /* system clock control register 1 */ 82 83 84 /*------------------------------------------------------ 85 Chip select control register //0x0008 86 ------------------------------------------------------*/ 87 union st_csr { /* union CSR */ 88 struct { /* Bit Access */ 89 unsigned char CS0 :1; /* CS0~ output enable bit */ 90 unsigned char CS1 :1; /* CS1~ output enable bit */ 91 unsigned char CS2 :1; /* CS2~ output enable bit */ 92 unsigned char CS3 :1; /* CS3~ output enable bit */ 93 unsigned char CS0W:1; /* CS0~ wait bit */ 94 unsigned char CS1W:1; /* CS1~ wait bit */ 95 unsigned char CS2W:1; /* CS2~ wait bit */ 96 unsigned char CS3W:1; /* CS3~ wait bit */ 97 } BIT; /* */ 98 unsigned char BYTE; /* Byte Access */ 99 }; /* Chip select control register */ 100 101 /*------------------------------------------------------ 102 Address match interrupt enable register //0x0009 103 ------------------------------------------------------*/ 104 union st_aier { /* union AIER */ 105 struct { /* Bit Access */ 106 unsigned char AIER0:1; /* Address match interrupt0 enable bit*/ 107 unsigned char AIER1:1; /* Address match interrupt1 enable bit*/ 108 unsigned char :1; /* Nothing assigned */ 109 unsigned char :1; /* Nothing assigned */ 110 unsigned char :1; /* Nothing assigned */ 111 unsigned char :1; /* Nothing assigned */ 112 unsigned char :1; /* Nothing assigned */ 113 unsigned char :1; /* Nothing assigned */ 114 } BIT; /* */ 115 unsigned char BYTE; /* Byte Access */ 116 }; /* Address match interrupt enable register */ 117 118 119 /*------------------------------------------------------ 120 Protect register //0x000A 121 -----------------------------------------------------*/ 122 union st_prcr { /* union PRCR */ 123 struct { /* Bit Access */ 124 unsigned char PRC0:1; /* Enables writing to system clock control registers 0 & 1 */ 125 unsigned char PRC1:1; /* Enables writing to processor mode registers 0 & 1 */ 126 unsigned char PRC2:1; /* Enables writing to port P9 direction register & SI/Oi control register(i=3,4)*/ 127 unsigned char PRC3:1; /* Enable writting to Power supply detection register 2 and Power supply down detection register */ 128 unsigned char :1; /* Nothing assigned */ 129 unsigned char :1; /* Nothing assigned */ 130 unsigned char :1; /* Nothing assigned */ 131 unsigned char :1; /* Nothing assigned */ 132 } BIT; /* */ 133 unsigned char BYTE; /* Byte Access */ 134 }; /* Protect register */ 135 136 /*------------------------------------------------------ 137 Data bank register //0x000B 138 ------------------------------------------------------*/ 139 union st_dbr { /* union DBR */ 140 struct { /* Bit Access */ 141 unsigned char :1; /* Nothing assigned */ 142 unsigned char :1; /* Nothing assigned */ 143 unsigned char OFS :1; /* Offset bit */ 144 unsigned char BSR0:1; /* Bank select bit 0 */ 145 unsigned char BSR1:1; /* Bank select bit 1 */ 146 unsigned char BSR2:1; /* Bank select bit 2 */ 147 unsigned char :1; /* Nothing assigned */ 148 unsigned char :1; /* Nothing assigned */ 149 } BIT; /* */ 150 unsigned char BYTE; /* Data bank register */ 151 }; 152 153 /*------------------------------------------------------ 154 Oscillation stop detection register //0x000C 155 ------------------------------------------------------*/ 156 union st_cm2 { /* union CM2 */ 157 struct { /* Bit Access */ 158 unsigned char CM2_0:1; /* Oscillation stop detection bit */ 159 unsigned char CM2_1:1; /* Main clock switch bit */ 160 unsigned char CM2_2:1; /* Oscillation stop detection status */ 161 unsigned char CM2_3:1; /* Clock monitor bit */ 162 unsigned char :1; /* Nothing assigned */ 163 unsigned char :1; /* Nothing assigned */ 164 unsigned char :1; /* Nothing assigned */ 165 unsigned char CM2_7:1; /* Operation select bit(when an oscillation stop is detected) */ 166 } BIT; /* */ 167 unsigned char BYTE; /* Oscillation stop detection register */ 168 }; 169 170 /*------------------------------------------------------ 171 Watchdog timer control register //0x000f 172 -----------------------------------------------------*/ 173 union st_wdc { /* union WDC */ 174 struct { /* Bit Access */ 175 unsigned char B0:1; /* High-order bit of watchdog timer */ 176 unsigned char B1:1; /* High-order bit of watchdog timer */ 177 unsigned char B2:1; /* High-order bit of watchdog timer */ 178 unsigned char B3:1; /* High-order bit of watchdog timer */ 179 unsigned char B4:1; /* High-order bit of watchdog timer */ 180 unsigned char WDC5:1; /* Cold start / warm start discrimination flag */ 181 unsigned char B6:1; /* Reserved bit, must always be 0 */ 182 unsigned char WDC7:1; /* Prescaler select bit */ 183 } BIT; /* */ 184 unsigned char BYTE; /* Byte Access */ 185 }; /* Watchdog timer control register */ 186 187 /*------------------------------------------------------ 188 Address match interrupt register 0 //0x0010 189 -----------------------------------------------------*/ 190 union st_rmad0 { 191 struct{ 192 unsigned char RMAD0L; /* Address match interrupt register 0 low 8 bit */ 193 unsigned char RMAD0M; /* Address match interrupt register 0 mid 8 bit */ 194 unsigned char RMAD0H; /* Address match interrupt register 0 high 8 bit */ 195 unsigned char NC; /* non use */ 196 } BYTE; /* Byte access */ 197 unsigned long DWORD; /* Word Access */ 198 }; /* Address match interrupt register 0 32 bit */ 199 200 /*------------------------------------------------------ 201 Address match interrupt register 1 //0x0014 202 -----------------------------------------------------*/ 203 union st_rmad1 { 204 struct{ 205 unsigned char RMAD1L; /* Address match interrupt register 1 low 8 bit */ 206 unsigned char RMAD1M; /* Address match interrupt register 1 mid 8 bit */ 207 unsigned char RMAD1H; /* Address match interrupt register 1 high 8 bit */ 208 unsigned char NC; /* non use */ 209 } BYTE; /* Byte access */ 210 unsigned long DWORD; /* Word Access */ 211 }; /* Address match interrupt register 1 32 bit */ 212 213 /*------------------------------------------------------ 214 Voltage Detection Register 1 //0x0019 215 -----------------------------------------------------*/ 216 union st_vcr1 { /* union VCR1 */ 217 struct { /* Bit Access */ 218 unsigned char B0:1; /* Reserved bit,must be 0 */ 219 unsigned char B1:1; /* Reserved bit,must be 0 */ 220 unsigned char B2:1; /* Reserved bit,must be 0 */ 221 unsigned char VC1_3:1; /* Voltage down monitor flag */ 222 unsigned char B4:1; /* Reserved bit,must be 0 */ 223 unsigned char B5:1; /* Reserved bit,must be 0 */ 224 unsigned char B6:1; /* Reserved bit, must always be 0 */ 225 unsigned char B7:1; /* Reserved bit,must be 0 */ 226 } BIT; /* */ 227 unsigned char BYTE; /* Byte Access */ 228 }; /* Voltage Detection Register 1 */ 229 230 /*------------------------------------------------------ 231 Voltage Detection Register 2 //0x001A 232 -----------------------------------------------------*/ 233 union st_vcr2 { /* union VCR2 */ 234 struct { /* Bit Access */ 235 unsigned char B0:1; /* Reserved bit,must be 0 */ 236 unsigned char B1:1; /* Reserved bit,must be 0 */ 237 unsigned char B2:1; /* Reserved bit,must be 0 */ 238 unsigned char B3:1; /* Reserved bit,must be 0 */ 239 unsigned char B4:1; /* Reserved bit,must be 0 */ 240 unsigned char B5:1; /* Reserved bit,must be 0 */ 241 unsigned char VC2_6:1; /* Reset area monitor bit */ 242 unsigned char VC2_7:1; /* Voltage down monitor bit */ 243 } BIT; /* */ 244 unsigned char BYTE; /* Byte Access */ 245 }; /* Voltage Detection Register 1 */ 246 247 /*------------------------------------------------------ 248 Chip select expansion control register//0x001B 249 -----------------------------------------------------*/ 250 union st_cse { /* union CSE */ 251 struct { /* Bit Access */ 252 unsigned char CSE00W:1; /* CS0~ wait expansion bit */ 253 unsigned char CSE01W:1; /* CS0~ wait expansion bit */ 254 unsigned char CSE10W:1; /* CS1~ wait expansion bit */ 255 unsigned char CSE11W:1; /* CS1~ wait expansion bit */ 256 unsigned char CSE20W:1; /* CS2~ wait expansion bit */ 257 unsigned char CSE21W:1; /* CS2~ wait expansion bit */ 258 unsigned char CSE30W:1; /* CS3~ wait expansion bit */ 259 unsigned char CSE31W:1; /* CS3~ wait expansion bit */ 260 } BIT; /* */ 261 unsigned char BYTE; /* Byte Access */ 262 }; /* Chip select expansion control register */ 263 264 /*------------------------------------------------------ 265 PLL control register 0 //0x001C 266 -----------------------------------------------------*/ 267 union st_plc0 { /* union */ 268 struct { /* Bit Access */ 269 unsigned char PLC00:1; /* Programmable counter select bit */ 270 unsigned char PLC01:1; /* Programmable counter select bit */ 271 unsigned char PLC02:1; /* Programmable counter select bit */ 272 unsigned char :1; /* Nothing assigned */ 273 unsigned char :1; /* Reserved bit,set to one */ 274 unsigned char :1; /* Reserved bit,set to zero */ 275 unsigned char :1; /* Reserved bit,set to zero */ 276 unsigned char PLC07:1; /* Operation enable bit */ 277 } BIT; /* */ 278 unsigned char BYTE; /* Byte Access */ 279 }; /* PLL control register 0 */ 280 281 /*------------------------------------------------------ 282 Processor mode register 2 //0x001E 283 -----------------------------------------------------*/ 284 union st_pm2 { /* union */ 285 struct { /* Bit Access */ 286 unsigned char PM2_0:1; /* Specifying wait when accessing SFR at PLL operation */ 287 unsigned char PM2_1:1; /* System clock protective bit */ 288 unsigned char PM2_2:1; /* WDT count source protective bit */ 289 unsigned char :1; /* Reserved bit,set to zero */ 290 unsigned char :1; /* Reserved bit,set to zero */ 291 unsigned char :1; /* Nothing assigned */ 292 unsigned char :1; /* Nothing assigned */ 293 unsigned char :1; /* Nothing assigned */ 294 } BIT; /* */ 295 unsigned char BYTE; /* Byte Access */ 296 }; /* Processor mode register 2 */ 297 298 /*------------------------------------------------------ 299 Power supply down detection register //0x001F 300 -----------------------------------------------------*/ 301 union st_d4int { /* union */ 302 struct { /* Bit Access */ 303 unsigned char D40:1; /* Power supply down detection interrupt enable bit */ 304 unsigned char D41:1; /* STOP mode deactivation control bit */ 305 unsigned char D42:1; /* Power supply change detection flag */ 306 unsigned char D43:1; /* WDT overflow detect flag */ 307 unsigned char DF0:1; /* Sampling clock select bit */ 308 unsigned char DF1:1; /* Sampling clock select bit */ 309 unsigned char :1; /* Nothing assigned */ 310 unsigned char :1; /* Nothing assigned */ 311 } BIT; /* */ 312 unsigned char BYTE; /* Byte Access */ 313 }; /* Power supply down detection register */ 314 315 /*------------------------------------------------------ 316 DMA0 source pointer //0x0020 317 -----------------------------------------------------*/ 318 union st_sar0 { 319 struct{ 320 unsigned char SAR01; /* DMA0 source pointer low 8 bit */ 321 unsigned char SAR0M; /* DMA0 source pointer mid 8 bit */ 322 unsigned char SAR0H; /* DMA0 source pointer high 8 bit */ 323 unsigned char NC; /* non use */ 324 } BYTE; /* Byte access */ 325 unsigned long DWORD; /* Word Access */ 326 }; /* DMA0 source pointer 32 bit */ 327 328 /*------------------------------------------------------ 329 DMA1 source pointer //0x0030 330 -----------------------------------------------------*/ 331 union st_sar1 { 332 struct{ 333 unsigned char SAR11; /* DMA1 source pointer low 8 bit */ 334 unsigned char SAR1M; /* DMA1 source pointer mid 8 bit */ 335 unsigned char SAR1H; /* DMA1 source pointer high 8 bit */ 336 unsigned char NC; /* non use */ 337 } BYTE; /* Byte access */ 338 unsigned long DWORD; /* Word Access */ 339 }; /* DMA1 source pointer 32 bit */ 340 341 /*------------------------------------------------------ 342 DMA0 destination pointer //0x0024 343 -----------------------------------------------------*/ 344 union st_dar0 { /* DMA0 destination pointer 32 bit */ 345 struct{ 346 unsigned char DAR0L; /* DMA0 destination pointer low 8 bit */ 347 unsigned char DAR0M; /* DMA0 destination pointer mid 8 bit */ 348 unsigned char DAR0H; /* DMA0 destination pointer high 8 bit */ 349 unsigned char NC; /* non use */ 350 } BYTE; /* Byte access */ 351 unsigned long DWORD; /* Word Access */ 352 }; 353 354 /*------------------------------------------------------ 355 DMA1 destination pointer //0x0034 356 -----------------------------------------------------*/ 357 union st_dar1 { /* DMA1 destination pointer 32 bit */ 358 struct{ 359 unsigned char DAR1L; /* DMA1 destination pointer low 8 bit */ 360 unsigned char DAR1M; /* DMA1 destination pointer mid 8 bit */ 361 unsigned char DAR1H; /* DMA1 destination pointer high 8 bit */ 362 unsigned char NC; /* non use */ 363 } BYTE; /* Byte access */ 364 unsigned long DWORD; /* Word Access */ 365 }; 366 367 /*------------------------------------------------------ 368 DMA0 transfer counter //0x0028 369 -----------------------------------------------------*/ 370 union st_tcr0 { /* DMA0 transfer counter 16 bit */ 371 struct{ 372 unsigned char TCR0L; /* DMA0 transfer counter low 8 bit */ 373 unsigned char TCR0H; /* DMA0 transfer counter high 8 bit */ 374 } BYTE; /* Byte access */ 375 unsigned short WORD; /* Word Access */ 376 }; 377 378 /*------------------------------------------------------ 379 DMA1 transfer counter //0x0038 380 -----------------------------------------------------*/ 381 union st_tcr1 { /* DMA1 transfer counter 16 bit */ 382 struct{ 383 unsigned char TCR1L; /* DMA1 transfer counter low 8 bit */ 384 unsigned char TCR1H; /* DMA1 transfer counter high 8 bit */ 385 } BYTE; /* Byte access */ 386 unsigned short WORD; /* Word Access */ 387 }; 388 389 /*------------------------------------------------------ 390 DMA0 control register //0x002c 391 ------------------------------------------------------*/ 392 union st_dm0con { /* DMA0 control register */ 393 struct{ 394 unsigned char DMBIT:1; /* Transfer unit bit select bit */ 395 unsigned char DMASL:1; /* Repeat transfer mode select bit */ 396 unsigned char DMAS :1; /* DMA request bit */ 397 unsigned char DMAE :1; /* DMA enable bit */ 398 unsigned char DSD :1; /* Source address direction select bit */ 399 unsigned char DAD :1; /* Destination address direction select bit */ 400 unsigned char :1; 401 unsigned char :1; 402 }BIT; 403 unsigned char BYTE; 404 }; 405 406 /*------------------------------------------------------ 407 DMA1 control register //0x003c 408 ------------------------------------------------------*/ 409 union st_dm1con { /* DMA1 control register union */ 410 struct{ 411 unsigned char DMBIT:1; /* Transfer unit bit select bit */ 412 unsigned char DMASL:1; /* Repeat transfer mode select bit */ 413 unsigned char DMAS :1; /* DMA request bit */ 414 unsigned char DMAE :1; /* DMA enable bit */ 415 unsigned char DSD :1; /* Source address direction select bit */ 416 unsigned char DAD :1; /* Destination address direction select bit */ 417 unsigned char :1; /*Nothing assigned */ 418 unsigned char :1; /*Nothing assigned */ 419 }BIT; 420 unsigned char BYTE; 421 }; 422 423 union st_icr { /* interrupt control registers */ 424 struct{ 425 unsigned char ILVL0:1; /* Interrupt priority level select bit */ 426 unsigned char ILVL1:1; /* Interrupt priority level select bit */ 427 unsigned char ILVL2:1; /* Interrupt priority level select bit */ 428 unsigned char IR :1; /* Interrupt request bit */ 429 unsigned char POL :1; /* Polarity select bit */ 430 unsigned char :1; /* Reserved bit, set to 0 */ 431 unsigned char :1; /* Nothing assigned */ 432 unsigned char :1; /* Nothing assigned */ 433 }BIT; 434 unsigned char BYTE; 435 }; 436 437 union st_icr1 { /* interrupt control registers */ 438 struct{ 439 unsigned char ILVL0:1; /* Interrupt priority level select bit */ 440 unsigned char ILVL1:1; /* Interrupt priority level select bit */ 441 unsigned char ILVL2:1; /* Interrupt priority level select bit */ 442 unsigned char IR :1; /* Interrupt request bit */ 443 unsigned char :1; /* Nothing assigned */ 444 unsigned char :1; /* Nothing assigned */ 445 unsigned char :1; /* Nothing assigned */ 446 unsigned char :1; /* Nothing assigned */ 447 }BIT; 448 unsigned char BYTE; 449 }; 450 451 /*------------------------------------------------------ 452 bcnic //0x004a 453 ------------------------------------------------------*/ 454 union st_bcnic { /* interrupt control registers*/ 455 struct{ 456 unsigned char ILVL0_BCNIC:1;/* Interrupt priority level select bit */ 457 unsigned char ILVL1_BCNIC:1;/* Interrupt priority level select bit */ 458 unsigned char ILVL2_BCNIC:1;/* Interrupt priority level select bit */ 459 unsigned char IR_BCNIC :1;/* Interrupt request bit */ 460 unsigned char :1; 461 unsigned char :1; 462 unsigned char :1; 463 unsigned char :1; 464 }BIT; 465 unsigned char BYTE; 466 }; 467 468 /*------------------------------------------------------ 469 dm0ic //0x004b 470 ------------------------------------------------------*/ 471 union st_dm0ic { /* interrupt control registers*/ 472 struct{ 473 unsigned char ILVL0_DM0IC:1;/* Interrupt priority level select bit */ 474 unsigned char ILVL1_DM0IC:1;/* Interrupt priority level select bit */ 475 unsigned char ILVL2_DM0IC:1;/* Interrupt priority level select bit */ 476 unsigned char IR_DM0IC :1;/* Interrupt request bit */ 477 unsigned char :1; 478 unsigned char :1; 479 unsigned char :1; 480 unsigned char :1; 481 }BIT; 482 unsigned char BYTE; 483 }; 484 485 /*------------------------------------------------------ 486 Flash identification register //0x01b4 487 ------------------------------------------------------*/ 488 union st_fidr { /* Flash identification register */ 489 struct{ 490 unsigned char FIDR0:1; /* Flash identification value */ 491 unsigned char FIDR1:1; /* Flash identification value */ 492 unsigned char :1; /* Nothing assigned */ 493 unsigned char :1; /* Nothing assigned */ 494 unsigned char :1; /* Nothing assigned */ 495 unsigned char :1; /* Nothing assigned */ 496 unsigned char :1; /* Nothing assigned */ 497 unsigned char :1; /* Nothing assigned */ 498 }BIT; 499 unsigned char BYTE; 500 }; 501 502 /*------------------------------------------------------ 503 Flash memory control register 1 //0x01b5 504 ------------------------------------------------------*/ 505 union st_fmr1 { /* Flash identification register */ 506 struct{ 507 unsigned char :1; /* Reserved bit */ 508 unsigned char FMR11:1; /* EW1 mode select bit */ 509 unsigned char :1; /* Reserved bit */ 510 unsigned char :1; /* Reserved bit */ 511 unsigned char :1; /* Reserved bit */ 512 unsigned char :1; /* Reserved bit */ 513 unsigned char FMR16:1; /* Lock bit status flag */ 514 unsigned char :1; /* Reserved bit */ 515 }BIT; 516 unsigned char BYTE; 517 }; 518 519 /*------------------------------------------------------ 520 Flash memory control register 0 //0x01b7 521 ------------------------------------------------------*/ 522 union st_fmr0 { /* Flash identification register */ 523 struct{ 524 unsigned char FMR00:1; /* RY/BY~ status flag */ 525 unsigned char FMR01:1; /* EW0 mode select bit */ 526 unsigned char FMR02:1; /* Lock bit disable bit */ 527 unsigned char FMSTP:1; /* Flash memory stop bit */ 528 unsigned char :1; /* Reserved bit */ 529 unsigned char FMR05:1; /* User ROM area select bit */ 530 unsigned char FMR06:1; /* Program status flag */ 531 unsigned char FMR07:1; /* Erase status flag */ 532 }BIT; 533 unsigned char BYTE; 534 }; 535 536 /*------------------------------------------------------ 537 Address match interrupt register 2 //0x01b8 538 -----------------------------------------------------*/ 539 union st_rmad2 { 540 struct{ 541 unsigned char RMAD2L; /* Address match interrupt register 2 low 8 bit */ 542 unsigned char RMAD2M; /* Address match interrupt register 2 mid 8 bit */ 543 unsigned char RMAD2H; /* Address match interrupt register 2 high 8 bit */ 544 unsigned char NC; /* non use */ 545 } BYTE; /* Byte access */ 546 unsigned long DWORD; /* Word Access */ 547 }; /* Address match interrupt register 2 32 bit */ 548 549 550 /*------------------------------------------------------ 551 Address match interrupt enable register 2 //0x01bb 552 ------------------------------------------------------*/ 553 union st_aier2 { /* Address match interrupt enable register 2 */ 554 struct{ 555 unsigned char AIER20:1; /* Address match interrupt 2 enable bit */ 556 unsigned char AIER21:1; /* Address match interrupt 3 enable bit */ 557 unsigned char :1; /* Nothing assigned */ 558 unsigned char :1; /* Nothing assigned */ 559 unsigned char :1; /* Nothing assigned */ 560 unsigned char :1; /* Nothing assigned */ 561 unsigned char :1; /* Nothing assigned */ 562 unsigned char :1; /* Nothing assigned */ 563 }BIT; 564 unsigned char BYTE; 565 }; 566 567 /*------------------------------------------------------ 568 Address match interrupt register 3 //0x01bc 569 -----------------------------------------------------*/ 570 union st_rmad3 { 571 struct{ 572 unsigned char RMAD3L; /* Address match interrupt register 3 low 8 bit */ 573 unsigned char RMAD3M; /* Address match interrupt register 3 mid 8 bit */ 574 unsigned char RMAD3H; /* Address match interrupt register 3 high 8 bit */ 575 unsigned char NC; /* non use */ 576 } BYTE; /* Byte access */ 577 unsigned long DWORD; /* Word Access */ 578 }; /* Address match interrupt register 3 32 bit */ 579 580 /*------------------------------------------------------ 581 Peripheral clock select register //0x025e 582 ------------------------------------------------------*/ 583 union st_pclkr { /* Peripheral clock select register */ 584 struct{ 585 unsigned char PCLK0 :1; /* TimerA,B clock select bit */ 586 unsigned char PCLK1 :1; /* SI/O clock select bit */ 587 unsigned char :1; /* Reserved bit,set to 0 */ 588 unsigned char :1; /* Reserved bit,set to 0 */ 589 unsigned char :1; /* Reserved bit,set to 0 */ 590 unsigned char :1; /* Reserved bit,set to 0 */ 591 unsigned char :1; /* Reserved bit,set to 0 */ 592 unsigned char :1; /* Reserved bit,set to 0 */ 593 }BIT; 594 unsigned char BYTE; 595 }; 596 597 /*------------------------------------------------------ 598 Timer B3,4,5 Count start flag //0x0340 599 ------------------------------------------------------*/ 600 union st_tbsr { /* union tbsr */ 601 struct { /* Bit Access */ 602 unsigned char :1; /* Nothing Assigned */ 603 unsigned char :1; /* Nothing Assigned */ 604 unsigned char :1; /* Nothing Assigned */ 605 unsigned char :1; /* Nothing Assigned */ 606 unsigned char :1; /* Nothing Assigned */ 607 unsigned char TB3S:1; /* Timer B3 count start flag */ 608 unsigned char TB4S:1; /* Timer B4 count start flag */ 609 unsigned char TB5S:1; /* Timer B5 count start flag */ 610 } BIT; /* */ 611 unsigned char BYTE; /* Byte Access */ 612 }; /* Timer B3,4,5 Count start flag */ 613 614 /*------------------------------------------------------ 615 Three-phase PWM control regester 0 //0x0348 616 ------------------------------------------------------*/ 617 union st_invc0 { /* union invc0 */ 618 struct { /* Bit Access */ 619 unsigned char INV00:1;/* Effective interrupt output polarity select bit */ 620 unsigned char INV01:1;/* Effective interrupt output specification bit */ 621 unsigned char INV02:1;/* Mode select bit */ 622 unsigned char INV03:1;/* Output control bit */ 623 unsigned char INV04:1;/* Positive and negative phases concurrent L output disable function enable bit */ 624 unsigned char INV05:1;/* Positive and negative phases concurrent L output detect flag */ 625 unsigned char INV06:1;/* Modulation mode select bit */ 626 unsigned char INV07:1;/* Software trigger bit */ 627 } BIT; /* */ 628 unsigned char BYTE; /* Byte Access */ 629 }; /* */ 630 631 /*------------------------------------------------------ 632 Three-phase PWM control regester 1 //0x0349 633 ------------------------------------------------------*/ 634 union st_invc1 { /* union invc1 */ 635 struct { /* Bit Access */ 636 unsigned char INV10:1;/* Timer Ai start trigger signal select bit */ 637 unsigned char INV11:1;/* Timer A1-1,A2-1,A4-1 control bit */ 638 unsigned char INV12:1;/* Short circuit timer count source select bit*/ 639 unsigned char :1;/* Nothing Assigned */ 640 unsigned char :1;/* Reserved bit (always 0) */ 641 unsigned char :1;/* Nothing Assigned */ 642 unsigned char :1;/* Nothing Assigned */ 643 unsigned char :1;/* Nothing Assigned */ 644 } BIT; /* */ 645 unsigned char BYTE; /* Byte Access */ 646 }; /* */ 647 648 /*------------------------------------------------------ 649 Three-phase output buffer register 0 //0x034a 650 ------------------------------------------------------*/ 651 union st_idb0 { /* union idb0 */ 652 struct { /* Bit Access */ 653 unsigned char DU0 :1;/* U phase output buffer 0 */ 654 unsigned char DUB0:1;/* U~ phase output buffer 0 */ 655 unsigned char DV0 :1;/* V phase output buffer 0 */ 656 unsigned char DVB0:1;/* V~ phase output buffer 0 */ 657 unsigned char DW0 :1;/* W phase output buffer 0 */ 658 unsigned char DWB0:1;/* W~ phase output buffer 0 */ 659 unsigned char :1;/* Nothing Assigned */ 660 unsigned char :1;/* Nothing Assigned */ 661 } BIT; /* */ 662 unsigned char BYTE; /* Byte Access */ 663 }; /* */ 664 665 /*------------------------------------------------------ 666 Three-phase output buffer register 1 //0x034b 667 ------------------------------------------------------*/ 668 union st_idb1 { /* union idb1 */ 669 struct { /* Bit Access */ 670 unsigned char DU1 :1;/* U phase output buffer 1 */ 671 unsigned char DUB1:1;/* U~ phase output buffer 1 */ 672 unsigned char DV1 :1;/* V phase output buffer 1 */ 673 unsigned char DVB1:1;/* V~ phase output buffer 1 */ 674 unsigned char DW1 :1;/* W phase output buffer 1 */ 675 unsigned char DWB1:1;/* W~ phase output buffer 1 */ 676 unsigned char :1;/* Nothing Assigned */ 677 unsigned char :1;/* Nothing Assigned */ 678 } BIT; /* */ 679 unsigned char BYTE; /* Byte Access */ 680 }; /* */ 681 682 /*---------------------------------------------------------------------------------- 683 Timer mode registers //0x035b,0x035c,0x035d,0x0396, 684 0x0397,0x0398,0x0399,0x039a,0x039b,0x039c 685 ---------------------------------------------------------------------------------*/ 686 union st_tmr { /* union tmr */ 687 struct { /* Bit Access */ 688 unsigned char TMOD0:1; /* Operation mode select bit */ 689 unsigned char TMOD1:1; /* Operation mode select bit */ 690 unsigned char MR0 :1; /* Pulse output function select bit */ 691 unsigned char MR1 :1; /* External trigger select bit */ 692 unsigned char MR2 :1; /* Trigger select bit */ 693 unsigned char MR3 :1; /* Must always be "0" in one-shot timer*/ 694 unsigned char TCK0 :1; /* Count source select bit */ 695 unsigned char TCK1 :1; /* Count source select bit */ 696 } BIT; /* */ 697 unsigned char BYTE; /* Byte Access */ 698 }; 699 700 /*------------------------------------------------------ 701 Interrupt request cause select register 2 //0x035e 702 ------------------------------------------------------*/ 703 union st_ifsr2a { /* union ifsr2a */ 704 struct { /* Bit Access */ 705 unsigned char :1; /* Nothing assigned */ 706 unsigned char :1; /* Nothing assigned */ 707 unsigned char :1; /* Nothing assigned */ 708 unsigned char :1; /* Nothing assigned */ 709 unsigned char :1; /* Nothing assigned */ 710 unsigned char :1; /* Nothing assigned */ 711 unsigned char IFSR26 :1; /* Interrupt request cause select bit */ 712 unsigned char IFSR27 :1; /* Interrupt request cause select bit */ 713 } BIT; /* */ 714 unsigned char BYTE; /* Byte Access */ 715 }; 716 717 /*------------------------------------------------------ 718 Interrupt request cause select register //0x035f 719 -----------------------------------------------------*/ 720 union st_ifsr { /* union IFSR */ 721 struct { /* Bit Access */ 722 unsigned char IFSR0:1; /* INT0~ interrupt polarity switching bit */ 723 unsigned char IFSR1:1; /* INT1~ interrupt polarity switching bit */ 724 unsigned char IFSR2:1; /* INT2~ interrupt polarity switching bit */ 725 unsigned char IFSR3:1; /* INT3~ interrupt polarity switching bit */ 726 unsigned char IFSR4:1; /* INT4~ interrupt polarity switching bit */ 727 unsigned char IFSR5:1; /* INT5~ interrupt polarity switching bit */ 728 unsigned char IFSR6:1; /* Interrupt request cause select bit */ 729 unsigned char IFSR7:1; /* Interrupt request cause select bit */ 730 } BIT; /* */ 731 unsigned char BYTE; /* Byte Access */ 732 }; /* */ 733 734 /*------------------------------------------------------ 735 SI/O4 control registers //0x0360 736 ------------------------------------------------------*/ 737 union st_s4c { /* union S4C */ 738 struct { /* Bit Access */ 739 unsigned char SM40:1; /* Internal synchronous clock select bit */ 740 unsigned char SM41:1; /* Internal synchronous clock select bit */ 741 unsigned char SM42:1; /* Sout4 output disable bit */ 742 unsigned char SM43:1; /* SI/O4 port select bit */ 743 unsigned char SM44:1; /* CLK polarity select bit */ 744 unsigned char SM45:1; /* Transfer direction select bit */ 745 unsigned char SM46:1; /* Synchronous clock select bit */ 746 unsigned char SM47:1; /* Sout4 initial value set bit */ 747 } BIT; /* */ 748 unsigned char BYTE; /* Byte Access */ 749 }; 750 751 /*------------------------------------------------------ 752 SI/O3 control registers //0x0362 753 ------------------------------------------------------*/ 754 union st_s3c { /* union S3C */ 755 struct { /* Bit Access */ 756 unsigned char SM30:1; /* Internal synchronous clock select bit */ 757 unsigned char SM31:1; /* Internal synchronous clock select bit */ 758 unsigned char SM32:1; /* Sout3 output disable bit */ 759 unsigned char SM33:1; /* SI/O3 port select bit */ 760 unsigned char SM34:1; /* CLK polarity select bit */ 761 unsigned char SM35:1; /* Transfer direction select bit */ 762 unsigned char SM36:1; /* Synchronous clock select bit */ 763 unsigned char SM37:1; /* Sout3 initial value set bit */ 764 } BIT; /* */ 765 unsigned char BYTE; /* Byte Access */ 766 }; /* */ 767 768 /*------------------------------------------------------ 769 UART0 special mode register 4 //0x036c 770 ------------------------------------------------------*/ 771 union st_u0smr4 { /* union u0smr4 */ 772 struct { /* Bit Access */ 773 unsigned char STAREQ :1; /* Start condition generate bit */ 774 unsigned char RSTAREQ:1; /* Restart condition generate bit */ 775 unsigned char STPREQ :1; /* Stop condition generate bit */ 776 unsigned char STSPSEL:1; /* SCL,SDA output select bit */ 777 unsigned char ACKD :1; /* ACK data bit */ 778 unsigned char ACKC :1; /* ACK data output enable bit */ 779 unsigned char SCLHI :1; /* SCL output stop enable bit */ 780 unsigned char SWC9 :1; /* Final bit L hold enable bit */ 781 } BIT; /* */ 782 unsigned char BYTE; /* Byte Access */ 783 }; /* */ 784 785 /*------------------------------------------------------ 786 UART0 special mode register 3 //0x036d 787 ------------------------------------------------------*/ 788 union st_u0smr3 { /* union u0smr3 */ 789 struct { /* Bit Access */ 790 unsigned char :1; /* Nothing is assigned */ 791 unsigned char CKPH :1; /* Clock phase set bit */ 792 unsigned char :1; /* Nothing is assigned */ 793 unsigned char NODC :1; /* Clock output set bit */ 794 unsigned char :1; /* Nothing is assigned */ 795 unsigned char DL0 :1; /* SDA0(TxD0) digital delay setup bit */ 796 unsigned char DL1 :1; /* SDA0(TxD0) digital delay setup bit */ 797 unsigned char DL2 :1; /* SDA0(TxD0) digital delay setup bit */ 798 } BIT; /* */ 799 unsigned char BYTE; /* Byte Access */ 800 }; /* */ 801 802 /*------------------------------------------------------ 803 UART0 special mode register 2 //0x036e 804 ------------------------------------------------------*/ 805 union st_u0smr2 { /* union u0smr2 */ 806 struct { /* Bit Access */ 807 unsigned char IICM2 :1; /* IIC mode selection bit 2 */ 808 unsigned char CSC :1; /* Clock-synchronous bit */ 809 unsigned char SWC :1; /* SCL wait output bit */ 810 unsigned char ALS :1; /* SDA output stop bit */ 811 unsigned char STAC :1; /* UART0 initialization bit */ 812 unsigned char SWC2 :1; /* SCL wait output bit 2 */ 813 unsigned char SDHI :1; /* SDA output disable bit */ 814 unsigned char :1; /* Nothing is assigned */ 815 } BIT; /* */ 816 unsigned char BYTE; /* Byte Access */ 817 }; /* */ 818 819 /*------------------------------------------------------ 820 UART0 special mode register //0x036f 821 ------------------------------------------------------*/ 822 union st_u0smr { /* union u0smr */ 823 struct { /* Bit Access */ 824 unsigned char IICM:1; /* IIC mode selection bit */ 825 unsigned char ABC :1; /* Arbitration lost detecting flag control bit */ 826 unsigned char BBS :1; /* Bus busy flag */ 827 unsigned char :1; /* Reserved bit,set to 0 */ 828 unsigned char ABSC:1; /* Bus collision detect sampling clock select bit */ 829 unsigned char ACSE:1; /* Auto clear function select bit of transmit enable bit */ 830 unsigned char SSS :1; /* Transmit start condition select bit */ 831 unsigned char :1; /* Nothing is assigned */ 832 } BIT; /* */ 833 unsigned char BYTE; /* Byte Access */ 834 }; /* */ 835 836 /*------------------------------------------------------ 837 UART1 special mode register 4 //0x0370 838 ------------------------------------------------------*/ 839 union st_u1smr4 { /* union u1smr4 */ 840 struct { /* Bit Access */ 841 unsigned char STAREQ:1; /* Start condition generate bit */ 842 unsigned char RSTARE:1; /* Restart condition generate bit */ 843 unsigned char STPREQ:1; /* Stop condition generate bit */ 844 unsigned char STSPSE:1; /* SCL,SDA output select bit */ 845 unsigned char ACKD :1; /* ACK data bit */ 846 unsigned char ACKC :1; /* ACK data output enable bit */ 847 unsigned char SCLHI :1; /* SCL output stop enable bit */ 848 unsigned char SWC9 :1; /* Final bit L hold enable bit */ 849 } BIT; /* */ 850 unsigned char BYTE; /* Byte Access */ 851 }; /* */ 852 853 /*------------------------------------------------------ 854 UART1 special mode register 3 //0x0371 855 ------------------------------------------------------*/ 856 union st_u1smr3 { /* union u1smr3 */ 857 struct { /* Bit Access */ 858 unsigned char :1; /* Nothing is assigned */ 859 unsigned char CKPH :1; /* Clock phase set bit */ 860 unsigned char :1; /* Nothing is assigned */ 861 unsigned char NODC :1; /* Clock output set bit */ 862 unsigned char :1; /* Nothing is assigned */ 863 unsigned char DL0 :1; /* SDA1(TxD1) digital delay setup bit */ 864 unsigned char DL1 :1; /* SDA1(TxD1) digital delay setup bit */ 865 unsigned char DL2 :1; /* SDA1(TxD1) digital delay setup bit */ 866 } BIT; /* */ 867 unsigned char BYTE; /* Byte Access */ 868 }; /* */ 869 870 /*------------------------------------------------------ 871 UART1 special mode register 2 //0x0372 872 ------------------------------------------------------*/ 873 union st_u1smr2 { /* union u1smr2 */ 874 struct { /* Bit Access */ 875 unsigned char IICM2 :1; /* IIC mode selection bit 2 */ 876 unsigned char CSC :1; /* Clock-synchronous bit */ 877 unsigned char SWC :1; /* SCL wait output bit */ 878 unsigned char ALS :1; /* SDA output stop bit */ 879 unsigned char STAC :1; /* UART0 initialization bit */ 880 unsigned char SWC2 :1; /* SCL wait output bit 2 */ 881 unsigned char SDHI :1; /* SDA output disable bit */ 882 unsigned char :1; /* Nothing is assigned */ 883 } BIT; /* */ 884 unsigned char BYTE; /* Byte Access */ 885 }; /* */ 886 887 /*------------------------------------------------------ 888 UART1 special mode register //0x0373 889 ------------------------------------------------------*/ 890 union st_u1smr { /* union u1smr */ 891 struct { /* Bit Access */ 892 unsigned char IICM:1; /* IIC mode selection bit */ 893 unsigned char ABC :1; /* Arbitration lost detecting flag control bit */ 894 unsigned char BBS :1; /* Bus busy flag */ 895 unsigned char :1; /* Reserved bit,set to 0 */ 896 unsigned char ABSC:1; /* Bus collision detect sampling clock select bit */ 897 unsigned char ACSE:1; /* Auto clear function select bit of transmit enable bit */ 898 unsigned char SSS :1; /* Transmit start condition select bit */ 899 unsigned char :1; /* Nothing is assigned */ 900 } BIT; /* */ 901 unsigned char BYTE; /* Byte Access */ 902 }; /* */ 903 904 /*------------------------------------------------------ 905 UART2 special mode register 4 //0x0374 906 ------------------------------------------------------*/ 907 union st_u2smr4 { /* union u1smr4 */ 908 struct { /* Bit Access */ 909 unsigned char STAREQ:1; /* Start condition generate bit */ 910 unsigned char RSTARE:1; /* Restart condition generate bit */ 911 unsigned char STPREQ:1; /* Stop condition generate bit */ 912 unsigned char STSPSE:1; /* SCL,SDA output select bit */ 913 unsigned char ACKD :1; /* ACK data bit */ 914 unsigned char ACKC :1; /* ACK data output enable bit */ 915 unsigned char SCLHI :1; /* SCL output stop enable bit */ 916 unsigned char SWC9 :1; /* Final bit L hold enable bit */ 917 } BIT; /* */ 918 unsigned char BYTE; /* Byte Access */ 919 }; /* */ 920 921 /*------------------------------------------------------ 922 UART2 special mode register 3 //0x0375 923 ------------------------------------------------------*/ 924 union st_u2smr3 { /* union U2SMR3 */ 925 struct { /* Bit Access */ 926 unsigned char :1; /* Nothing is assigned */ 927 unsigned char CKPH :1; /* Clock phase set bit */ 928 unsigned char :1; /* Nothing is assigned */ 929 unsigned char NODC :1; /* Clock output set bit */ 930 unsigned char :1; /* Nothing is assigned */ 931 unsigned char DL0 :1; /* SDA digital delay setup bit */ 932 unsigned char DL1 :1; /* SDA digital delay setup bit */ 933 unsigned char DL2 :1; /* SDA digital delay setup bit */ 934 } BIT; /* */ 935 unsigned char BYTE; /* Byte Access */ 936 }; /* */ 937 938 /*------------------------------------------------------ 939 UART2 special mode register 2 //0x0376 940 ------------------------------------------------------*/ 941 union st_u2smr2 { /* union U2SMR2 */ 942 struct { /* Bit Access */ 943 unsigned char IICM2:1; /* IIC mode selection bit 2 */ 944 unsigned char CSC :1; /* Clock-synchronous bit */ 945 unsigned char SWC :1; /* SCL wait output bit */ 946 unsigned char ALS :1; /* SDA output stop bit */ 947 unsigned char STAC :1; /* UART2 initialization bit */ 948 unsigned char SWC2 :1; /* SCL wait output bit 2 */ 949 unsigned char SDHI :1; /* SDA output disable bit */ 950 unsigned char :1; /* Nothing is assigned */ 951 } BIT; /* */ 952 unsigned char BYTE; /* Byte Access */ 953 }; /* */ 954 955 /*------------------------------------------------------ 956 UART2 special mode register //0x0377 957 ------------------------------------------------------*/ 958 union st_u2smr { /* union U2SMR */ 959 struct { /* Bit Access */ 960 unsigned char IICM :1; /* IIC mode selection bit */ 961 unsigned char ABC :1; /* Arbitration lost detecting flag control bit */ 962 unsigned char BBS :1; /* Reserved bit,set to 0 */ 963 unsigned char :1; /* SCLL sync output enable bit */ 964 unsigned char ABSCS:1; /* Bus collision detect sampling clock select bit */ 965 unsigned char ACSE :1; /* Auto clear function select bit of transmit enable bit */ 966 unsigned char SSS :1; /* Transmit start condition select bit */ 967 unsigned char :1; /* Nothing is assigned */ 968 } BIT; /* */ 969 unsigned char BYTE; /* Byte Access */ 970 }; /* */ 971 972 /*------------------------------------------------------ 973 UART2 transmit/receive mode register //0x0378 974 ------------------------------------------------------*/ 975 union st_u2mr { /* union U2MR */ 976 struct { /* Bit Access */ 977 unsigned char SMD0_U2MR :1; /* Serial I/O mode select bit */ 978 unsigned char SMD1_U2MR :1; /* Serial I/O mode select bit */ 979 unsigned char SMD2_U2MR :1; /* Serial I/O mode select bit */ 980 unsigned char CKDIR_U2MR:1; /* Internal/external clock select bit */ 981 unsigned char STPS_U2MR :1; /* Stop bit length select bit */ 982 unsigned char PRY_U2MR :1; /* Odd/even parity select bit */ 983 unsigned char PRYE_U2MR :1; /* Parity enable bit */ 984 unsigned char IOPOL_U2MR:1; /* TxD RxD I/O polarity reverse bit */ 985 } BIT; /* */ 986 unsigned char BYTE; /* Byte Access */ 987 }; 988 989 /*------------------------------------------------------ 990 UART2 Transmit buffer register 16 bit //0x037a 991 ------------------------------------------------------*/ 992 union st_u2tb { /* UART2 Transmit buffer register 16 bit ; Use "MOV" instruction when writing to this register. */ 993 struct{ 994 unsigned char U2TBL; /* UART2 Transmit buffer register low 8 bit */ 995 unsigned char U2TBH; /* UART2 Transmit buffer register high 8 bit */ 996 } BYTE; /* Byte access */ 997 unsigned short WORD; /* Word Access */ 998 }; 999 1000 /*------------------------------------------------------ 1001 UART2 transmit/receive control register 0//0x037c 1002 ------------------------------------------------------*/ 1003 union st_u2c0 { /* union U2C0 */ 1004 struct { /* Bit Access */ 1005 unsigned char CLK0 :1; /* BRG count source select bit */ 1006 unsigned char CLK1 :1; /* BRG count source select bit */ 1007 unsigned char CRS :1; /* CTS~/RTS~ function select bit */ 1008 unsigned char TXEPT:1; /* Transmit register empty flag */ 1009 unsigned char CRD :1; /* CTS~/RTS~ disable bit */ 1010 unsigned char :1; /* Nothing Assigned */ 1011 unsigned char CKPOL:1; /* CLK polarity select bit */ 1012 unsigned char UFORM:1; /* Transfer format select bit */ 1013 } BIT; /* */ 1014 unsigned char BYTE; /* Byte Access */ 1015 }; /* UART2 transmit/receive control register 0*/ 1016 1017 /*------------------------------------------------------ 1018 UART2 transmit/receive control register 1 //0x037d 1019 -----------------------------------------------------*/ 1020 union st_u2c1 { /* union U2C1 */ 1021 struct { /* Bit Access */ 1022 unsigned char TE_U2C1:1; /* Transmit enable bit */ 1023 unsigned char TI_U2C1:1; /* Transmit buffer empty flag */ 1024 unsigned char RE_U2C1:1; /* Receive enable bit */ 1025 unsigned char RI_U2C1:1; /* Receive complete flag */ 1026 unsigned char U2IRS :1; /* UART2 transmit interrupt cause select bit*/ 1027 unsigned char U2RRM :1; /* UART2 continuous receive mode enable bit */ 1028 unsigned char U2LCH :1; /* Data logic select bit */ 1029 unsigned char U2ERE :1; /* Error signal output enable bit */ 1030 } BIT; /* */ 1031 unsigned char BYTE; /* Byte Access */ 1032 }; /*UART2 transmit/receive control register 1 */ 1033 1034 /*------------------------------------------------------ 1035 UART2 receive buffer registers //0x037e 1036 ------------------------------------------------------*/ 1037 union st_u2rb { /* UART2 receive buffer register */ 1038 struct { /* Bit Access */ 1039 unsigned char :1; /* Receive data */ 1040 unsigned char :1; /* Receive data */ 1041 unsigned char :1; /* Receive data */ 1042 unsigned char :1; /* Receive data */ 1043 unsigned char :1; /* Receive data */ 1044 unsigned char :1; /* Receive data */ 1045 unsigned char :1; /* Receive data */ 1046 unsigned char :1; /* Receive data */ 1047 unsigned char :1; /* Receive data */ 1048 unsigned char :1; /* Nothing assigned */ 1049 unsigned char :1; /* Nothing assigned */ 1050 unsigned char ABT_U2RB:1; /* Arbitration lost detecting flag */ 1051 unsigned char OER_U2RB:1; /* Overrun error flag */ 1052 unsigned char FER_U2RB:1; /* Framing error flag */ 1053 unsigned char PER_U2RB:1; /* Parity error flag */ 1054 unsigned char SUM_U2RB:1; /* Error sum flag */ 1055 }BIT; 1056 struct{ 1057 unsigned char U2RBL; /* Low 8 bit */ 1058 unsigned char U2RBH; /* High 8 bit */ 1059 }BYTE; 1060 unsigned short WORD; 1061 }; 1062 1063 /*------------------------------------------------------ 1064 Count start flag //0x0380 1065 ------------------------------------------------------*/ 1066 union st_tabsr { /* union TABSR */ 1067 struct { /* Bit Access */ 1068 unsigned char TA0S:1; /* Timer A0 count start flag */ 1069 unsigned char TA1S:1; /* Timer A1 count start flag */ 1070 unsigned char TA2S:1; /* Timer A2 count start flag */ 1071 unsigned char TA3S:1; /* Timer A3 count start flag */ 1072 unsigned char TA4S:1; /* Timer A4 count start flag */ 1073 unsigned char TB0S:1; /* Timer B0 count start flag */ 1074 unsigned char TB1S:1; /* Timer B1 count start flag */ 1075 unsigned char TB2S:1; /* Timer B2 count start flag */ 1076 } BIT; /* */ 1077 unsigned char BYTE; /* Byte Access */ 1078 }; /*UART2 transmit/receive control register 1 */ 1079 1080 /*------------------------------------------------------ 1081 Clock prescaler reset flag //0x0381 1082 ------------------------------------------------------*/ 1083 union st_cpsrf { /* union CPSRF */ 1084 struct { /* Bit Access */ 1085 unsigned char :1; /* */ 1086 unsigned char :1; /* */ 1087 unsigned char :1; /* */ 1088 unsigned char :1; /* */ 1089 unsigned char :1; /* */ 1090 unsigned char :1; /* */ 1091 unsigned char :1; /* */ 1092 unsigned char CPSR:1; /* Clock prescaler reset flag */ 1093 } BIT; /* */ 1094 unsigned char BYTE; /* Byte Access */ 1095 }; /* Watchdog timer start register */ 1096 1097 /*------------------------------------------------------ 1098 One-shot start flag //0x0382 1099 ------------------------------------------------------*/ 1100 union st_onsf { /* union ONSF */ 1101 struct { /* Bit Access */ 1102 unsigned char TA0OS:1; /* Timer A0 one-shot start flag */ 1103 unsigned char TA1OS:1; /* Timer A1 one-shot start flag */ 1104 unsigned char TA2OS:1; /* Timer A2 one-shot start flag */ 1105 unsigned char TA3OS:1; /* Timer A3 one-shot start flag */ 1106 unsigned char TA4OS:1; /* Timer A4 one-shot start flag */ 1107 unsigned char TAZIE:1; /* Z phase input enable bit */ 1108 unsigned char TA0TGL:1; /* Timer A0 event/trigger select bit */ 1109 unsigned char TA0TGH:1; /* Timer A0 event/trigger select bit */ 1110 } BIT; /* */ 1111 unsigned char BYTE; /* Byte Access */ 1112 }; /*UART2 transmit/receive control register 1 */ 1113 1114 /*------------------------------------------------------ 1115 Trigger select register //0x0383 1116 ------------------------------------------------------*/ 1117 union st_trgsr { /* union TRGSR */ 1118 struct { /* Bit Access */ 1119 unsigned char TA1TGL:1; /* Timer A1 event/trigger select bit */ 1120 unsigned char TA1TGH:1; /* Timer A1 event/trigger select bit */ 1121 unsigned char TA2TGL:1; /* Timer A2 event/trigger select bit */ 1122 unsigned char TA2TGH:1; /* Timer A2 event/trigger select bit */ 1123 unsigned char TA3TGL:1; /* Timer A3 event/trigger select bit */ 1124 unsigned char TA3TGH:1; /* Timer A3 event/trigger select bit */ 1125 unsigned char TA4TGL:1; /* Timer A4 event/trigger select bit */ 1126 unsigned char TA4TGH:1; /* Timer A4 event/trigger select bit */ 1127 } BIT; /* */ 1128 unsigned char BYTE; /* Byte Access */ 1129 }; /*UART2 transmit/receive control register 1 */ 1130 1131 /*------------------------------------------------------ 1132 Timer B2 special mode register //0x039e 1133 ------------------------------------------------------*/ 1134 union st_tb2sc { /* union tb2sc */ 1135 struct { /* Bit Access */ 1136 unsigned char PWCON :1; /* Timer B2 reload timing switching bit */ 1137 unsigned char IVPCR1:1; /* Three phase output port NMI control bit 1 */ 1138 unsigned char :1; /* Nothing is assigned */ 1139 unsigned char :1; /* Nothing is assigned */ 1140 unsigned char :1; /* Nothing is assigned */ 1141 unsigned char :1; /* Nothing is assigned */ 1142 unsigned char :1; /* Nothing is assigned */ 1143 unsigned char :1; /* Nothing is assigned */ 1144 } BIT; /* */ 1145 unsigned char BYTE; /* Byte Access */ 1146 }; /*UART2 transmit/receive control register 1 */ 1147 1148 /*------------------------------------------------------ 1149 UART0 transmit/receive mode register //0x03a0 1150 ------------------------------------------------------*/ 1151 union st_u0mr { /* union U0MR */ 1152 struct { /* Bit Access */ 1153 unsigned char SMD0_U0MR :1; /* Serial I/O mode select bit */ 1154 unsigned char SMD1_U0MR :1; /* Serial I/O mode select bit */ 1155 unsigned char SMD2_U0MR :1; /* Serial I/O mode select bit */ 1156 unsigned char CKDIR_U0MR:1; /* Internal/external clock select bit */ 1157 unsigned char STPS_U0MR :1; /* Stop bit length select bit */ 1158 unsigned char PRY_U0MR :1; /* Odd/even parity select bit */ 1159 unsigned char PRYE_U0MR :1; /* Parity enable bit */ 1160 unsigned char IOPOL_U0MR :1; /* TxD,RxD I/O polarity reverse bit */ 1161 } BIT; /* */ 1162 unsigned char BYTE; /* Byte Access */ 1163 }; 1164 1165 /*------------------------------------------------------ 1166 UART0 transmit/receive mode register //0x03a2 1167 ------------------------------------------------------*/ 1168 union st_u0tb { /* UART0 Transmit buffer register 16 bit ; Use "MOV" instruction when writing to this register. */ 1169 struct{ 1170 unsigned char U0TBL; /* UART0 Transmit buffer register low 8 bit */ 1171 unsigned char U0TBH; /* UART0 Transmit buffer register high 8 bit */ 1172 } BYTE; /* Byte access */ 1173 unsigned short WORD; /* Word Access */ 1174 }; 1175 1176 /*------------------------------------------------------ 1177 UARTi transmit/receive control register 0 //0x03a4 1178 ------------------------------------------------------*/ 1179 union st_u0c0 { /* union U0C0 */ 1180 struct { /* Bit Access */ 1181 unsigned char CLK0 :1; /* BRG count source select bit */ 1182 unsigned char CLK1 :1; /* BRG count source select bit */ 1183 unsigned char CRS :1; /* CTS~/RTS~ function select bit */ 1184 unsigned char TXEPT:1; /* Transmit register empty flag */ 1185 unsigned char CRD :1; /* CTS~/RTS~ disable bit */ 1186 unsigned char NCH :1; /* Data output select bit */ 1187 unsigned char CKPOL:1; /* CLK polarity select bit */ 1188 unsigned char UFORM:1; /* Transfer format select bit */ 1189 } BIT; /* */ 1190 unsigned char BYTE; /* Byte Access */ 1191 }; /*UARTi transmit/receive control register 0 */ 1192 1193 /*------------------------------------------------------ 1194 UART0 transmit/receive control register 1 //0x03a5 1195 ------------------------------------------------------*/ 1196 union st_u0c1 { /* union U0C1 */ 1197 struct { /* Bit Access */ 1198 unsigned char TE :1; /* Transmit enable bit */ 1199 unsigned char TI :1; /* Transmit buffer empty flag */ 1200 unsigned char RE :1; /* Receive enable bit */ 1201 unsigned char RI :1; /* Receive complete flag */ 1202 unsigned char :1; /* Nothing Assigned */ 1203 unsigned char :1; /* Nothing Assigned */ 1204 unsigned char U0LCH :1; /* Data logic select bit */ 1205 unsigned char U0ERE :1; /* Error signal output enable bit */ 1206 } BIT; /* */ 1207 unsigned char BYTE; /* Byte Access */ 1208 }; /*UART0 transmit/receive control register 1 */ 1209 1210 /*------------------------------------------------------ 1211 UART0 receive buffer register //0x03a6 1212 ------------------------------------------------------*/ 1213 union st_u0rb { /* UART0 receive buffer register */ 1214 struct { /* Bit Access */ 1215 unsigned char :1; /* Receive data */ 1216 unsigned char :1; /* Receive data */ 1217 unsigned char :1; /* Receive data */ 1218 unsigned char :1; /* Receive data */ 1219 unsigned char :1; /* Receive data */ 1220 unsigned char :1; /* Receive data */ 1221 unsigned char :1; /* Receive data */ 1222 unsigned char :1; /* Receive data */ 1223 unsigned char :1; /* Receive data */ 1224 unsigned char :1; /* Nothing assigned */ 1225 unsigned char :1; /* Nothing assigned */ 1226 unsigned char ABT_U0RB:1; /* Arbitration lost detecting flag */ 1227 unsigned char OER_U0RB:1; /* Overrun error flag */ 1228 unsigned char FER_U0RB:1; /* Framing error flag */ 1229 unsigned char PER_U0RB:1; /* Parity error flag */ 1230 unsigned char SUM_U0RB:1; /* Error sum flag */ 1231 }BIT; 1232 struct{ 1233 unsigned char U0RBL; /* Low 8 bit */ 1234 unsigned char U0RBH; /* High 8 bit */ 1235 }BYTE; 1236 unsigned short WORD; 1237 }; 1238 1239 /*------------------------------------------------------ 1240 UART1 transmit/receive mode register //0x03a8 1241 ------------------------------------------------------*/ 1242 union st_u1mr { /* union U1MR */ 1243 struct { /* Bit Access */ 1244 unsigned char SMD0_U1MR :1; /* Serial I/O mode select bit */ 1245 unsigned char SMD1_U1MR :1; /* Serial I/O mode select bit */ 1246 unsigned char SMD2_U1MR :1; /* Serial I/O mode select bit */ 1247 unsigned char CKDIR_U1MR :1; /* Internal/external clock select bit */ 1248 unsigned char STPS_U1MR :1; /* Stop bit length select bit */ 1249 unsigned char PRY_U1MR :1; /* Odd/even parity select bit */ 1250 unsigned char PRYE_U1MR :1; /* Parity enable bit */ 1251 unsigned char IOPOL_U1MR :1; /* TxD,RxD I/O polarity reverse bit */ 1252 } BIT; /* */ 1253 unsigned char BYTE; /* Byte Access */ 1254 }; 1255 1256 /*------------------------------------------------------ 1257 UART1 transmit buffer register //0x03aa 1258 ------------------------------------------------------*/ 1259 union st_u1tb { /* UART1 Transmit buffer register 16 bit ; Use "MOV" instruction when writing to this register. */ 1260 struct{ 1261 unsigned char U1TBL; /* UART1 Transmit buffer register low 8 bit */ 1262 unsigned char U1TBH; /* UART1 Transmit buffer register high 8 bit */ 1263 } BYTE; /* Byte access */ 1264 unsigned short WORD; /* Word Access */ 1265 }; 1266 1267 /*------------------------------------------------------ 1268 UART1 transmit/receive control register 0 //0x03ac 1269 ------------------------------------------------------*/ 1270 union st_u1c0 { /* union UCR */ 1271 struct { /* Bit Access */ 1272 unsigned char CLK0 :1; /* BRG count source select bit */ 1273 unsigned char CLK1 :1; /* BRG count source select bit */ 1274 unsigned char CRS :1; /* CTS~/RTS~ function select bit */ 1275 unsigned char TXEPT:1; /* Transmit register empty flag */ 1276 unsigned char CRD :1; /* CTS~/RTS~ disable bit */ 1277 unsigned char NCH :1; /* Data output select bit */ 1278 unsigned char CKPOL:1; /* CLK polarity select bit */ 1279 unsigned char UFORM:1; /* Transfer format select bit */ 1280 } BIT; /* */ 1281 unsigned char BYTE; /* Byte Access */ 1282 }; /*UARTi transmit/receive control register 0 */ 1283 1284 /*------------------------------------------------------ 1285 UART1 transmit/receive control register 1 //0x03ad 1286 ------------------------------------------------------*/ 1287 union st_u1c1 { /* union U1C1 */ 1288 struct { /* Bit Access */ 1289 unsigned char TE:1; /* Transmit enable bit */ 1290 unsigned char TI:1; /* Transmit buffer empty flag */ 1291 unsigned char RE:1; /* Receive enable bit */ 1292 unsigned char RI:1; /* Receive complete flag */ 1293 unsigned char :1; /* */ 1294 unsigned char :1; /* */ 1295 unsigned char :1; /* */ 1296 unsigned char :1; /* */ 1297 } BIT; /* */ 1298 unsigned char BYTE; /* Byte Access */ 1299 }; /*UART1 transmit/receive control register 1 */ 1300 1301 /*------------------------------------------------------ 1302 UART1 receive buffer register //0x03ae 1303 ------------------------------------------------------*/ 1304 union st_u1rb { /* UART1 receive buffer register */ 1305 struct { /* Bit Access */ 1306 unsigned char :1; /* Receive data */ 1307 unsigned char :1; /* Receive data */ 1308 unsigned char :1; /* Receive data */ 1309 unsigned char :1; /* Receive data */ 1310 unsigned char :1; /* Receive data */ 1311 unsigned char :1; /* Receive data */ 1312 unsigned char :1; /* Receive data */ 1313 unsigned char :1; /* Receive data */ 1314 unsigned char :1; /* Receive data */ 1315 unsigned char :1; /* Nothing assigned */ 1316 unsigned char :1; /* Nothing assigned */ 1317 unsigned char ABT_U1RB:1; /* Arbitration lost detecting flag */ 1318 unsigned char OER_U1RB:1; /* Overrun error flag */ 1319 unsigned char FER_U1RB:1; /* Framing error flag */ 1320 unsigned char PER_U1RB:1; /* Parity error flag */ 1321 unsigned char SUM_U1RB:1; /* Error sum flag */ 1322 }BIT; 1323 struct{ 1324 unsigned char U1RBL; /* Low 8 bit */ 1325 unsigned char U1RBH; /* High 8 bit */ 1326 }BYTE; 1327 unsigned short WORD; 1328 }; 1329 1330 /*------------------------------------------------------ 1331 UART transmit/receive control register 2 //0x03b0 1332 ------------------------------------------------------*/ 1333 union st_ucon { /* union UCON */ 1334 struct { /* Bit Access */ 1335 unsigned char U0IRS :1; /* UART0 transmit interrupt cause select bit*/ 1336 unsigned char U1IRS :1; /* UART1 transmit interrupt cause select bit*/ 1337 unsigned char U0RRM :1; /* UART0 continuous receive mode enable bit */ 1338 unsigned char U1RRM :1; /* UART1 continuous receive mode enable bit */ 1339 unsigned char CLKMD0:1; /* CLK/CLKS select bit 0 */ 1340 unsigned char CLKMD1:1; /* CLK/CLKS select bit 1 */ 1341 unsigned char RCSP :1; /* Separate CTS~/RTS~ bit */ 1342 unsigned char :1; /* */ 1343 } BIT; /* */ 1344 unsigned char BYTE; /* Byte Access */ 1345 }; /*UART transmit/receive control register 2 */ 1346 1347 /*------------------------------------------------------ 1348 DMA0 request cause select register //0x03b8 1349 ------------------------------------------------------*/ 1350 union st_dm0sl { /* DMAi request cause select registers */ 1351 struct{ 1352 unsigned char DSEL0:1;/* DMA request cause select bit */ 1353 unsigned char DSEL1:1;/* DMA request cause select bit */ 1354 unsigned char DSEL2:1;/* DMA request cause select bit */ 1355 unsigned char DSEL3:1;/* DMA request cause select bit */ 1356 unsigned char :1; 1357 unsigned char :1; 1358 unsigned char DMS :1;/* DMA request cause expansion bit */ 1359 unsigned char DSR :1;/* Software DMA request bit */ 1360 }BIT; 1361 unsigned char BYTE; 1362 }; 1363 1364 /*------------------------------------------------------ 1365 DMA1 request cause select register //0x03ba 1366 ------------------------------------------------------*/ 1367 union st_dm1sl { /* DMAi request cause select registers */ 1368 struct{ 1369 unsigned char DSEL0:1; /* DMA request cause select bit */ 1370 unsigned char DSEL1:1; /* DMA request cause select bit */ 1371 unsigned char DSEL2:1; /* DMA request cause select bit */ 1372 unsigned char DSEL3:1; /* DMA request cause select bit */ 1373 unsigned char :1; 1374 unsigned char :1; 1375 unsigned char DMS :1; /* DMA request cause expansion bit */ 1376 unsigned char DSR :1; /* Software DMA request bit */ 1377 }BIT; 1378 unsigned char BYTE; 1379 }; 1380 1381 /*------------------------------------------------------ 1382 CRC data register //0x03bc 1383 ------------------------------------------------------*/ 1384 union st_crcd { /* CRC data register 16 bit */ 1385 struct{ 1386 unsigned char CRCDL; /* CRC data register low 8 bit */ 1387 unsigned char CRCDH; /* CRC data register high 8 bit */ 1388 } BYTE; /* Byte access */ 1389 unsigned short WORD; /* Word Access */ 1390 }; 1391 1392 /*------------------------------------------------------ 1393 A/D register 0 //0x03c0 1394 ------------------------------------------------------*/ 1395 union st_ad0 { /* A/D register 0 16 bit */ 1396 struct{ 1397 unsigned char AD0L; /* A/D register 0 low 8 bit */ 1398 unsigned char AD0H; /* A/D register 0 high 8 bit */ 1399 }BYTE; /* Byte access */ 1400 unsigned short WORD; /* Word Access */ 1401 }; 1402 1403 /*------------------------------------------------------ 1404 A/D register 1 //0x03c2 1405 ------------------------------------------------------*/ 1406 union st_ad1 { /* A/D register 1 16 bit */ 1407 struct{ 1408 unsigned char AD1L; /* A/D register 1 low 8 bit */ 1409 unsigned char AD1H; /* A/D register 1 high 8 bit */ 1410 } BYTE; /* Byte access */ 1411 unsigned short WORD; /* Word Access */ 1412 }; 1413 1414 /*------------------------------------------------------ 1415 A/D register 2 //0x03c4 1416 ------------------------------------------------------*/ 1417 union st_ad2 { /* A/D register 2 16 bit */ 1418 struct{ 1419 unsigned char AD2L; /* A/D register 2 low 8 bit */ 1420 unsigned char AD2H; /* A/D register 2 high 8 bit */ 1421 } BYTE; /* Byte access */ 1422 unsigned short WORD; /* Word Access */ 1423 }; 1424 1425 /*------------------------------------------------------ 1426 A/D register 3 //0x03c6 1427 ------------------------------------------------------*/ 1428 union st_ad3 { /* A/D register 3 16 bit */ 1429 struct{ 1430 unsigned char AD3L; /* A/D register 3 low 8 bit */ 1431 unsigned char AD3H; /* A/D register 3 high 8 bit */ 1432 } BYTE; /* Byte access */ 1433 unsigned short WORD; /* Word Access */ 1434 }; 1435 1436 /*------------------------------------------------------ 1437 A/D register 4 //0x03c8 1438 ------------------------------------------------------*/ 1439 union st_ad4 { /* A/D register 4 16 bit */ 1440 struct{ 1441 unsigned char AD4L; /* A/D register 4 low 8 bit */ 1442 unsigned char AD4H; /* A/D register 4 high 8 bit */ 1443 } BYTE; /* Byte access */ 1444 unsigned short WORD; /* Word Access */ 1445 }; 1446 1447 /*------------------------------------------------------ 1448 A/D register 5 //0x03ca 1449 ------------------------------------------------------*/ 1450 union st_ad5 { /* A/D register 5 16 bit */ 1451 struct{ 1452 unsigned char AD5L; /* A/D register 5 low 8 bit */ 1453 unsigned char AD5H; /* A/D register 5 high 8 bit */ 1454 } BYTE; /* Byte access */ 1455 unsigned short WORD; /* Word Access */ 1456 }; 1457 1458 /*------------------------------------------------------ 1459 A/D register 6 //0x03cc 1460 ------------------------------------------------------*/ 1461 union st_ad6 { /* A/D register 6 16 bit */ 1462 struct{ 1463 unsigned char AD6L; /* A/D register 6 low 8 bit */ 1464 unsigned char AD6H; /* A/D register 6 high 8 bit */ 1465 } BYTE; /* Byte access */ 1466 unsigned short WORD; /* Word Access */ 1467 }; 1468 1469 /*------------------------------------------------------ 1470 A/D register 7 //0x03ce 1471 ------------------------------------------------------*/ 1472 union st_ad7 { /* A/D register 7 16 bit */ 1473 struct{ 1474 unsigned char AD7L; /* A/D register 7 low 8 bit */ 1475 unsigned char AD7H; /* A/D register 7 high 8 bit */ 1476 } BYTE; /* Byte access */ 1477 unsigned short WORD; /* Word Access */ 1478 }; 1479 1480 /*------------------------------------------------------ 1481 A/D control register 2 //0x03d4 1482 ------------------------------------------------------*/ 1483 union st_adcon2 { /* union ADCON2 */ 1484 struct { /* Bit Access */ 1485 unsigned char SMP :1; /* A/D conversion method select bit */ 1486 unsigned char ADGSEL0 :1; /* Reserved bit (Always set to 0 ) */ 1487 unsigned char ADGSEL1 :1; /* Reserved bit (Always set to 0 ) */ 1488 unsigned char :1; /* Reserved bit (Always set to 0 ) */ 1489 unsigned char CKS2 :1; /* Nothing Assigned. */ 1490 unsigned char :1; /* Nothing Assigned. */ 1491 unsigned char :1; /* Nothing Assigned. */ 1492 unsigned char :1; /* Nothing Assigned. */ 1493 } BIT; 1494 unsigned char BYTE; /* Byte Access */ 1495 }; 1496 1497 /*------------------------------------------------------ 1498 A/D control register 0 //0x03d6 1499 ------------------------------------------------------*/ 1500 union st_adcon0 { /* union ADCON0 */ 1501 struct { /* Bit Access */ 1502 unsigned char CH0 :1; /* Analog input pin select bit */ 1503 unsigned char CH1 :1; /* Analog input pin select bit */ 1504 unsigned char CH2 :1; /* Analog input pin select bit */ 1505 unsigned char MD0 :1; /* A/D operation mode select bit 0 */ 1506 unsigned char MD1 :1; /* A/D operation mode select bit 0 */ 1507 unsigned char TRG :1; /* Trigger select bit */ 1508 unsigned char ADST:1; /* A/D conversion start flag */ 1509 unsigned char CKS0:1; /* Frequency select bit 0 */ 1510 } BIT; /* */ 1511 unsigned char BYTE; /* Byte Access */ 1512 }; /*A/D control register 0 */ 1513 1514 1515 /*------------------------------------------------------ 1516 A/D control register 1 //0x03d7 1517 ------------------------------------------------------*/ 1518 union st_adcon1 { /* union ADCON1 */ 1519 struct { /* Bit Access */ 1520 unsigned char SCAN0:1; /* A/D sweep pin select bit */ 1521 unsigned char SCAN1:1; /* A/D sweep pin select bit */ 1522 unsigned char MD2 :1; /* A/D operation mode select bit 1 */ 1523 unsigned char BITS :1; /* 8/10-bit mode select bit */ 1524 unsigned char CKS1 :1; /* Frequency select bit 1 */ 1525 unsigned char VCUT :1; /* Vref connect bit */ 1526 unsigned char OPA0 :1; /* External op-amp connection mode bit */ 1527 unsigned char OPA1 :1; /* External op-amp connection mode bit */ 1528 } BIT; /* */ 1529 unsigned char BYTE; /* Byte Access */ 1530 }; /*A-D control register 1 */ 1531 1532 1533 /*------------------------------------------------------ 1534 D/A control register //0x03dc 1535 ------------------------------------------------------*/ 1536 union st_dacon{ /* union DACON */ 1537 struct { /* Bit Access */ 1538 unsigned char DA0E :1; /* D/A0 output enable bit */ 1539 unsigned char DA1E :1; /* D/A1 output enable bit */ 1540 unsigned char :1; /* Nothing Assigned */ 1541 unsigned char :1; /* Nothing Assigned */ 1542 unsigned char :1; /* Nothing Assigned */ 1543 unsigned char :1; /* Nothing Assigned */ 1544 unsigned char :1; /* Nothing Assigned */ 1545 unsigned char :1; /* Nothing Assigned */ 1546 } BIT; /* */ 1547 unsigned char BYTE; /* Byte Access */ 1548 }; /* D/A control register */ 1549 1550 /*------------------------------------------------------ 1551 Port P14 control register //0x03de 1552 ------------------------------------------------------*/ 1553 union st_pc14{ /* union pc14 */ 1554 struct { /* Bit Access */ 1555 unsigned char P140 :1; /* Port P14_0 register */ 1556 unsigned char P141 :1; /* Port P14_1 register */ 1557 unsigned char :1; /* Nothing Assigned */ 1558 unsigned char :1; /* Nothing Assigned */ 1559 unsigned char pd140:1; /* Port P14_0 direction register */ 1560 unsigned char pd141:1; /* Port P14_1 direction register */ 1561 unsigned char :1; /* Nothing Assigned */ 1562 unsigned char :1; /* Nothing Assigned */ 1563 } BIT; /* */ 1564 unsigned char BYTE; /* Byte Access */ 1565 }; /* Port P14 control register */ 1566 1567 /*------------------------------------------------------ 1568 Pull-up control register 3 //0x03df 1569 ------------------------------------------------------*/ 1570 union st_pur3{ /* union pur3 */ 1571 struct { /* Bit Access */ 1572 unsigned char PU30:1; /* P11_0 to P11_3 pull-up */ 1573 unsigned char PU31:1; /* P11_4 to P11_7 pull-up */ 1574 unsigned char PU32:1; /* P12_0 to P12_3 pull-up */ 1575 unsigned char PU33:1; /* P12_4 to P12_7 pull-up */ 1576 unsigned char PU34:1; /* P13_0 to P13_3 pull-up */ 1577 unsigned char PU35:1; /* P13_4 to P13_7 pull-up */ 1578 unsigned char PU36:1; /* P14_0,P14_1 pull-up */ 1579 unsigned char PU37:1; /* P11 to P14 effective bit */ 1580 } BIT; /* */ 1581 unsigned char BYTE; /* Byte Access */ 1582 }; /* Pull-up control register 3 */ 1583 1584 /*------------------------------------------------------ 1585 Port P0 register //0x03e0 1586 ------------------------------------------------------*/ 1587 union st_p0 { /* union P0 */ 1588 struct { /* Bit Access */ 1589 unsigned char P0_0:1; /* Port P00 register */ 1590 unsigned char P0_1:1; /* Port P01 register */ 1591 unsigned char P0_2:1; /* Port P02 register */ 1592 unsigned char P0_3:1; /* Port P03 register */ 1593 unsigned char P0_4:1; /* Port P04 register */ 1594 unsigned char P0_5:1; /* Port P05 register */ 1595 unsigned char P0_6:1; /* Port P06 register */ 1596 unsigned char P0_7:1; /* Port P07 register */ 1597 } BIT; /* */ 1598 unsigned char BYTE; /* Byte Access */ 1599 }; /* */ 1600 1601 /*------------------------------------------------------ 1602 Port P1 register //0x03e1 1603 ------------------------------------------------------*/ 1604 union st_p1 { /* union P1 */ 1605 struct { /* Bit Access */ 1606 unsigned char P1_0:1;/* Port P10 register */ 1607 unsigned char P1_1:1;/* Port P11 register */ 1608 unsigned char P1_2:1;/* Port P12 register */ 1609 unsigned char P1_3:1;/* Port P13 register */ 1610 unsigned char P1_4:1;/* Port P14 register */ 1611 unsigned char P1_5:1;/* Port P15 register */ 1612 unsigned char P1_6:1;/* Port P16 register */ 1613 unsigned char P1_7:1;/* Port P17 register */ 1614 } BIT; /* */ 1615 unsigned char BYTE; /* Byte Access */ 1616 }; /* */ 1617 1618 /*------------------------------------------------------ 1619 Port P0 direction register //0x03e2 1620 ------------------------------------------------------*/ 1621 union st_pd0 { /* union PD0 */ 1622 struct { /* Bit Access */ 1623 unsigned char PD0_0:1;/* Port P00 direction register */ 1624 unsigned char PD0_1:1;/* Port P01 direction register */ 1625 unsigned char PD0_2:1;/* Port P02 direction register */ 1626 unsigned char PD0_3:1;/* Port P03 direction register */ 1627 unsigned char PD0_4:1;/* Port P04 direction register */ 1628 unsigned char PD0_5:1;/* Port P05 direction register */ 1629 unsigned char PD0_6:1;/* Port P06 direction register */ 1630 unsigned char PD0_7:1;/* Port P07 direction register */ 1631 } BIT; /* */ 1632 unsigned char BYTE; /* Byte Access */ 1633 }; /* */ 1634 1635 1636 /*------------------------------------------------------ 1637 Port P1 direction register //0x03e3 1638 ------------------------------------------------------*/ 1639 union st_pd1 { /* union PD1 */ 1640 struct { /* Bit Access */ 1641 unsigned char PD1_0:1;/* Port P10 direction register */ 1642 unsigned char PD1_1:1;/* Port P11 direction register */ 1643 unsigned char PD1_2:1;/* Port P12 direction register */ 1644 unsigned char PD1_3:1;/* Port P13 direction register */ 1645 unsigned char PD1_4:1;/* Port P14 direction register */ 1646 unsigned char PD1_5:1;/* Port P15 direction register */ 1647 unsigned char PD1_6:1;/* Port P16 direction register */ 1648 unsigned char PD1_7:1;/* Port P17 direction register */ 1649 } BIT; /* */ 1650 unsigned char BYTE; /* Byte Access */ 1651 }; /* */ 1652 1653 /*------------------------------------------------------ 1654 Port P2 register //0x03e4 1655 ------------------------------------------------------*/ 1656 union st_p2 { /* union P2 */ 1657 struct { /* Bit Access */ 1658 unsigned char P2_0:1;/* Port P20 register */ 1659 unsigned char P2_1:1;/* Port P21 register */ 1660 unsigned char P2_2:1;/* Port P22 register */ 1661 unsigned char P2_3:1;/* Port P23 register */ 1662 unsigned char P2_4:1;/* Port P24 register */ 1663 unsigned char P2_5:1;/* Port P25 register */ 1664 unsigned char P2_6:1;/* Port P26 register */ 1665 unsigned char P2_7:1;/* Port P27 register */ 1666 } BIT; /* */ 1667 unsigned char BYTE; /* Byte Access */ 1668 }; /* */ 1669 1670 /*------------------------------------------------------ 1671 Port P3 register //0x03e5 1672 ------------------------------------------------------*/ 1673 union st_p3 { /* union P3 */ 1674 struct { /* Bit Access */ 1675 unsigned char P3_0:1;/* Port P30 register */ 1676 unsigned char P3_1:1;/* Port P31 register */ 1677 unsigned char P3_2:1;/* Port P32 register */ 1678 unsigned char P3_3:1;/* Port P33 register */ 1679 unsigned char P3_4:1;/* Port P34 register */ 1680 unsigned char P3_5:1;/* Port P35 register */ 1681 unsigned char P3_6:1;/* Port P36 register */ 1682 unsigned char P3_7:1;/* Port P37 register */ 1683 } BIT; /* */ 1684 unsigned char BYTE; /* Byte Access */ 1685 }; /* */ 1686 1687 /*------------------------------------------------------ 1688 Port P2 direction register //0x03e6 1689 ------------------------------------------------------*/ 1690 union st_pd2 { /* union PD2 */ 1691 struct { /* Bit Access */ 1692 unsigned char PD2_0:1;/* Port P20 direction register */ 1693 unsigned char PD2_1:1;/* Port P21 direction register */ 1694 unsigned char PD2_2:1;/* Port P22 direction register */ 1695 unsigned char PD2_3:1;/* Port P23 direction register */ 1696 unsigned char PD2_4:1;/* Port P24 direction register */ 1697 unsigned char PD2_5:1;/* Port P25 direction register */ 1698 unsigned char PD2_6:1;/* Port P26 direction register */ 1699 unsigned char PD2_7:1;/* Port P27 direction register */ 1700 } BIT; /* */ 1701 unsigned char BYTE; /* Byte Access */ 1702 }; /* */ 1703 1704 1705 /*------------------------------------------------------ 1706 Port P3 direction register //0x03e7 1707 ------------------------------------------------------*/ 1708 union st_pd3 { /* union PD3 */ 1709 struct { /* Bit Access */ 1710 unsigned char PD3_0:1;/* Port P30 direction register */ 1711 unsigned char PD3_1:1;/* Port P31 direction register */ 1712 unsigned char PD3_2:1;/* Port P32 direction register */ 1713 unsigned char PD3_3:1;/* Port P33 direction register */ 1714 unsigned char PD3_4:1;/* Port P34 direction register */ 1715 unsigned char PD3_5:1;/* Port P35 direction register */ 1716 unsigned char PD3_6:1;/* Port P36 direction register */ 1717 unsigned char PD3_7:1;/* Port P37 direction register */ 1718 } BIT; /* */ 1719 unsigned char BYTE; /* Byte Access */ 1720 }; /* */ 1721 1722 /*------------------------------------------------------ 1723 Port P4 register //0x03e8 1724 ------------------------------------------------------*/ 1725 union st_p4 { /* union P4 */ 1726 struct { /* Bit Access */ 1727 unsigned char P4_0:1;/* Port P40 register */ 1728 unsigned char P4_1:1;/* Port P41 register */ 1729 unsigned char P4_2:1;/* Port P42 register */ 1730 unsigned char P4_3:1;/* Port P43 register */ 1731 unsigned char P4_4:1;/* Port P44 register */ 1732 unsigned char P4_5:1;/* Port P45 register */ 1733 unsigned char P4_6:1;/* Port P46 register */ 1734 unsigned char P4_7:1;/* Port P47 register */ 1735 } BIT; /* */ 1736 unsigned char BYTE; /* Byte Access */ 1737 }; /* */ 1738 1739 /*------------------------------------------------------ 1740 Port P5 register //0x03e9 1741 ------------------------------------------------------*/ 1742 union st_p5 { /* union P5 */ 1743 struct { /* Bit Access */ 1744 unsigned char P5_0:1;/* Port P50 register */ 1745 unsigned char P5_1:1;/* Port P51 register */ 1746 unsigned char P5_2:1;/* Port P52 register */ 1747 unsigned char P5_3:1;/* Port P53 register */ 1748 unsigned char P5_4:1;/* Port P54 register */ 1749 unsigned char P5_5:1;/* Port P55 register */ 1750 unsigned char P5_6:1;/* Port P56 register */ 1751 unsigned char P5_7:1;/* Port P57 register */ 1752 } BIT; /* */ 1753 unsigned char BYTE; /* Byte Access */ 1754 }; /* */ 1755 1756 1757 /*------------------------------------------------------ 1758 Port P4 direction register //0x03ea 1759 ------------------------------------------------------*/ 1760 union st_pd4 { /* union PD4 */ 1761 struct { /* Bit Access */ 1762 unsigned char PD4_0:1;/* Port P40 direction register */ 1763 unsigned char PD4_1:1;/* Port P41 direction register */ 1764 unsigned char PD4_2:1;/* Port P42 direction register */ 1765 unsigned char PD4_3:1;/* Port P43 direction register */ 1766 unsigned char PD4_4:1;/* Port P44 direction register */ 1767 unsigned char PD4_5:1;/* Port P45 direction register */ 1768 unsigned char PD4_6:1;/* Port P46 direction register */ 1769 unsigned char PD4_7:1;/* Port P47 direction register */ 1770 } BIT; /* */ 1771 unsigned char BYTE; /* Byte Access */ 1772 }; /* */ 1773 1774 1775 1776 /*------------------------------------------------------ 1777 Port P5 direction register //0x03eb 1778 ------------------------------------------------------*/ 1779 union st_pd5 { /* union PD5 */ 1780 struct { /* Bit Access */ 1781 unsigned char PD5_0:1;/* Port P50 direction register */ 1782 unsigned char PD5_1:1;/* Port P51 direction register */ 1783 unsigned char PD5_2:1;/* Port P52 direction register */ 1784 unsigned char PD5_3:1;/* Port P53 direction register */ 1785 unsigned char PD5_4:1;/* Port P54 direction register */ 1786 unsigned char PD5_5:1;/* Port P55 direction register */ 1787 unsigned char PD5_6:1;/* Port P56 direction register */ 1788 unsigned char PD5_7:1;/* Port P57 direction register */ 1789 } BIT; /* */ 1790 unsigned char BYTE; /* Byte Access */ 1791 }; /* */ 1792 1793 /*------------------------------------------------------ 1794 Port P6 register //0x03ec 1795 ------------------------------------------------------*/ 1796 union st_p6 { /* union P6 */ 1797 struct { /* Bit Access */ 1798 unsigned char P6_0:1;/* Port P60 register */ 1799 unsigned char P6_1:1;/* Port P61 register */ 1800 unsigned char P6_2:1;/* Port P62 register */ 1801 unsigned char P6_3:1;/* Port P63 register */ 1802 unsigned char P6_4:1;/* Port P64 register */ 1803 unsigned char P6_5:1;/* Port P65 register */ 1804 unsigned char P6_6:1;/* Port P66 register */ 1805 unsigned char P6_7:1;/* Port P67 register */ 1806 } BIT; /* */ 1807 unsigned char BYTE; /* Byte Access */ 1808 }; /* */ 1809 1810 /*------------------------------------------------------ 1811 Port P7 register //0x03ed 1812 ------------------------------------------------------*/ 1813 union st_p7 { /* union P7 */ 1814 struct { /* Bit Access */ 1815 unsigned char P7_0:1;/* Port P70 register */ 1816 unsigned char P7_1:1;/* Port P71 register */ 1817 unsigned char P7_2:1;/* Port P72 register */ 1818 unsigned char P7_3:1;/* Port P73 register */ 1819 unsigned char P7_4:1;/* Port P74 register */ 1820 unsigned char P7_5:1;/* Port P75 register */ 1821 unsigned char P7_6:1;/* Port P76 register */ 1822 unsigned char P7_7:1;/* Port P77 register */ 1823 } BIT; /* */ 1824 unsigned char BYTE; /* Byte Access */ 1825 }; /* */ 1826 1827 1828 /*------------------------------------------------------ 1829 Port P6 direction register //0x03ee 1830 ------------------------------------------------------*/ 1831 union st_pd6 { /* union PD6 */ 1832 struct { /* Bit Access */ 1833 unsigned char PD6_0:1;/* Port P60 direction register */ 1834 unsigned char PD6_1:1;/* Port P61 direction register */ 1835 unsigned char PD6_2:1;/* Port P62 direction register */ 1836 unsigned char PD6_3:1;/* Port P63 direction register */ 1837 unsigned char PD6_4:1;/* Port P64 direction register */ 1838 unsigned char PD6_5:1;/* Port P65 direction register */ 1839 unsigned char PD6_6:1;/* Port P66 direction register */ 1840 unsigned char PD6_7:1;/* Port P67 direction register */ 1841 } BIT; /* */ 1842 unsigned char BYTE; /* Byte Access */ 1843 }; /* */ 1844 1845 1846 /*------------------------------------------------------ 1847 Port P7 direction register //0x03ef 1848 ------------------------------------------------------*/ 1849 union st_pd7 { /* union PD7 */ 1850 struct { /* Bit Access */ 1851 unsigned char PD7_0:1;/* Port P70 direction register */ 1852 unsigned char PD7_1:1;/* Port P71 direction register */ 1853 unsigned char PD7_2:1;/* Port P72 direction register */ 1854 unsigned char PD7_3:1;/* Port P73 direction register */ 1855 unsigned char PD7_4:1;/* Port P74 direction register */ 1856 unsigned char PD7_5:1;/* Port P75 direction register */ 1857 unsigned char PD7_6:1;/* Port P76 direction register */ 1858 unsigned char PD7_7:1;/* Port P77 direction register */ 1859 } BIT; /* */ 1860 unsigned char BYTE; /* Byte Access */ 1861 }; /* */ 1862 1863 /*------------------------------------------------------ 1864 Port P8 register //0x03f0 1865 ------------------------------------------------------*/ 1866 union st_p8 { /* union P8 */ 1867 struct { /* Bit Access */ 1868 unsigned char P8_0:1;/* Port P80 register */ 1869 unsigned char P8_1:1;/* Port P81 register */ 1870 unsigned char P8_2:1;/* Port P82 register */ 1871 unsigned char P8_3:1;/* Port P83 register */ 1872 unsigned char P8_4:1;/* Port P84 register */ 1873 unsigned char P8_5:1;/* Port P85 register */ 1874 unsigned char P8_6:1;/* Port P86 register */ 1875 unsigned char P8_7:1;/* Port P87 register */ 1876 } BIT; /* */ 1877 unsigned char BYTE; /* Byte Access */ 1878 }; /* */ 1879 1880 /*------------------------------------------------------ 1881 Port P9 register //0x03f1 1882 ------------------------------------------------------*/ 1883 union st_p9 { /* union P9 */ 1884 struct { /* Bit Access */ 1885 unsigned char P9_0:1;/* Port P90 register */ 1886 unsigned char P9_1:1;/* Port P91 register */ 1887 unsigned char P9_2:1;/* Port P92 register */ 1888 unsigned char P9_3:1;/* Port P93 register */ 1889 unsigned char P9_4:1;/* Port P94 register */ 1890 unsigned char P9_5:1;/* Port P95 register */ 1891 unsigned char P9_6:1;/* Port P96 register */ 1892 unsigned char P9_7:1;/* Port P97 register */ 1893 } BIT; /* */ 1894 unsigned char BYTE; /* Byte Access */ 1895 }; /* */ 1896 1897 /*------------------------------------------------------ 1898 Port P8 direction register //0x03f2 1899 ------------------------------------------------------*/ 1900 union st_pd8 { /* union PD8 */ 1901 struct { /* Bit Access */ 1902 unsigned char PD8_0:1;/* Port P80 direction register */ 1903 unsigned char PD8_1:1;/* Port P81 direction register */ 1904 unsigned char PD8_2:1;/* Port P82 direction register */ 1905 unsigned char PD8_3:1;/* Port P83 direction register */ 1906 unsigned char PD8_4:1;/* Port P84 direction register */ 1907 unsigned char :1;/* Nothing assigned */ 1908 unsigned char PD8_6:1;/* Port P86 direction register */ 1909 unsigned char PD8_7:1;/* Port P87 direction register */ 1910 } BIT; /* */ 1911 unsigned char BYTE; /* Byte Access */ 1912 }; /* */ 1913 1914 1915 /*------------------------------------------------------ 1916 Port P9 direction register //0x03f3 1917 ------------------------------------------------------*/ 1918 union st_pd9 { /* union PD9 */ 1919 struct { /* Bit Access */ 1920 unsigned char PD9_0:1;/* Port P90 direction register */ 1921 unsigned char PD9_1:1;/* Port P91 direction register */ 1922 unsigned char PD9_2:1;/* Port P92 direction register */ 1923 unsigned char PD9_3:1;/* Port P93 direction register */ 1924 unsigned char PD9_4:1;/* Port P94 direction register */ 1925 unsigned char PD9_5:1;/* Port P95 direction register */ 1926 unsigned char PD9_6:1;/* Port P96 direction register */ 1927 unsigned char PD9_7:1;/* Port P97 direction register */ 1928 } BIT; /* */ 1929 unsigned char BYTE; /* Byte Access */ 1930 }; /* */ 1931 1932 /*------------------------------------------------------ 1933 Port P10 register //0x03f4 1934 ------------------------------------------------------*/ 1935 union st_p10 { /* union P10 */ 1936 struct { /* Bit Access */ 1937 unsigned char P10_0:1;/* Port P100 register */ 1938 unsigned char P10_1:1;/* Port P101 register */ 1939 unsigned char P10_2:1;/* Port P102 register */ 1940 unsigned char P10_3:1;/* Port P103 register */ 1941 unsigned char P10_4:1;/* Port P104 register */ 1942 unsigned char P10_5:1;/* Port P105 register */ 1943 unsigned char P10_6:1;/* Port P106 register */ 1944 unsigned char P10_7:1;/* Port P107 register */ 1945 } BIT; /* */ 1946 unsigned char BYTE; /* Byte Access */ 1947 }; /* */ 1948 1949 /*------------------------------------------------------ 1950 Port P11 register //0x03f5 1951 ------------------------------------------------------*/ 1952 union st_p11 { /* union P11 */ 1953 struct { /* Bit Access */ 1954 unsigned char P11_0:1;/* Port P110 register */ 1955 unsigned char P11_1:1;/* Port P111 register */ 1956 unsigned char P11_2:1;/* Port P112 register */ 1957 unsigned char P11_3:1;/* Port P113 register */ 1958 unsigned char P11_4:1;/* Port P114 register */ 1959 unsigned char P11_5:1;/* Port P115 register */ 1960 unsigned char P11_6:1;/* Port P116 register */ 1961 unsigned char P11_7:1;/* Port P117 register */ 1962 } BIT; /* */ 1963 unsigned char BYTE; /* Byte Access */ 1964 }; /* */ 1965 1966 /*------------------------------------------------------ 1967 Port P10 direction register //0x03f6 1968 ------------------------------------------------------*/ 1969 union st_pd10 { /* union PD10 */ 1970 struct { /* Bit Access */ 1971 unsigned char PD10_0:1;/* Port P100 direction register */ 1972 unsigned char PD10_1:1;/* Port P101 direction register */ 1973 unsigned char PD10_2:1;/* Port P102 direction register */ 1974 unsigned char PD10_3:1;/* Port P103 direction register */ 1975 unsigned char PD10_4:1;/* Port P104 direction register */ 1976 unsigned char PD10_5:1;/* Port P105 direction register */ 1977 unsigned char PD10_6:1;/* Port P106 direction register */ 1978 unsigned char PD10_7:1;/* Port P107 direction register */ 1979 } BIT; /* */ 1980 char BYTE; /* Byte Access */ 1981 }; /* */ 1982 1983 /*------------------------------------------------------ 1984 Port P11 direction register //0x03f7 1985 ------------------------------------------------------*/ 1986 union st_pd11 { /* union PD11 */ 1987 struct { /* Bit Access */ 1988 unsigned char PD11_0:1;/* Port P110 direction register */ 1989 unsigned char PD11_1:1;/* Port P111 direction register */ 1990 unsigned char PD11_2:1;/* Port P112 direction register */ 1991 unsigned char PD11_3:1;/* Port P113 direction register */ 1992 unsigned char PD11_4:1;/* Port P114 direction register */ 1993 unsigned char PD11_5:1;/* Port P115 direction register */ 1994 unsigned char PD11_6:1;/* Port P116 direction register */ 1995 unsigned char PD11_7:1;/* Port P117 direction register */ 1996 } BIT; /* */ 1997 char BYTE; /* Byte Access */ 1998 }; /* */ 1999 2000 /*------------------------------------------------------ 2001 Port P12 register //0x03f8 2002 ------------------------------------------------------*/ 2003 union st_p12 { /* union P12 */ 2004 struct { /* Bit Access */ 2005 unsigned char P12_0:1;/* Port P120 register */ 2006 unsigned char P12_1:1;/* Port P121 register */ 2007 unsigned char P12_2:1;/* Port P122 register */ 2008 unsigned char P12_3:1;/* Port P123 register */ 2009 unsigned char P12_4:1;/* Port P124 register */ 2010 unsigned char P12_5:1;/* Port P125 register */ 2011 unsigned char P12_6:1;/* Port P126 register */ 2012 unsigned char P12_7:1;/* Port P127 register */ 2013 } BIT; /* */ 2014 unsigned char BYTE; /* Byte Access */ 2015 }; /* */ 2016 2017 /*------------------------------------------------------ 2018 Port P13 register //0x03f9 2019 ------------------------------------------------------*/ 2020 union st_p13 { /* union P13 */ 2021 struct { /* Bit Access */ 2022 unsigned char P13_0:1;/* Port P130 register */ 2023 unsigned char P13_1:1;/* Port P131 register */ 2024 unsigned char P13_2:1;/* Port P132 register */ 2025 unsigned char P13_3:1;/* Port P133 register */ 2026 unsigned char P13_4:1;/* Port P134 register */ 2027 unsigned char P13_5:1;/* Port P135 register */ 2028 unsigned char P13_6:1;/* Port P136 register */ 2029 unsigned char P13_7:1;/* Port P137 register */ 2030 } BIT; /* */ 2031 unsigned char BYTE; /* Byte Access */ 2032 }; /* */ 2033 2034 /*------------------------------------------------------ 2035 Port P12 direction register //0x03fa 2036 ------------------------------------------------------*/ 2037 union st_pd12 { /* union PD12 */ 2038 struct { /* Bit Access */ 2039 unsigned char PD12_0:1;/* Port P120 direction register */ 2040 unsigned char PD12_1:1;/* Port P121 direction register */ 2041 unsigned char PD12_2:1;/* Port P122 direction register */ 2042 unsigned char PD12_3:1;/* Port P123 direction register */ 2043 unsigned char PD12_4:1;/* Port P124 direction register */ 2044 unsigned char PD12_5:1;/* Port P125 direction register */ 2045 unsigned char PD12_6:1;/* Port P126 direction register */ 2046 unsigned char PD12_7:1;/* Port P127 direction register */ 2047 } BIT; /* */ 2048 char BYTE; /* Byte Access */ 2049 }; /* */ 2050 2051 /*------------------------------------------------------ 2052 Port P13 direction register //0x03fb 2053 ------------------------------------------------------*/ 2054 union st_pd13 { /* union PD13 */ 2055 struct { /* Bit Access */ 2056 unsigned char PD13_0:1;/* Port P130 direction register */ 2057 unsigned char PD13_1:1;/* Port P131 direction register */ 2058 unsigned char PD13_2:1;/* Port P132 direction register */ 2059 unsigned char PD13_3:1;/* Port P133 direction register */ 2060 unsigned char PD13_4:1;/* Port P134 direction register */ 2061 unsigned char PD13_5:1;/* Port P135 direction register */ 2062 unsigned char PD13_6:1;/* Port P136 direction register */ 2063 unsigned char PD13_7:1;/* Port P137 direction register */ 2064 } BIT; /* */ 2065 char BYTE; /* Byte Access */ 2066 }; /* */ 2067 2068 /*------------------------------------------------------ 2069 Pull-up control register 0 //0x03fc 2070 ------------------------------------------------------*/ 2071 union st_pur0 { /* union PUR0 */ 2072 struct { /* Bit Access */ 2073 unsigned char PU00:1;/* P00 to P03 pull-up */ 2074 unsigned char PU01:1;/* P04 to P07 pull-up */ 2075 unsigned char PU02:1;/* P10 to P13 pull-up */ 2076 unsigned char PU03:1;/* P14 to P17 pull-up */ 2077 unsigned char PU04:1;/* P20 to P23 pull-up */ 2078 unsigned char PU05:1;/* P24 to P27 pull-up */ 2079 unsigned char PU06:1;/* P30 to P33 pull-up */ 2080 unsigned char PU07:1;/* P34 to P37 pull-up */ 2081 } BIT; /* */ 2082 unsigned char BYTE; /* Byte Access */ 2083 }; /* */ 2084 2085 /*------------------------------------------------------ 2086 Pull-up control register 1 //0x03fd 2087 ------------------------------------------------------*/ 2088 union st_pur1 { /* union PUR1 */ 2089 struct { /* Bit Access */ 2090 unsigned char PU10:1;/* P40 to P43 pull-up */ 2091 unsigned char PU11:1;/* P44 to P47 pull-up */ 2092 unsigned char PU12:1;/* P50 to P53 pull-up */ 2093 unsigned char PU13:1;/* P54 to P57 pull-up */ 2094 unsigned char PU14:1;/* P60 to P63 pull-up */ 2095 unsigned char PU15:1;/* P64 to P67 pull-up */ 2096 unsigned char PU16:1;/* P70 to P73 pull-up (Except P70,P71 ; P70,P71 -> N-channel open drain ports)*/ 2097 unsigned char PU17:1;/* P74 to P77 pull-up */ 2098 } BIT; /* */ 2099 unsigned char BYTE; /* Byte Access */ 2100 }; /* */ 2101 2102 /*------------------------------------------------------ 2103 Pull-up control register 2 //0x03fe 2104 ------------------------------------------------------*/ 2105 union st_pur2 { /* union PUR2 */ 2106 struct { /* Bit Access */ 2107 unsigned char PU20:1;/* P80 to P83 pull-up */ 2108 unsigned char PU21:1;/* P84 to P87 pull-up (Except P85) */ 2109 unsigned char PU22:1;/* P90 to P93 pull-up */ 2110 unsigned char PU23:1;/* P94 to P97 pull-up */ 2111 unsigned char PU24:1;/* P100 to P103 pull-up */ 2112 unsigned char PU25:1;/* P104 to P107 pull-up */ 2113 unsigned char :1;/* Nothing assigned */ 2114 unsigned char :1;/* Nothing assigned */ 2115 } BIT; /* */ 2116 unsigned char BYTE; /* Byte Access */ 2117 }; /* */ 2118 2119 /*------------------------------------------------------ 2120 Port control register //0x03ff 2121 ------------------------------------------------------*/ 2122 union st_pcr { /* union PCR2 */ 2123 struct { /* Bit Access */ 2124 unsigned char PCR0:1;/* Port P1 control register */ 2125 unsigned char :1;/* Nothing assigned */ 2126 unsigned char :1;/* Nothing assigned */ 2127 unsigned char :1;/* Nothing assigned */ 2128 unsigned char :1;/* Nothing assigned */ 2129 unsigned char :1;/* Nothing assigned */ 2130 unsigned char :1;/* Nothing assigned */ 2131 unsigned char :1;/* Nothing assigned */ 2132 } BIT; /* */ 2133 unsigned char BYTE; /* Byte Access */ 2134 }; /* */ 2135 2136 2137 2138 2139 /* Processor mode register 0 */ 2140 #define PM0 (*(volatile union st_pm0 *)(0x0004)) 2141 2142 /* Processor mode register 1 */ 2143 #define PM1 (*(volatile union st_pm1 *)(0x0005)) 2144 2145 /* System clock control register 0 */ 2146 #define CM0 (*(volatile union st_cm0 *)(0x0006)) 2147 2148 /* System clock control register 1 */ 2149 #define CM1 (*(volatile union st_cm1 *)(0x0007)) 2150 2151 /* Chip select control register */ 2152 #define CSR (*(volatile union st_csr *)(0x0008)) 2153 2154 /* Address match interrupt enable register */ 2155 #define AIER (*(volatile union st_aier *)(0x0009)) 2156 2157 /* Protect register */ 2158 #define PRCR (*(volatile union st_prcr *)(0x000A)) 2159 2160 /* Data bank register */ 2161 #define DBR (*(volatile union st_dbr *)(0x000B)) 2162 2163 /* Oscillation stop detection register */ 2164 #define CM2 (*(volatile union st_cm2 *)(0x000C)) 2165 2166 /* Watchdog timer start register */ 2167 #define WDTS (*(volatile char *)(0x000E)) 2168 2169 /* Watchdog timer control register */ 2170 #define WDC (*(volatile union st_wdc *)(0x000F)) 2171 2172 /* Address match interrupt register 0 */ 2173 #define RMAD0 (*(volatile union st_rmad0 *)(0x0010)) 2174 2175 /* Address match interrupt register 1 */ 2176 #define RMAD1 (*(volatile union st_rmad1 *)(0x0014)) 2177 2178 /* Voltage detection register 1 */ 2179 #define VCR1 (*(volatile union st_vcr1 *)(0x0019)) 2180 2181 /* Voltage detection register 2 */ 2182 #define VCR2 (*(volatile union st_vcr2 *)(0x001A)) 2183 2184 /* Chip select expansion control register */ 2185 #define CSE (*(volatile union st_cse *)(0x001B)) 2186 2187 /* PLC control register 0 */ 2188 #define PLC0 (*(volatile union st_plc0 *)(0x001C)) 2189 2190 /* Processor mode register 2 */ 2191 #define PM2 (*(volatile union st_pm2 *)(0x001E)) 2192 2193 /* Power supply down detection register */ 2194 #define D4INT (*(volatile union st_d4int *)(0x001F)) 2195 2196 /* DMA0 source pointer */ 2197 #define SAR0 (*(volatile union st_sar0 *)(0x0020)) 2198 2199 /* DMA0 destination pointer */ 2200 #define DAR0 (*(volatile union st_dar0 *)(0x0024)) 2201 2202 /* DMA0 transfer counter */ 2203 #define TCR0 (*(volatile union st_tcr0 *)(0x0028)) 2204 2205 /* DMA0 control register */ 2206 #define DM0CON (*(volatile union st_dm0con *)(0x002C)) 2207 2208 /* DMA1 source pointer */ 2209 #define SAR1 (*(volatile union st_sar1 *)(0x0030)) 2210 2211 /* DMA1 destination pointer */ 2212 #define DAR1 (*(volatile union st_dar1 *)(0x0034)) 2213 2214 /* DMA1 transfer counter */ 2215 #define TCR1 (*(volatile union st_tcr1 *)(0x0038)) 2216 2217 /* DMA1 control register */ 2218 #define DM1CON (*(volatile union st_dm1con *)(0x003c)) 2219 2220 2221 /* INT3~ interrupt control register */ 2222 #define INT3IC (*(volatile union st_icr *)(0x0044)) 2223 2224 /* Timer B5 interrupt control register */ 2225 #define TB5IC (*(volatile union st_icr1 *)(0x0045)) 2226 2227 /* Timer B4 interrupt control register */ 2228 #define TB4IC (*(volatile union st_icr1 *)(0x0046)) 2229 2230 /* Timer B3 interrupt control register */ 2231 #define TB3IC (*(volatile union st_icr1 *)(0x0047)) 2232 2233 /* UART1 BUS collision detection interrupt control register */ 2234 #define U1BCNIC (*(volatile union st_icr1 *)(0x0046)) 2235 2236 /* UART0 BUS collision detection interrupt control register */ 2237 #define U0BCNIC (*(volatile union st_icr1 *)(0x0047)) 2238 2239 /* SI/O4 interrupt control register */ 2240 #define S4IC (*(volatile union st_icr *)(0x0048)) 2241 2242 /* SI/O3 interrupt control register */ 2243 #define S3IC (*(volatile union st_icr *)(0x0049)) 2244 2245 /* INT5~ interrupt control register */ 2246 #define INT5IC (*(volatile union st_icr *)(0x0048)) 2247 2248 /* INT4~ interrupt control register */ 2249 #define INT4IC (*(volatile union st_icr *)(0x0049)) 2250 2251 /* Bus collision detection interrupt control register */ 2252 #define BCNIC (*(volatile union st_bcnic *)(0x004a)) 2253 2254 /* DMA0 interrupt control register */ 2255 #define DM0IC (*(volatile union st_dm0ic *)(0x004b)) 2256 2257 /* DMA1 interrupt control register */ 2258 #define DM1IC (*(volatile union st_icr1 *)(0x004c)) 2259 2260 /* Key input interrupt control register */ 2261 #define KUPIC (*(volatile union st_icr1 *)(0x004D)) 2262 2263 /* A/D conversion interrupt control register */ 2264 #define ADIC (*(volatile union st_icr1 *)(0x004E)) 2265 2266 /* UART2 transmit interrupt control register */ 2267 #define S2TIC (*(volatile union st_icr1 *)(0x004F)) 2268 2269 /* UART2 receive interrupt control register */ 2270 #define S2RIC (*(volatile union st_icr1 *)(0x0050)) 2271 2272 /* UART0 transmit interrupt control register */ 2273 #define S0TIC (*(volatile union st_icr1 *)(0x0051)) 2274 2275 /* UART0 receive interrupt control register */ 2276 #define S0RIC (*(volatile union st_icr1 *)(0x0052)) 2277 2278 /* UART1 transmit interrupt control register */ 2279 #define S1TIC (*(volatile union st_icr1 *)(0x0053)) 2280 2281 /* UART1 receive interrupt control register */ 2282 #define S1RIC (*(volatile union st_icr1 *)(0x0054)) 2283 2284 /* Timer A0 interrupt control register */ 2285 #define TA0IC (*(volatile union st_icr1 *)(0x0055)) 2286 2287 /* Timer A1 interrupt control register */ 2288 #define TA1IC (*(volatile union st_icr1 *)(0x0056)) 2289 2290 /* Timer A2 interrupt control register */ 2291 #define TA2IC (*(volatile union st_icr1 *)(0x0057)) 2292 2293 /* Timer A3 interrupt control register */ 2294 #define TA3IC (*(volatile union st_icr1 *)(0x0058)) 2295 2296 /* Timer A4 interrupt control register */ 2297 #define TA4IC (*(volatile union st_icr1 *)(0x0059)) 2298 2299 /* Timer B0 interrupt control register */ 2300 #define TB0IC (*(volatile union st_icr1 *)(0x005A)) 2301 2302 /* Timer B1 interrupt control register */ 2303 #define TB1IC (*(volatile union st_icr1 *)(0x005B)) 2304 2305 /* Timer B2 interrupt control register */ 2306 #define TB2IC (*(volatile union st_icr1 *)(0x005C)) 2307 2308 /* INT0~ interrupt control register */ 2309 #define INT0IC (*(volatile union st_icr *)(0x005D)) 2310 2311 /* INT1~ interrupt control register */ 2312 #define INT1IC (*(volatile union st_icr *)(0x005E)) 2313 2314 /* INT2~ interrupt control register */ 2315 #define INT2IC (*(volatile union st_icr *)(0x005F)) 2316 2317 /* Flash identification register */ 2318 #define FIDR (*(volatile union st_fidr *)(0x01b4)) 2319 2320 /* Flash memory control register 1 */ 2321 #define FMR1 (*(volatile union st_fmr1 *)(0x01b5)) 2322 2323 /* Flash memory control register 0 */ 2324 #define FMR0 (*(volatile union st_fmr0 *)(0x01b7)) 2325 2326 /* Address match interrupt register 2 */ 2327 #define RMAD2 (*(volatile union st_rmad2 *)(0x01b8)) 2328 2329 /* Address match interrupt enable register 2 */ 2330 #define AIER2 (*(volatile union st_aier2 *)(0x01bb)) 2331 2332 /* Address match interrupt register 3 */ 2333 #define RMAD3 (*(volatile union st_rmad3 *)(0x01bc)) 2334 2335 /* Peripheral clock select register */ 2336 #define PCLKR (*(volatile union st_pclkr *)(0x025e)) 2337 2338 /* Timer B3,4,5 count start flag */ 2339 #define TBSR (*(volatile union st_tbsr *)(0x0340)) 2340 2341 2342 /******************************************************** 2343 * declare SFR short * 2344 ********************************************************/ 2345 /*-------------------------------------------------------- 2346 Timer registers : Read and write data in 16-bit units. 2347 --------------------------------------------------------*/ 2348 2349 /* Timer A1-1 register */ 2350 #define TA1_1 (*(volatile unsigned short *)(0x0342)) 2351 2352 /* Timer A2-1 register */ 2353 #define TA2_1 (*(volatile unsigned short *)(0x0344)) 2354 2355 /* Timer A4-1 register */ 2356 #define TA4_1 (*(volatile unsigned short *)(0x0346)) 2357 2358 /* Three-phase PWM control regester 0 */ 2359 #define INVC0 (*(volatile union st_invc0 *)(0x0348)) 2360 2361 /* Three-phase PWM control register 1 */ 2362 #define INVC1 (*(volatile union st_invc1 *)(0x0349)) 2363 2364 /* Three-phase output buffer register 0 */ 2365 #define IDB0 (*(volatile union st_idb0 *)(0x034a)) 2366 2367 /* Three-phase output buffer register 1 */ 2368 #define IDB1 (*(volatile union st_idb1 *)(0x034b)) 2369 2370 /*------------------------------------------------------ 2371 Dead time timer ; Use "MOV" instruction when writing to this register. 2372 ------------------------------------------------------*/ 2373 /* Dead time timer */ 2374 #define DTT (*(volatile unsigned char *)(0x034c)) 2375 2376 /*------------------------------------------------------------------ 2377 Timer B2 interrupt occurrences frequency set counter 2378 ; Use "MOV" instruction when writing to this register. 2379 -------------------------------------------------------------------*/ 2380 /* Timer B2 interrupt occurrences frequency set counter */ 2381 #define ICTB2 (*(volatile unsigned char *)(0x034d)) 2382 2383 2384 /* Timer B3 register */ 2385 #define TB3 (*(volatile unsigned short *)(0x0350)) 2386 2387 /* Timer B4 register */ 2388 #define TB4 (*(volatile unsigned short *)(0x0352)) 2389 2390 /* Timer B5 register */ 2391 #define TB5 (*(volatile unsigned short *)(0x0354)) 2392 2393 /* Timer B3 mode register */ 2394 #define TB3MR (*(volatile union st_tmr *)(0x035b)) 2395 2396 /* Timer B4 mode register */ 2397 #define TB4MR (*(volatile union st_tmr *)(0x035c)) 2398 2399 /* Timer B5 mode register */ 2400 #define TB5MR (*(volatile union st_tmr *)(0x035d)) 2401 2402 /* Interrupt request cause select register 2 */ 2403 #define IFSR2A (*(volatile union st_ifsr2a *)(0x035e)) 2404 2405 /* Interrupt cause select register */ 2406 #define IFSR (*(volatile union st_ifsr *)(0x035f)) 2407 2408 /* SI/O3i transmit/receive register (i=3,4)*/ 2409 #define S3TRR (*(volatile unsigned char *)(0x0360)) 2410 2411 /* SI/O3 control register */ 2412 #define S3C (*(volatile union st_s3c *)(0x0362)) 2413 2414 2415 /* SI/O3 bit rate generator (Use "MOV" instruction when writing to these registers)*/ 2416 #define S3BRG (*(volatile unsigned char *)(0x0363)) 2417 2418 2419 /* SI/O4 transmit/receive register */ 2420 #define S4TRR (*(volatile unsigned char *)(0x0364)) 2421 2422 /* SI/O4 control register */ 2423 #define S4C (*(volatile union st_s4c *)(0x0366)) 2424 2425 /* SI/O4 bit rate generator */ 2426 #define S4BRG (*(volatile unsigned char *)(0x0367)) 2427 2428 /* UART0 special mode register 4 */ 2429 #define U0SMR4 (*(volatile union st_u0smr4 *)(0x036c)) 2430 2431 /* UART0 special mode register 3 */ 2432 #define U0SMR3 (*(volatile union st_u0smr3 *)(0x036d)) 2433 2434 2435 /* UART0 special mode register 2 */ 2436 #define U0SMR2 (*(volatile union st_u0smr2 *)(0x036e)) 2437 2438 /* UART0 special mode register */ 2439 #define U0SMR (*(volatile union st_u0smr *)(0x036f)) 2440 2441 /* UART1 special mode register 4 */ 2442 #define U1SMR4 (*(volatile union st_u1smr4 *)(0x0370)) 2443 2444 /* UART1 special mode register 3 */ 2445 #define U1SMR3 (*(volatile union st_u1smr3 *)(0x0371)) 2446 2447 /* UART1 special mode register 2 */ 2448 #define U1SMR2 (*(volatile union st_u1smr2 *)(0x0372)) 2449 2450 /* UART1 special mode register */ 2451 #define U1SMR (*(volatile union st_u1smr *)(0x0373)) 2452 2453 /* UART2 special mode register 4 */ 2454 #define U2SMR4 (*(volatile union st_u2smr4 *)(0x0374)) 2455 2456 /* UART2 special mode register 3 */ 2457 #define U2SMR3 (*(volatile union st_u2smr3 *)(0x0375)) 2458 2459 2460 /* UART2 special mode register 2 */ 2461 #define U2SMR2 (*(volatile union st_u2smr2 *)(0x0376)) 2462 2463 /* UART2 special mode register */ 2464 #define U2SMR (*(volatile union st_u2smr *)(0x0377)) 2465 2466 /* UART2 transmit/receive mode register */ 2467 #define U2MR (*(volatile union st_u2mr *)(0x0378)) 2468 2469 /* UART2 bit rate generator */ 2470 #define U2BRG (*(volatile unsigned char *)(0x0379)) 2471 2472 /* UART2 transmit buffer register */ 2473 #define U2TB (*(volatile union st_u2tb *)(0x037a)) 2474 2475 /* UART2 transmit/receive control register 0 */ 2476 //#pragma ADDRESS u2c0_addr 037cH 2477 #define U2C0 (*(volatile union st_u2c0 *)(0x037c)) 2478 2479 /* UART2 transmit/receive control register 1 */ 2480 #define U2C1 (*(volatile union st_u2c1 *)(0x037d)) 2481 2482 /* UART2 receive buffer register */ 2483 #define U2RB (*(volatile union st_u2rb *)(0x037e)) 2484 2485 /* Count start flag */ 2486 #define TABSR (*(volatile union st_tabsr *)(0x0380)) 2487 2488 /* Clock prescaler reset flag */ 2489 #define CPSRF (*(volatile union st_cpsrf *)(0x0381)) 2490 2491 2492 /* One-shot start flag */ 2493 #define ONSF (*(volatile union st_onsf *)(0x0382)) 2494 2495 2496 /* Trigger select register */ 2497 #define TRGSR (*(volatile union st_trgsr *)(0x0383)) 2498 2499 2500 /* Up/down flag (Use "MOV" instruction when writing to this register.)*/ 2501 #define UDF (*(volatile unsigned char *)(0x0384)) 2502 2503 /* Timer A0 register */ 2504 #define TA0 (*(volatile unsigned short *)(0x0386)) 2505 2506 /* Timer A1 register */ 2507 #define TA1 (*(volatile unsigned short *)(0x0388)) 2508 2509 /* Timer A2 register */ 2510 #define TA2 (*(volatile unsigned short *)(0x038a)) 2511 2512 /* Timer A3 register */ 2513 #define TA3 (*(volatile unsigned short *)(0x038c)) 2514 2515 /* Timer A4 register */ 2516 #define TA4 (*(volatile unsigned short *)(0x038e)) 2517 2518 /* Timer B0 register */ 2519 #define TB0 (*(volatile unsigned short *)(0x0390)) 2520 2521 /* Timer B1 register */ 2522 #define TB1 (*(volatile unsigned short *)(0x0392)) 2523 2524 /* Timer B2 register */ 2525 #define TB2 (*(volatile unsigned short *)(0x0394)) 2526 2527 2528 2529 /* Timer A0 mode register */ 2530 #define TA0MR (*(volatile union st_tmr *)(0x0396)) 2531 2532 /* Timer A1 mode register */ 2533 #define TA1MR (*(volatile union st_tmr *)(0x0397)) 2534 2535 /* Timer A2 mode register */ 2536 #define TA2MR (*(volatile union st_tmr *)(0x0398)) 2537 2538 /* Timer A3 mode register */ 2539 #define TA3MR (*(volatile union st_tmr *)(0x0399)) 2540 2541 /* Timer A4 mode register */ 2542 #define TA4MR (*(volatile union st_tmr *)(0x039A)) 2543 2544 /* Timer B0 mode register */ 2545 #define TB0MR (*(volatile union st_tmr *)(0x039b)) 2546 2547 /* Timer B1 mode register */ 2548 #define TB1MR (*(volatile union st_tmr *)(0x039c)) 2549 2550 /* Timer B2 mode register */ 2551 #define TB2MR (*(volatile union st_tmr *)(0x039d)) 2552 2553 /* Timer B2 special mode register */ 2554 #define TB2SC (*(volatile union st_tb2sc *)(0x039e)) 2555 2556 /* UART0 transmit/receive mode register */ 2557 #define U0MR (*(volatile union st_u0mr *)(0x03a0)) 2558 2559 /* UART0 bit rate generator (Use "MOV" instruction when writing to these registers.)*/ 2560 #define U0BRG (*(volatile unsigned char *)(0x03a1)) 2561 2562 /* UART0 transmit buffer register */ 2563 #define U0TB (*(volatile union st_u0tb *)(0x03a2)) 2564 2565 /* UART0 transmit/receive control register 0 */ 2566 #define U0C0 (*(volatile union st_u0c0 *)(0x03a4)) 2567 2568 /* UART0 transmit/receive control register 1 */ 2569 #define U0C1 (*(volatile union st_u0c1 *)(0x03a5)) 2570 2571 /* UART0 receive buffer register */ 2572 #define U0RB (*(volatile union st_u0rb *)(0x03a6)) 2573 2574 /* UART1 transmit/receive mode register */ 2575 #define U1MR (*(volatile union st_u1mr *)(0x03a8)) 2576 2577 /* UART1 bit rate generator */ 2578 #define U1BRG (*(volatile unsigned char *)(0x03a9)) 2579 2580 /* UART1 transmit buffer register */ 2581 #define U1TB (*(volatile union st_u1tb *)(0x03aa)) 2582 2583 /* UART1 transmit/receive control register 0 */ 2584 #define U1C0 (*(volatile union st_u1c0 *)(0x03ac)) 2585 2586 /* UART1 transmit/receive control register 1 */ 2587 #define U1C1 (*(volatile union st_u1c1 *)(0x03ad)) 2588 2589 /* UART1 receive buffer register */ 2590 #define U1RB (*(volatile union st_u1rb *)(0x03ae)) 2591 2592 /* UART transmit/receive control register 2 */ 2593 #define UCON (*(volatile union st_ucon *)(0x03b0)) 2594 2595 /* DMA0 cause select register */ 2596 #define DM0SL (*(volatile union st_dm0sl *)(0x03b8)) 2597 2598 /* DMA1 cause select register */ 2599 #define DM1SL (*(volatile union st_dm1sl *)(0x03ba)) 2600 2601 /* CRC data register */ 2602 #define CRCD (*(volatile union st_crcd *)(0x03bc)) 2603 2604 /* CRC input register */ 2605 #define CRCIN (*(volatile unsigned char *)(0x03be)) 2606 2607 /* A/D register 0 */ 2608 #define AD0 (*(volatile union st_ad0 *)(0x03c0)) 2609 2610 /* A/D register 1 */ 2611 #define AD1 (*(volatile union st_ad1 *)(0x03c2)) 2612 2613 /* A/D register 2 */ 2614 #define AD2 (*(volatile union st_ad2 *)(0x03c4)) 2615 2616 /* A/D register 3 */ 2617 #define AD3 (*(volatile union st_ad3 *)(0x03c6)) 2618 2619 /* A/D register 4 */ 2620 #define AD4 (*(volatile union st_ad4 *)(0x03c8)) 2621 2622 /* A/D register 5 */ 2623 #define AD5 (*(volatile union st_ad5 *)(0x03ca)) 2624 2625 /* A/D register 6 */ 2626 #define AD6 (*(volatile union st_ad6 *)(0x03cc)) 2627 2628 /* A/D register 7 */ 2629 #define AD7 (*(volatile union st_ad7 *)(0x03ce)) 2630 2631 /* A/D control register 2 */ 2632 #define ADCON2 (*(volatile union st_adcon2 *)(0x03d4)) 2633 2634 /* A/D control register 0 */ 2635 #define ADCON0 (*(volatile union st_adcon0 *)(0x03d6)) 2636 2637 /* A/D control register 1 */ 2638 #define ADCON1 (*(volatile union st_adcon1 *)(0x03d7)) 2639 2640 /* D/A register 0 */ 2641 #define DA0 (*(volatile unsigned char *)(0x03d8)) 2642 2643 /* D/A register 1 */ 2644 #define DA1 (*(volatile unsigned char *)(0x03da)) 2645 2646 /* D/A control register */ 2647 #define DACON (*(volatile union st_dacon *)(0x03dc)) 2648 2649 /* Port P14 control register */ 2650 #define PC14 (*(volatile union st_pc14 *)(0x03de)) 2651 2652 /* Pull-up control register 3 */ 2653 #define PUR3 (*(volatile union st_pur3 *)(0x03df)) 2654 2655 2656 /* Port P0 register */ 2657 #define P0 (*(volatile union st_p0 *)(0x03e0)) 2658 2659 /* Port P1 register */ 2660 #define P1 (*(volatile union st_p1 *)(0x03e1)) 2661 2662 /* Port P0 direction register */ 2663 #define PD0 (*(volatile union st_pd0 *)(0x03e2)) 2664 2665 /* Port P1 direction register */ 2666 #define PD1 (*(volatile union st_pd1 *)(0x03e3)) 2667 2668 /* Port P2 register */ 2669 #define P2 (*(volatile union st_p2 *)(0x03e4)) 2670 2671 /* Port P3 register */ 2672 #define P3 (*(volatile union st_p3 *)(0x03e5)) 2673 2674 /* Port P2 direction register */ 2675 #define PD2 (*(volatile union st_pd2 *)(0x03e6)) 2676 2677 /* Port P3 direction register */ 2678 #define PD3 (*(volatile union st_pd3 *)(0x03e7)) 2679 2680 2681 /* Port P4 register */ 2682 #define P4 (*(volatile union st_p4 *)(0x03e8)) 2683 2684 /* Port P5 register */ 2685 #define P5 (*(volatile union st_p5 *)(0x03e9)) 2686 2687 /* Port P4 direction register */ 2688 #define PD4 (*(volatile union st_pd4 *)(0x03ea)) 2689 2690 /* Port P5 direction register */ 2691 #define PD5 (*(volatile union st_pd5 *)(0x03eb)) 2692 2693 /* Port P6 register */ 2694 #define P6 (*(volatile union st_p6 *)(0x03ec)) 2695 2696 /* Port P7 register */ 2697 #define P7 (*(volatile union st_p7 *)(0x03ed)) 2698 2699 /* Port P6 direction register */ 2700 #define PD6 (*(volatile union st_pd6 *)(0x03ee)) 2701 2702 /* Port P7 direction register */ 2703 #define PD7 (*(volatile union st_pd7 *)(0x03ef)) 2704 2705 /* Port P8 register */ 2706 #define P8 (*(volatile union st_p8 *)(0x03f0)) 2707 2708 /* Port P9 register */ 2709 #define P9 (*(volatile union st_p9 *)(0x03f1)) 2710 2711 /* Port P8 direction register */ 2712 #define PD8 (*(volatile union st_pd8 *)(0x03f2)) 2713 2714 /* Port P9 direction register */ 2715 #define PD9 (*(volatile union st_pd9 *)(0x03f3)) 2716 2717 /* Port P10 register */ 2718 #define P10 (*(volatile union st_p10 *)(0x03f4)) 2719 2720 /* Port P11 register */ 2721 #define P11 (*(volatile union st_p11 *)(0x03f5)) 2722 2723 /* Port P10 direction register */ 2724 #define PD10 (*(volatile union st_pd10 *)(0x03f6)) 2725 2726 /* Port P11 direction register */ 2727 #define PD11 (*(volatile union st_pd11 *)(0x03f7)) 2728 2729 /* Port P12 register */ 2730 #define P12 (*(volatile union st_p12 *)(0x03f8)) 2731 2732 /* Port P13 register */ 2733 #define P13 (*(volatile union st_p13 *)(0x03f9)) 2734 2735 /* Port P12 direction register */ 2736 #define PD12 (*(volatile union st_pd12 *)(0x03fa)) 2737 2738 /* Port P13 direction register */ 2739 #define PD13 (*(volatile union st_pd13 *)(0x03f7)) 2740 2741 /* Pull-up control register 0 */ 2742 #define PUR0 (*(volatile union st_pur0 *)(0x03fc)) 2743 2744 /* Pull-up control register 1 */ 2745 #define PUR1 (*(volatile union st_pur1 *)(0x03fd)) 2746 2747 /* Pull-up control register 2 */ 2748 #define PUR2 (*(volatile union st_pur2 *)(0x03fe)) 2749 2750 /* Port control register */ 2751 #define PCR (*(volatile union st_pcr *)(0x03ff)) 2752 2753 2754 2755 2756 2757 2758